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generic: phy-mediatek-xfi-tphy: fix SGMII issue

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Fix issue of transmitting abnormal data which leads to link problems
in 1G and 2.5G SerDes modes (SGMII, 1000Base-X, 2500Base-X) on the
MediaTek MT7988 SoC.

Link: b72d6cba92
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2024-03-25 21:58:49 +00:00
parent 71ccb35017
commit 79e9ce354e
2 changed files with 4 additions and 2 deletions
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3
target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
View File

@ -102,7 +102,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
--- /dev/null --- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
@@ -0,0 +1,392 @@ @@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-License-Identifier: GPL-2.0-or-later
+/* MediaTek 10GE SerDes PHY driver +/* MediaTek 10GE SerDes PHY driver
+ * + *
@ -272,6 +272,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ XTP_PCS_PWD_ASYNC(2)); + XTP_PCS_PWD_ASYNC(2));
+ +
+ usleep_range(1, 5); + usleep_range(1, 5);
+ writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40);
+ +
+ /* Setup TX DA default value */ + /* Setup TX DA default value */
+ mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20); + mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);

3
target/linux/generic/pending-6.6/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
View File

@ -102,7 +102,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
--- /dev/null --- /dev/null
+++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
@@ -0,0 +1,392 @@ @@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0-or-later +// SPDX-License-Identifier: GPL-2.0-or-later
+/* MediaTek 10GE SerDes PHY driver +/* MediaTek 10GE SerDes PHY driver
+ * + *
@ -272,6 +272,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ XTP_PCS_PWD_ASYNC(2)); + XTP_PCS_PWD_ASYNC(2));
+ +
+ usleep_range(1, 5); + usleep_range(1, 5);
+ writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40);
+ +
+ /* Setup TX DA default value */ + /* Setup TX DA default value */
+ mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20); + mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);