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refresh 2.6.27 patches based on -rc9

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SVN-Revision: 12892
This commit is contained in:
Gabor Juhos 2008-10-07 12:29:33 +00:00
parent 901317f935
commit 73f2d150e3
11 changed files with 45 additions and 54 deletions
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4
include/kernel-version.mk
View File

@ -28,8 +28,8 @@ endif
ifeq ($(LINUX_VERSION),2.6.26.5)
LINUX_KERNEL_MD5SUM:=98261b39a558cf0739703ffea7db9f43
endif
ifeq ($(LINUX_VERSION),2.6.27-rc8)
LINUX_KERNEL_MD5SUM:=0fe739abe48e834a2ba664a2601328e6
ifeq ($(LINUX_VERSION),2.6.27-rc9)
LINUX_KERNEL_MD5SUM:=d78ffa904cc4a9c4eafd68ce55135198
endif
# disable the md5sum check for unknown kernel versions

2
target/linux/adm5120/patches-2.6.27/001-adm5120.patch
View File

@ -21,7 +21,7 @@
config MACH_ALCHEMY
bool "Alchemy processor based machines"
@@ -597,6 +611,7 @@
@@ -598,6 +612,7 @@
endchoice

2
target/linux/adm5120/patches-2.6.27/140-cmdline_hack.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -126,7 +126,12 @@
@@ -127,7 +127,12 @@
/*
* Reserved space for exception handlers.
* Necessary for machines which link their kernels at KSEG0.

2
target/linux/ar71xx/patches-2.6.27/300-mips_fw_myloader.patch
View File

@ -10,7 +10,7 @@
libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -781,6 +781,9 @@
@@ -782,6 +782,9 @@
config MIPS_DISABLE_OBSOLETE_IDE
bool

6
target/linux/ar71xx/patches-2.6.27/900-mips_multi_machine_support.patch
View File

@ -113,7 +113,7 @@
+
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -82,6 +82,7 @@
@@ -83,6 +83,7 @@
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
@ -123,7 +123,7 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -614,6 +614,7 @@
@@ -615,6 +615,7 @@
endchoice
@ -131,7 +131,7 @@
source "arch/mips/au1000/Kconfig"
source "arch/mips/basler/excite/Kconfig"
source "arch/mips/jazz/Kconfig"
@@ -787,6 +788,9 @@
@@ -788,6 +789,9 @@
config SYNC_R4K
bool

2
target/linux/ar71xx/patches-2.6.27/901-get_c0_compare_irq_function.patch
View File

@ -8,7 +8,7 @@
extern void check_wait(void);
extern asmlinkage void r4k_wait(void);
@@ -1482,6 +1483,8 @@
@@ -1484,6 +1485,8 @@
*/
if (cpu_has_mips_r2) {
cp0_compare_irq = (read_c0_intctl() >> 29) & 7;

73
target/linux/ar71xx/patches-2.6.27/902-mips_clocksource_init_war.patch
View File

@ -1,10 +1,9 @@
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -13,6 +13,22 @@
#include <asm/smtc_ipi.h>
#include <asm/time.h>
@@ -15,6 +15,22 @@
#include <asm/cevt-r4k.h>
+/*
/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register. 4 time the
@ -20,46 +19,38 @@
+ irq_disable_hazard(); \
+ } while (0)
+
static int mips_next_event(unsigned long delta,
struct clock_event_device *evt)
{
@@ -28,6 +44,7 @@
+/*
* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
* of these routines with SMTC-specific variants.
*/
@@ -30,6 +46,7 @@
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
+ compare_change_hazard();
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
#ifdef CONFIG_MIPS_MT_SMTC
evpe(vpflags);
@@ -187,7 +204,7 @@
*/
if (c0_compare_int_pending()) {
write_c0_compare(read_c0_count());
- irq_disable_hazard();
+ compare_change_hazard();
if (c0_compare_int_pending())
return 0;
}
@@ -196,7 +213,7 @@
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
- irq_disable_hazard();
+ compare_change_hazard();
if ((int)(read_c0_count() - cnt) < 0)
break;
/* increase delta if the timer was already expired */
@@ -205,11 +222,12 @@
while ((int)(read_c0_count() - cnt) <= 0)
; /* Wait for expiry */
+ compare_change_hazard();
if (!c0_compare_int_pending())
return 0;
write_c0_compare(read_c0_count());
- irq_disable_hazard();
+ compare_change_hazard();
if (c0_compare_int_pending())
return 0;
return res;
}
@@ -99,22 +116,6 @@
return (read_c0_cause() >> cp0_compare_irq) & 0x100;
}
-/*
- * Compare interrupt can be routed and latched outside the core,
- * so a single execution hazard barrier may not be enough to give
- * it time to clear as seen in the Cause register. 4 time the
- * pipeline depth seems reasonably conservative, and empirically
- * works better in configurations with high CPU/bus clock ratios.
- */
-
-#define compare_change_hazard() \
- do { \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- irq_disable_hazard(); \
- } while (0)
-
int c0_compare_int_usable(void)
{
unsigned int delta;

2
target/linux/generic-2.6/patches-2.6.27/011-mips_boot.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -120,6 +120,8 @@
@@ -121,6 +121,8 @@
#endif
.endm

2
target/linux/generic-2.6/patches-2.6.27/840-unable_to_open_console.patch
View File

@ -1,6 +1,6 @@
--- a/init/main.c
+++ b/init/main.c
@@ -802,7 +802,7 @@
@@ -801,7 +801,7 @@
numa_default_policy();
if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0)

2
target/linux/generic-2.6/patches-2.6.27/921-gpio_spi_driver.patch
View File

@ -362,7 +362,7 @@
obj-$(CONFIG_SPI_PXA2XX) += pxa2xx_spi.o
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3855,6 +3855,11 @@
@@ -3854,6 +3854,11 @@
W: http://www.ibm.com/developerworks/power/cell/
S: Supported

2
target/linux/generic-2.6/patches-2.6.27/922-gpiommc.patch
View File

@ -824,7 +824,7 @@
+be done automatically.
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1835,6 +1835,11 @@
@@ -1833,6 +1833,11 @@
W: http://gigaset307x.sourceforge.net/
S: Maintained