diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile index 944c942efc4..393e8c3a9f0 100644 --- a/package/boot/uboot-rockchip/Makefile +++ b/package/boot/uboot-rockchip/Makefile @@ -5,10 +5,10 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2020.07 -PKG_RELEASE:=3 +PKG_VERSION:=2021.01 +PKG_RELEASE:=1 -PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a +PKG_HASH:=b407e1510a74e863b8b5cb42a24625344f0e0c2fc7582d8c866bd899367d0454 PKG_MAINTAINER:=Tobias Maedel diff --git a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch index 4161c46ce20..bd401103eaf 100644 --- a/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch +++ b/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch @@ -17,7 +17,7 @@ Signed-off-by: David Bauer --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl -@@ -320,12 +320,6 @@ PHONY += dts_dir +@@ -321,12 +321,6 @@ PHONY += dts_dir dts_dir: $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) diff --git a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch index bc65fb69ef7..f2f63d8e363 100644 --- a/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ b/package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch @@ -28,7 +28,7 @@ Signed-off-by: David Bauer --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -106,6 +106,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ +@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ rk3328-evb.dtb \ diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c index fa42c1a7609..cf9411116be 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-platdata.c @@ -4,20 +4,15 @@ * This file was generated by dtoc from a .dtb (device tree binary) file. */ +/* Allow use of U_BOOT_DEVICE() in this file */ +#define DT_PLATDATA_C + #include #include #include -static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { - .reg = {0xff100000, 0x1000}, -}; -U_BOOT_DEVICE(syscon_at_ff100000) = { - .name = "rockchip_rk3328_grf", - .platdata = &dtv_syscon_at_ff100000, - .platdata_size = sizeof(dtv_syscon_at_ff100000), -}; - -static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { +/* Node /clock-controller@ff440000 index 0 */ +static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = { .reg = {0xff440000, 0x1000}, .rockchip_grf = 0x3a, }; @@ -25,94 +20,11 @@ U_BOOT_DEVICE(clock_controller_at_ff440000) = { .name = "rockchip_rk3328_cru", .platdata = &dtv_clock_controller_at_ff440000, .platdata_size = sizeof(dtv_clock_controller_at_ff440000), + .parent_idx = -1, }; -static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = { - .clock_frequency = 0x16e3600, - .clocks = { - {&dtv_clock_controller_at_ff440000, {40}}, - {&dtv_clock_controller_at_ff440000, {212}},}, - .dma_names = {"tx", "rx"}, - .dmas = {0x10, 0x6, 0x10, 0x7}, - .interrupts = {0x0, 0x39, 0x4}, - .pinctrl_0 = 0x26, - .pinctrl_names = "default", - .reg = {0xff130000, 0x100}, - .reg_io_width = 0x4, - .reg_shift = 0x2, -}; -U_BOOT_DEVICE(serial_at_ff130000) = { - .name = "rockchip_rk3328_uart", - .platdata = &dtv_serial_at_ff130000, - .platdata_size = sizeof(dtv_serial_at_ff130000), -}; - -static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = { - .bus_width = 0x4, - .cap_mmc_highspeed = true, - .cap_sd_highspeed = true, - .clocks = { - {&dtv_clock_controller_at_ff440000, {317}}, - {&dtv_clock_controller_at_ff440000, {33}}, - {&dtv_clock_controller_at_ff440000, {74}}, - {&dtv_clock_controller_at_ff440000, {78}},}, - .disable_wp = true, - .fifo_depth = 0x100, - .interrupts = {0x0, 0xc, 0x4}, - .max_frequency = 0x8f0d180, - .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, - .pinctrl_names = "default", - .reg = {0xff500000, 0x4000}, - .u_boot_spl_fifo_mode = true, - .vmmc_supply = 0x4b, - .vqmmc_supply = 0x1e, -}; -U_BOOT_DEVICE(mmc_at_ff500000) = { - .name = "rockchip_rk3328_dw_mshc", - .platdata = &dtv_mmc_at_ff500000, - .platdata_size = sizeof(dtv_mmc_at_ff500000), -}; - -static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { - .ranges = true, - .rockchip_grf = 0x3a, -}; -U_BOOT_DEVICE(pinctrl) = { - .name = "rockchip_rk3328_pinctrl", - .platdata = &dtv_pinctrl, - .platdata_size = sizeof(dtv_pinctrl), -}; - -static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { - .clocks = { - {&dtv_clock_controller_at_ff440000, {200}},}, - .gpio_controller = true, - .interrupt_controller = true, - .interrupts = {0x0, 0x33, 0x4}, - .reg = {0xff210000, 0x100}, -}; -U_BOOT_DEVICE(gpio0_at_ff210000) = { - .name = "rockchip_gpio_bank", - .platdata = &dtv_gpio0_at_ff210000, - .platdata_size = sizeof(dtv_gpio0_at_ff210000), -}; - -static const struct dtd_regulator_fixed dtv_sdmmc_regulator = { - .gpio = {0x60, 0x1e, 0x1}, - .pinctrl_0 = 0x61, - .pinctrl_names = "default", - .regulator_max_microvolt = 0x325aa0, - .regulator_min_microvolt = 0x325aa0, - .regulator_name = "vcc_sd", - .vin_supply = 0x1c, -}; -U_BOOT_DEVICE(sdmmc_regulator) = { - .name = "regulator_fixed", - .platdata = &dtv_sdmmc_regulator, - .platdata_size = sizeof(dtv_sdmmc_regulator), -}; - -static const struct dtd_rockchip_rk3328_dmc dtv_dmc = { +/* Node /dmc index 1 */ +static struct dtd_rockchip_rk3328_dmc dtv_dmc = { .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000, 0xff720000, 0x1000, 0xff798000, 0x1000}, .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0, @@ -145,5 +57,114 @@ U_BOOT_DEVICE(dmc) = { .name = "rockchip_rk3328_dmc", .platdata = &dtv_dmc, .platdata_size = sizeof(dtv_dmc), + .parent_idx = -1, }; +/* Node /pinctrl/gpio0@ff210000 index 2 */ +static struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = { + .clocks = { + {0, {200}},}, + .gpio_controller = true, + .interrupt_controller = true, + .interrupts = {0x0, 0x33, 0x4}, + .reg = {0xff210000, 0x100}, +}; +U_BOOT_DEVICE(gpio0_at_ff210000) = { + .name = "rockchip_gpio_bank", + .platdata = &dtv_gpio0_at_ff210000, + .platdata_size = sizeof(dtv_gpio0_at_ff210000), + .parent_idx = 4, +}; + +/* Node /mmc@ff500000 index 3 */ +static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = { + .bus_width = 0x4, + .cap_mmc_highspeed = true, + .cap_sd_highspeed = true, + .clocks = { + {0, {317}}, + {0, {33}}, + {0, {74}}, + {0, {78}},}, + .disable_wp = true, + .fifo_depth = 0x100, + .interrupts = {0x0, 0xc, 0x4}, + .max_frequency = 0x8f0d180, + .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a}, + .pinctrl_names = "default", + .reg = {0xff500000, 0x4000}, + .u_boot_spl_fifo_mode = true, + .vmmc_supply = 0x4b, + .vqmmc_supply = 0x1e, +}; +U_BOOT_DEVICE(mmc_at_ff500000) = { + .name = "rockchip_rk3288_dw_mshc", + .platdata = &dtv_mmc_at_ff500000, + .platdata_size = sizeof(dtv_mmc_at_ff500000), + .parent_idx = -1, +}; + +/* Node /pinctrl index 4 */ +static struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = { + .ranges = true, + .rockchip_grf = 0x3a, +}; +U_BOOT_DEVICE(pinctrl) = { + .name = "rockchip_rk3328_pinctrl", + .platdata = &dtv_pinctrl, + .platdata_size = sizeof(dtv_pinctrl), + .parent_idx = -1, +}; + +/* Node /sdmmc-regulator index 5 */ +static struct dtd_regulator_fixed dtv_sdmmc_regulator = { + .gpio = {0x60, 0x1e, 0x1}, + .pinctrl_0 = 0x61, + .pinctrl_names = "default", + .regulator_max_microvolt = 0x325aa0, + .regulator_min_microvolt = 0x325aa0, + .regulator_name = "vcc_sd", + .vin_supply = 0x1c, +}; +U_BOOT_DEVICE(sdmmc_regulator) = { + .name = "regulator_fixed", + .platdata = &dtv_sdmmc_regulator, + .platdata_size = sizeof(dtv_sdmmc_regulator), + .parent_idx = -1, +}; + +/* Node /serial@ff130000 index 6 */ +static struct dtd_ns16550_serial dtv_serial_at_ff130000 = { + .clock_frequency = 0x16e3600, + .clocks = { + {0, {40}}, + {0, {212}},}, + .dma_names = {"tx", "rx"}, + .dmas = {0x10, 0x6, 0x10, 0x7}, + .interrupts = {0x0, 0x39, 0x4}, + .pinctrl_0 = 0x26, + .pinctrl_names = "default", + .reg = {0xff130000, 0x100}, + .reg_io_width = 0x4, + .reg_shift = 0x2, +}; +U_BOOT_DEVICE(serial_at_ff130000) = { + .name = "ns16550_serial", + .platdata = &dtv_serial_at_ff130000, + .platdata_size = sizeof(dtv_serial_at_ff130000), + .parent_idx = -1, +}; + +/* Node /syscon@ff100000 index 7 */ +static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = { + .reg = {0xff100000, 0x1000}, +}; +U_BOOT_DEVICE(syscon_at_ff100000) = { + .name = "rockchip_rk3328_grf", + .platdata = &dtv_syscon_at_ff100000, + .platdata_size = sizeof(dtv_syscon_at_ff100000), + .parent_idx = -1, +}; + +void dm_populate_phandle_data(void) { +} diff --git a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h index 88291627b8c..6dcb4c1f1bc 100644 --- a/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h +++ b/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-structs-gen.h @@ -6,6 +6,18 @@ #include #include +struct dtd_ns16550_serial { + fdt32_t clock_frequency; + struct phandle_1_arg clocks[2]; + const char * dma_names[2]; + fdt32_t dmas[4]; + fdt32_t interrupts[3]; + fdt32_t pinctrl_0; + const char * pinctrl_names; + fdt64_t reg[2]; + fdt32_t reg_io_width; + fdt32_t reg_shift; +}; struct dtd_regulator_fixed { fdt32_t gpio[3]; fdt32_t pinctrl_0; @@ -22,15 +34,7 @@ struct dtd_rockchip_gpio_bank { fdt32_t interrupts[3]; fdt64_t reg[2]; }; -struct dtd_rockchip_rk3328_cru { - fdt64_t reg[2]; - fdt32_t rockchip_grf; -}; -struct dtd_rockchip_rk3328_dmc { - fdt64_t reg[12]; - fdt32_t rockchip_sdram_params[196]; -}; -struct dtd_rockchip_rk3328_dw_mshc { +struct dtd_rockchip_rk3288_dw_mshc { fdt32_t bus_width; bool cap_mmc_highspeed; bool cap_sd_highspeed; @@ -46,6 +50,14 @@ struct dtd_rockchip_rk3328_dw_mshc { fdt32_t vmmc_supply; fdt32_t vqmmc_supply; }; +struct dtd_rockchip_rk3328_cru { + fdt64_t reg[2]; + fdt32_t rockchip_grf; +}; +struct dtd_rockchip_rk3328_dmc { + fdt64_t reg[12]; + fdt32_t rockchip_sdram_params[196]; +}; struct dtd_rockchip_rk3328_grf { fdt64_t reg[2]; }; @@ -53,20 +65,3 @@ struct dtd_rockchip_rk3328_pinctrl { bool ranges; fdt32_t rockchip_grf; }; -struct dtd_rockchip_rk3328_uart { - fdt32_t clock_frequency; - struct phandle_1_arg clocks[2]; - const char * dma_names[2]; - fdt32_t dmas[4]; - fdt32_t interrupts[3]; - fdt32_t pinctrl_0; - const char * pinctrl_names; - fdt64_t reg[2]; - fdt32_t reg_io_width; - fdt32_t reg_shift; -}; -#define dtd_syscon dtd_rockchip_rk3328_cru -#define dtd_simple_mfd dtd_rockchip_rk3328_grf -#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart -#define dtd_rockchip_cru dtd_rockchip_rk3328_cru -#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc