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ar71xx: update QCA956x support
- separate qca956x and tp9343 (they use different IDs) - rename qca9561->qca956x for consistency - add missing bits (device reset, gpio output select) - fix wmac setup Signed-off-by: Roman Yeryomin <roman@advem.lv> SVN-Revision: 47981
This commit is contained in:
parent
3f78186f76
commit
67953f30f3
@ -129,7 +129,7 @@
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qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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+ else if (soc_is_qca956x())
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ qca956x_clocks_init();
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else
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BUG();
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@ -140,7 +140,7 @@
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x())
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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panic("Reset register not defined for this SOC");
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@ -149,20 +149,30 @@
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x())
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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panic("Reset register not defined for this SOC");
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@@ -133,6 +137,8 @@ u32 ath79_device_reset_get(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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BUG();
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--- a/arch/mips/ath79/dev-common.c
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+++ b/arch/mips/ath79/dev-common.c
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@@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
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@@ -94,7 +94,9 @@ void __init ath79_register_uart(void)
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soc_is_ar913x() ||
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soc_is_ar934x() ||
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soc_is_qca953x() ||
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- soc_is_qca955x()) {
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+ soc_is_qca955x() ||
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+ soc_is_qca956x()) {
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+ soc_is_qca956x() ||
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+ soc_is_tp9343()) {
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ath79_uart_data[0].uartclk = uart_clk_rate;
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platform_device_register(&ath79_uart_device);
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} else if (soc_is_ar933x()) {
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@ -192,14 +202,14 @@
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qca953x_usb_setup();
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else if (soc_is_qca955x())
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qca955x_usb_setup();
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+ else if (soc_is_qca9561())
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+ else if (soc_is_qca956x())
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+ qca956x_usb_setup();
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else
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BUG();
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}
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
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@@ -189,6 +189,26 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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@ -219,6 +229,8 @@
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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+
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+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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+}
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+
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static bool __init
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@ -228,7 +240,7 @@
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qca953x_wmac_setup();
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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+ else if (soc_is_qca956x())
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ qca956x_wmac_setup();
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else
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BUG();
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@ -240,27 +252,38 @@
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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+ case REV_ID_MAJOR_TP9343:
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+ case REV_ID_MAJOR_QCA9561:
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+ case REV_ID_MAJOR_QCA956X:
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_prom_putchar = prom_putchar_ar71xx;
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break;
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
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@@ -148,7 +148,10 @@ static void __iomem *ath79_gpio_get_func
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soc_is_ar913x() ||
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soc_is_ar933x())
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reg = AR71XX_GPIO_REG_FUNC;
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- else if (soc_is_ar934x() || soc_is_qca953x())
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+ else if (soc_is_ar934x() ||
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+ soc_is_qca953x() || soc_is_qca956x())
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+ soc_is_qca953x() ||
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+ soc_is_qca956x() ||
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+ soc_is_tp9343())
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reg = AR934X_GPIO_REG_FUNC;
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else
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BUG();
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@@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
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@@ -187,7 +190,7 @@ void __init ath79_gpio_output_select(uns
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unsigned int reg;
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u32 t, s;
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- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
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+ BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
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if (gpio >= AR934X_GPIO_COUNT)
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return;
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@@ -228,12 +231,15 @@ void __init ath79_gpio_init(void)
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ath79_gpio_count = QCA953X_GPIO_COUNT;
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else if (soc_is_qca955x())
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ath79_gpio_count = QCA955X_GPIO_COUNT;
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+ else if (soc_is_qca956x())
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ ath79_gpio_count = QCA956X_GPIO_COUNT;
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else
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BUG();
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@ -269,23 +292,24 @@
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ath79_gpio_chip.ngpio = ath79_gpio_count;
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- if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
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+ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
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+ soc_is_qca956x()) {
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+ soc_is_qca956x() || soc_is_tp9343()) {
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ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
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ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
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}
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
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@@ -107,7 +107,9 @@ static void __init ath79_misc_irq_init(v
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca953x() ||
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- soc_is_qca955x())
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+ soc_is_qca955x() ||
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+ soc_is_qca956x())
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+ soc_is_qca956x() ||
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+ soc_is_tp9343())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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@@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
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@@ -268,6 +270,97 @@ static void qca955x_irq_init(void)
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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@ -383,21 +407,21 @@
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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@@ -397,6 +489,9 @@ void __init arch_init_irq(void)
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@@ -397,6 +490,9 @@ void __init arch_init_irq(void)
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} else if (soc_is_qca955x()) {
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ath79_ip2_handler = ath79_default_ip2_handler;
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ath79_ip3_handler = ath79_default_ip3_handler;
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+ } else if (soc_is_qca956x()) {
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+ } else if (soc_is_qca956x() || soc_is_tp9343()) {
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+ ath79_ip2_handler = ath79_default_ip2_handler;
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+ ath79_ip3_handler = ath79_default_ip3_handler;
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} else {
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BUG();
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}
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@@ -410,4 +505,6 @@ void __init arch_init_irq(void)
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@@ -410,4 +506,6 @@ void __init arch_init_irq(void)
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qca953x_irq_init();
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else if (soc_is_qca955x())
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qca955x_irq_init();
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+ else if (soc_is_qca956x())
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ qca956x_irq_init();
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}
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--- a/arch/mips/ath79/pci.c
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@ -428,7 +452,7 @@
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} else if (soc_is_qca955x()) {
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ath79_pci_irq_map = qca955x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
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+ } else if (soc_is_qca9561()) {
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+ } else if (soc_is_qca956x()) {
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+ ath79_pci_irq_map = qca956x_pci_irq_map;
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+ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
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} else {
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@ -438,7 +462,7 @@
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QCA955X_PCI_MEM_SIZE,
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1,
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ATH79_IP3_IRQ(2));
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+ } else if (soc_is_qca9561()) {
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+ } else if (soc_is_qca956x()) {
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+ pdev = ath79_register_pci_ar724x(0,
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+ QCA956X_PCI_CFG_BASE1,
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+ QCA956X_PCI_CTRL_BASE1,
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@ -456,15 +480,15 @@
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_TP9343:
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+ ath79_soc = ATH79_SOC_TP9343;
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+ chip = "9343";
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+ case REV_ID_MAJOR_QCA956X:
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+ ath79_soc = ATH79_SOC_QCA956X;
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+ chip = "956X";
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+ rev = id & QCA956X_REV_ID_REVISION_MASK;
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+ break;
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+
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+ case REV_ID_MAJOR_QCA9561:
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+ ath79_soc = ATH79_SOC_QCA9561;
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+ chip = "9561";
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+ case REV_ID_MAJOR_TP9343:
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+ ath79_soc = ATH79_SOC_TP9343;
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+ chip = "9343";
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+ rev = id & QCA956X_REV_ID_REVISION_MASK;
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+ break;
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+
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@ -476,7 +500,7 @@
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ath79_soc_rev = rev;
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- if (soc_is_qca953x() || soc_is_qca955x())
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+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
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+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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chip, ver, rev);
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+ else if (soc_is_tp9343())
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@ -511,7 +535,21 @@
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#define AR9300_OTP_BASE 0x14000
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#define AR9300_OTP_STATUS 0x15f18
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#define AR9300_OTP_STATUS_TYPE 0x7
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@@ -375,6 +392,49 @@
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@@ -152,6 +169,13 @@
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#define AR9300_OTP_READ_DATA 0x15f1c
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/*
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+ * Hidden Registers
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+ */
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+#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
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+#define QCA956X_DAM_RESET_SIZE 0x4
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+#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
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+
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+/*
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* DDR_CTRL block
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*/
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#define AR71XX_DDR_REG_PCI_WIN0 0x7c
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@@ -375,6 +399,49 @@
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#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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@ -561,7 +599,7 @@
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/*
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* USB_CONFIG block
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*/
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@@ -422,6 +482,11 @@
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@@ -422,6 +489,11 @@
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#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
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#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
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@ -573,7 +611,7 @@
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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@@ -596,6 +661,8 @@
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@@ -596,6 +668,8 @@
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#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
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@ -582,7 +620,7 @@
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#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
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#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
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#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
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@@ -663,6 +730,37 @@
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@@ -663,6 +737,37 @@
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QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
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QCA955X_EXT_INT_PCIE_RC2_INT3)
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@ -620,16 +658,16 @@
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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@@ -678,6 +776,8 @@
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@@ -678,6 +783,8 @@
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#define REV_ID_MAJOR_QCA9533_V2 0x0160
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#define REV_ID_MAJOR_QCA9556 0x0130
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#define REV_ID_MAJOR_QCA9558 0x1130
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+#define REV_ID_MAJOR_TP9343 0x0150
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+#define REV_ID_MAJOR_QCA9561 0x1150
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+#define REV_ID_MAJOR_QCA956X 0x1150
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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@@ -702,6 +802,8 @@
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@@ -702,6 +809,8 @@
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#define QCA955X_REV_ID_REVISION_MASK 0xf
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@ -638,7 +676,7 @@
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/*
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* SPI block
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*/
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@@ -766,6 +868,19 @@
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@@ -766,6 +875,19 @@
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#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
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#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
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@ -658,7 +696,7 @@
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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@@ -774,6 +889,7 @@
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@@ -774,6 +896,7 @@
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#define AR934X_GPIO_COUNT 23
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#define QCA953X_GPIO_COUNT 18
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#define QCA955X_GPIO_COUNT 24
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@ -673,11 +711,11 @@
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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+ ATH79_SOC_TP9343,
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+ ATH79_SOC_QCA9561,
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+ ATH79_SOC_QCA956X,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
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@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
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return soc_is_qca9556() || soc_is_qca9558();
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}
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@ -688,12 +726,17 @@
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+
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+static inline int soc_is_qca9561(void)
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+{
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+ return ath79_soc == ATH79_SOC_QCA9561;
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+ return ath79_soc == ATH79_SOC_QCA956X;
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+}
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+
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+static inline int soc_is_qca9563(void)
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+{
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+ return ath79_soc == ATH79_SOC_QCA956X;
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+}
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+
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+static inline int soc_is_qca956x(void)
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+{
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+ return soc_is_tp9343() || soc_is_qca9561();
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+ return soc_is_qca9561() || soc_is_qca9563();
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+}
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+
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extern void __iomem *ath79_ddr_base;
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@ -1,6 +1,6 @@
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--- a/arch/mips/ath79/gpio.c
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+++ b/arch/mips/ath79/gpio.c
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@@ -221,15 +221,27 @@ void __init ath79_gpio_output_select(uns
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@@ -221,15 +221,30 @@ void __init ath79_gpio_output_select(uns
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{
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void __iomem *base = ath79_gpio_base;
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unsigned long flags;
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@ -9,7 +9,7 @@
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+ unsigned long gpio_count;
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u32 t, s;
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- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
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- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x() && !soc_is_qca956x());
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+ if (soc_is_ar934x()) {
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+ gpio_count = AR934X_GPIO_COUNT;
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+ reg_base = AR934X_GPIO_REG_OUT_FUNC0;
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@ -19,6 +19,9 @@
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+ } else if (soc_is_qca955x()) {
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+ gpio_count = QCA955X_GPIO_COUNT;
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+ reg_base = QCA955X_GPIO_REG_OUT_FUNC0;
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+ } else if (soc_is_qca956x()) {
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+ gpio_count = QCA956X_GPIO_COUNT;
|
||||
+ reg_base = QCA956X_GPIO_REG_OUT_FUNC0;
|
||||
+ } else {
|
||||
+ BUG();
|
||||
+ }
|
||||
|
Loading…
Reference in New Issue
Block a user