mirror of
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mediatek: various fixes for v4.9
* adds MT7530 DSA support * backport latest ethernet driver * add PMIC leds * add auxadc support * add efuse support * add thermal sensor support * add irq affinity support for ethernet still todo * DSA multi cpu support Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
43d06ec2c7
commit
64175ffb79
@ -16,7 +16,7 @@ KERNELNAME:=Image dtbs zImage
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include $(INCLUDE_DIR)/target.mk
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += \
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DEFAULT_PACKAGES += \
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kmod-mt76 kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
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kmod-mt76 kmod-leds-gpio kmod-gpio-button-hotplug \
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wpad-mini
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wpad-mini
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$(eval $(call BuildTarget))
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$(eval $(call BuildTarget))
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@ -1,7 +1,6 @@
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#!/bin/sh
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#!/bin/sh
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. /lib/functions.sh
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. /lib/functions.sh
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. /lib/mediatek.sh
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. /lib/functions/uci-defaults.sh
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. /lib/functions/uci-defaults.sh
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. /lib/functions/system.sh
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. /lib/functions/system.sh
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@ -10,18 +9,16 @@ mediatek_setup_interfaces()
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local board="$1"
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local board="$1"
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case $board in
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case $board in
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eMMC | \
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'mediatek,mt7623-rfb-emmc' | \
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NAND | \
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'mediatek,mt7623-rfb-nand')
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mt7623_evb)
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ucidef_set_interface_lan "lan1 lan2 lan3 lan4"
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ucidef_set_interfaces_lan_wan "eth0.1" "eth1.2"
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ucidef_set_interface_wan wan
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ucidef_add_switch "switch0" \
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"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6@eth0" "5@eth1"
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;;
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;;
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esac
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esac
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}
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}
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board_config_update
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board_config_update
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board=$(mediatek_board_name)
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board=$(board_name)
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mediatek_setup_interfaces $board
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mediatek_setup_interfaces $board
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board_config_flush
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board_config_flush
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@ -1,39 +0,0 @@
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#!/bin/sh
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#
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# Copyright (C) 2016 OpenWrt.org
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#
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mediatek_board_detect() {
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local machine
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local name
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machine=$(cat /proc/device-tree/model)
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case "$machine" in
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"MediaTek MT7623 evaluation board")
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name="mt7623_evb"
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;;
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"MediaTek MT7623 eMMC evaluation board")
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name="eMMC"
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;;
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"MediaTek MT7623 NAND evaluation board")
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name="NAND"
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;;
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esac
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[ -z "$name" ] && name="unknown"
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[ -e "/tmp/sysinfo/" ] || mkdir -p "/tmp/sysinfo/"
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echo "$name" > /tmp/sysinfo/board_name
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echo "$machine" > /tmp/sysinfo/model
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}
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mediatek_board_name() {
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local name
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[ -f /tmp/sysinfo/board_name ] && name=$(cat /tmp/sysinfo/board_name)
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[ -z "$name" ] && name="unknown"
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echo "$name"
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}
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@ -1,4 +0,0 @@
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#!/bin/sh
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echo 4 > /proc/irq/32/smp_affinity
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echo 8 > /proc/irq/33/smp_affinity
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@ -1,12 +0,0 @@
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#!/bin/sh
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#
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# Copyright (c) 2014 The Linux Foundation. All rights reserved.
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#
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do_mediatek() {
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. /lib/mediatek.sh
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mediatek_board_detect
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}
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boot_hook_add preinit_main do_mediatek
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@ -0,0 +1,9 @@
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#!/bin/sh
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set_preinit_iface() {
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ifconfig eth0 up
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ifname=lan1
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}
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boot_hook_add preinit_main set_preinit_iface
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@ -60,7 +60,7 @@ CONFIG_CLKSRC_MMIO=y
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CONFIG_CLKSRC_OF=y
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CONFIG_CLKSRC_OF=y
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CONFIG_CLKSRC_PROBE=y
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CONFIG_CLKSRC_PROBE=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 block2mtd.block2mtd=/dev/mmcblk0,65536,eMMC,5 mtdparts=eMMC:256k(mbr)ro,512k(uboot)ro,256k(config)ro,256k(factory)ro,32M(kernel),32M(recovery),1024M(rootfs),2048M(usrdata),-(bmtpool) rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2"
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CONFIG_CMDLINE_FORCE=y
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CONFIG_CMDLINE_FORCE=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_MEDIATEK=y
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CONFIG_COMMON_CLK_MEDIATEK=y
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@ -95,6 +95,7 @@ CONFIG_CPU_HAS_ASID=y
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_RMAP=y
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# CONFIG_CPU_THERMAL is not set
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_V7=y
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CONFIG_CPU_V7=y
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CONFIG_CRC16=y
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CONFIG_CRC16=y
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@ -217,6 +218,9 @@ CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_MT65XX=y
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CONFIG_I2C_MT65XX=y
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CONFIG_IIO=y
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# CONFIG_IIO_BUFFER is not set
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# CONFIG_IIO_TRIGGER is not set
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CONFIG_INITRAMFS_ROOT_GID=1000
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CONFIG_INITRAMFS_ROOT_GID=1000
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CONFIG_INITRAMFS_ROOT_UID=1000
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CONFIG_INITRAMFS_ROOT_UID=1000
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CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
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CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-arm_cortex-a7_musl-1.1.14_eabi/root-mediatek /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
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@ -230,6 +234,7 @@ CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_IRQ_WORK=y
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CONFIG_KALLSYMS=y
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CONFIG_KALLSYMS=y
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CONFIG_LEDS_MT6323=y
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CONFIG_LIBFDT=y
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CONFIG_LIBFDT=y
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CONFIG_LOCKUP_DETECTOR=y
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CONFIG_LOCKUP_DETECTOR=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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CONFIG_LOCK_SPIN_ON_OWNER=y
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@ -245,8 +250,7 @@ CONFIG_MAGIC_SYSRQ=y
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CONFIG_MDIO_BITBANG=y
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CONFIG_MDIO_BITBANG=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MDIO_BOARDINFO=y
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CONFIG_MDIO_GPIO=y
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CONFIG_MDIO_GPIO=y
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# CONFIG_MTK_EFUSE is not set
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CONFIG_MEDIATEK_MT6577_AUXADC=y
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# CONFIG_MEDIATEK_MT6577_AUXADC is not set
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CONFIG_MEDIATEK_WATCHDOG=y
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CONFIG_MEDIATEK_WATCHDOG=y
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CONFIG_MFD_CORE=y
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CONFIG_MFD_CORE=y
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# CONFIG_MFD_MAX77620 is not set
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# CONFIG_MFD_MAX77620 is not set
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@ -278,18 +282,25 @@ CONFIG_MTD_UBI_BLOCK=y
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# CONFIG_MTD_UBI_FASTMAP is not set
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# CONFIG_MTD_UBI_FASTMAP is not set
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# CONFIG_MTD_UBI_GLUEBI is not set
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# CONFIG_MTD_UBI_GLUEBI is not set
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CONFIG_MTD_UBI_WL_THRESHOLD=4096
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CONFIG_MTD_UBI_WL_THRESHOLD=4096
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CONFIG_MTK_EFUSE=y
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CONFIG_MTK_INFRACFG=y
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CONFIG_MTK_INFRACFG=y
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# CONFIG_MTK_IOMMU is not set
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# CONFIG_MTK_IOMMU is not set
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# CONFIG_MTK_IOMMU_V1 is not set
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# CONFIG_MTK_IOMMU_V1 is not set
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CONFIG_MTK_PMIC_WRAP=y
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CONFIG_MTK_PMIC_WRAP=y
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CONFIG_MTK_SCPSYS=y
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CONFIG_MTK_SCPSYS=y
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CONFIG_MTK_THERMAL=y
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CONFIG_MTK_TIMER=y
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CONFIG_MTK_TIMER=y
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CONFIG_MULTI_IRQ_HANDLER=y
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CONFIG_MULTI_IRQ_HANDLER=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_DMA_MAP_STATE=y
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# CONFIG_NEON is not set
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# CONFIG_NEON is not set
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CONFIG_NET_DSA=y
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# CONFIG_NET_DSA_HWMON is not set
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CONFIG_NET_DSA_MT7530=y
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CONFIG_NET_DSA_TAG_MTK=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_MEDIATEK_SOC=y
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CONFIG_NET_MEDIATEK_SOC=y
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CONFIG_NET_SWITCHDEV=y
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# CONFIG_NET_VENDOR_AURORA is not set
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# CONFIG_NET_VENDOR_AURORA is not set
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CONFIG_NET_VENDOR_MEDIATEK=y
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CONFIG_NET_VENDOR_MEDIATEK=y
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# CONFIG_NET_VENDOR_WIZNET is not set
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# CONFIG_NET_VENDOR_WIZNET is not set
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@ -299,6 +310,7 @@ CONFIG_NO_HZ=y
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CONFIG_NO_HZ_COMMON=y
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CONFIG_NO_HZ_COMMON=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_NO_HZ_IDLE=y
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CONFIG_NR_CPUS=4
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CONFIG_NR_CPUS=4
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CONFIG_NVMEM=y
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CONFIG_OF=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_ADDRESS_PCI=y
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CONFIG_OF_ADDRESS_PCI=y
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@ -403,6 +415,10 @@ CONFIG_SWIOTLB=y
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CONFIG_SWPHY=y
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CONFIG_SWPHY=y
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CONFIG_SWP_EMULATE=y
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CONFIG_SWP_EMULATE=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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CONFIG_THERMAL=y
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CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
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CONFIG_THERMAL_GOV_STEP_WISE=y
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CONFIG_THERMAL_OF=y
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# CONFIG_THUMB2_KERNEL is not set
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# CONFIG_THUMB2_KERNEL is not set
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TIMER_STATS=y
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CONFIG_TIMER_STATS=y
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@ -151,7 +151,7 @@
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};
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};
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pio: pinctrl@10005000 {
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt7623-pinctrl";
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compatible = "mediatek,mt2701-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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pins-are-numbered;
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@ -165,7 +165,9 @@
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};
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};
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syscfg_pctl_a: syscfg@10005000 {
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syscfg_pctl_a: syscfg@10005000 {
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compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
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compatible = "mediatek,mt7623-pctl-a-syscfg",
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"mediatek,mt2701-pctl-a-syscfg",
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"syscon";
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reg = <0 0x10005000 0 0x1000>;
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reg = <0 0x10005000 0 0x1000>;
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};
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};
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@ -176,8 +178,9 @@
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reg = <0 0x10006000 0 0x1000>;
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reg = <0 0x10006000 0 0x1000>;
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infracfg = <&infracfg>;
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infracfg = <&infracfg>;
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clocks = <&clk26m>,
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clocks = <&clk26m>,
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<&topckgen CLK_TOP_MM_SEL>;
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<&topckgen CLK_TOP_MM_SEL>,
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clock-names = "mfg", "mm";
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<&topckgen CLK_TOP_ETHIF_SEL>;
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clock-names = "mfg", "mm", "ethif";
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};
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};
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watchdog: watchdog@10007000 {
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watchdog: watchdog@10007000 {
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@ -217,6 +220,19 @@
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reg = <0 0x10200100 0 0x1c>;
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reg = <0 0x10200100 0 0x1c>;
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};
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};
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7623-efuse",
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"mediatek,efuse";
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reg = <0 0x10206000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* Data cells */
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thermal_calibration: calib@424 {
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reg = <0x424 0xc>;
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};
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};
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apmixedsys: apmixedsys@10209000 {
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt7623-apmixedsys",
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compatible = "mediatek,mt7623-apmixedsys",
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"mediatek,mt2701-apmixedsys";
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"mediatek,mt2701-apmixedsys";
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@ -235,49 +251,13 @@
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<0 0x10216000 0 0x2000>;
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<0 0x10216000 0 0x2000>;
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};
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};
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i2c0: i2c@11007000 {
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auxadc: adc@11001000 {
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compatible = "mediatek,mt7623-i2c",
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compatible = "mediatek,mt7623-auxadc",
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"mediatek,mt6577-i2c";
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"mediatek,mt2701-auxadc";
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reg = <0 0x11007000 0 0x70>,
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reg = <0 0x11001000 0 0x1000>;
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<0 0x11000200 0 0x80>;
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clocks = <&pericfg CLK_PERI_AUXADC>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
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clock-names = "main";
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clock-div = <16>;
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#io-channel-cells = <1>;
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clocks = <&pericfg CLK_PERI_I2C0>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@11008000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11008000 0 0x70>,
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<0 0x11000280 0 0x80>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C1>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@11009000 {
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compatible = "mediatek,mt7623-i2c",
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"mediatek,mt6577-i2c";
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reg = <0 0x11009000 0 0x70>,
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<0 0x11000300 0 0x80>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
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clock-div = <16>;
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clocks = <&pericfg CLK_PERI_I2C2>,
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<&pericfg CLK_PERI_AP_DMA>;
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clock-names = "main", "dma";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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||||||
};
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};
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uart0: serial@11002000 {
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uart0: serial@11002000 {
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@ -328,7 +308,6 @@
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compatible = "mediatek,mt7623-pwm";
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compatible = "mediatek,mt7623-pwm";
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reg = <0 0x11006000 0 0x1000>;
|
reg = <0 0x11006000 0 0x1000>;
|
||||||
|
|
||||||
resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
|
resets = <&pericfg MT2701_PERI_PWM_SW_RST>;
|
||||||
reset-names = "pwm";
|
reset-names = "pwm";
|
||||||
|
|
||||||
@ -346,8 +325,54 @@
|
|||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c0: i2c@11007000 {
|
||||||
|
compatible = "mediatek,mt7623-i2c",
|
||||||
|
"mediatek,mt6577-i2c";
|
||||||
|
reg = <0 0x11007000 0 0x70>,
|
||||||
|
<0 0x11000200 0 0x80>;
|
||||||
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clock-div = <16>;
|
||||||
|
clocks = <&pericfg CLK_PERI_I2C0>,
|
||||||
|
<&pericfg CLK_PERI_AP_DMA>;
|
||||||
|
clock-names = "main", "dma";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1: i2c@11008000 {
|
||||||
|
compatible = "mediatek,mt7623-i2c",
|
||||||
|
"mediatek,mt6577-i2c";
|
||||||
|
reg = <0 0x11008000 0 0x70>,
|
||||||
|
<0 0x11000280 0 0x80>;
|
||||||
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clock-div = <16>;
|
||||||
|
clocks = <&pericfg CLK_PERI_I2C1>,
|
||||||
|
<&pericfg CLK_PERI_AP_DMA>;
|
||||||
|
clock-names = "main", "dma";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c2: i2c@11009000 {
|
||||||
|
compatible = "mediatek,mt7623-i2c",
|
||||||
|
"mediatek,mt6577-i2c";
|
||||||
|
reg = <0 0x11009000 0 0x70>,
|
||||||
|
<0 0x11000300 0 0x80>;
|
||||||
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clock-div = <16>;
|
||||||
|
clocks = <&pericfg CLK_PERI_I2C2>,
|
||||||
|
<&pericfg CLK_PERI_AP_DMA>;
|
||||||
|
clock-names = "main", "dma";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
spi: spi@1100a000 {
|
spi: spi@1100a000 {
|
||||||
compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
|
compatible = "mediatek,mt7623-spi",
|
||||||
|
"mediatek,mt6589-spi";
|
||||||
reg = <0 0x1100a000 0 0x1000>;
|
reg = <0 0x1100a000 0 0x1000>;
|
||||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
||||||
clocks = <&pericfg CLK_PERI_SPI0>;
|
clocks = <&pericfg CLK_PERI_SPI0>;
|
||||||
@ -356,8 +381,27 @@
|
|||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
thermal: thermal@1100b000 {
|
||||||
|
#thermal-sensor-cells = <1>;
|
||||||
|
compatible = "mediatek,mt2701-thermal",
|
||||||
|
"mediatek,mt2701-thermal";
|
||||||
|
reg = <0 0x1100b000 0 0x1000>;
|
||||||
|
interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&pericfg CLK_PERI_THERM>,
|
||||||
|
<&pericfg CLK_PERI_AUXADC>;
|
||||||
|
clock-names = "therm", "auxadc";
|
||||||
|
resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
|
||||||
|
reset-names = "therm";
|
||||||
|
mediatek,auxadc = <&auxadc>;
|
||||||
|
mediatek,apmixedsys = <&apmixedsys>;
|
||||||
|
|
||||||
|
nvmem-cells = <&thermal_calibration>;
|
||||||
|
nvmem-cell-names = "calibration-data";
|
||||||
|
};
|
||||||
|
|
||||||
nandc: nfi@1100d000 {
|
nandc: nfi@1100d000 {
|
||||||
compatible = "mediatek,mt2701-nfc";
|
compatible = "mediatek,mt7623-nfc",
|
||||||
|
"mediatek,mt2701-nfc";
|
||||||
reg = <0 0x1100d000 0 0x1000>;
|
reg = <0 0x1100d000 0 0x1000>;
|
||||||
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
|
||||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
|
||||||
@ -371,7 +415,8 @@
|
|||||||
};
|
};
|
||||||
|
|
||||||
bch: ecc@1100e000 {
|
bch: ecc@1100e000 {
|
||||||
compatible = "mediatek,mt2701-ecc";
|
compatible = "mediatek,mt7623-ecc",
|
||||||
|
"mediatek,mt2701-ecc";
|
||||||
reg = <0 0x1100e000 0 0x1000>;
|
reg = <0 0x1100e000 0 0x1000>;
|
||||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
|
||||||
clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
clocks = <&pericfg CLK_PERI_NFI_ECC>;
|
||||||
@ -402,7 +447,7 @@
|
|||||||
};
|
};
|
||||||
|
|
||||||
usb1: usb@1a1c0000 {
|
usb1: usb@1a1c0000 {
|
||||||
compatible = "mediatek,mt2701-xhci",
|
compatible = "mediatek,mt7623-xhci",
|
||||||
"mediatek,mt8173-xhci";
|
"mediatek,mt8173-xhci";
|
||||||
reg = <0 0x1a1c0000 0 0x1000>,
|
reg = <0 0x1a1c0000 0 0x1000>,
|
||||||
<0 0x1a1c4700 0 0x0100>;
|
<0 0x1a1c4700 0 0x0100>;
|
||||||
@ -528,21 +573,26 @@
|
|||||||
};
|
};
|
||||||
|
|
||||||
ethsys: syscon@1b000000 {
|
ethsys: syscon@1b000000 {
|
||||||
compatible = "mediatek,mt2701-ethsys", "syscon";
|
compatible = "mediatek,mt7623-ethsys",
|
||||||
|
"mediatek,mt2701-ethsys",
|
||||||
|
"syscon";
|
||||||
reg = <0 0x1b000000 0 0x1000>;
|
reg = <0 0x1b000000 0 0x1000>;
|
||||||
#reset-cells = <1>;
|
#reset-cells = <1>;
|
||||||
#clock-cells = <1>;
|
#clock-cells = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
eth: ethernet@1b100000 {
|
eth: ethernet@1b100000 {
|
||||||
compatible = "mediatek,mt2701-eth";
|
compatible = "mediatek,mt7623-eth",
|
||||||
|
"mediatek,mt2701-eth",
|
||||||
|
"syscon";
|
||||||
reg = <0 0x1b100000 0 0x20000>;
|
reg = <0 0x1b100000 0 0x20000>;
|
||||||
|
|
||||||
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
||||||
<ðsys CLK_ETHSYS_ESW>,
|
<ðsys CLK_ETHSYS_ESW>,
|
||||||
<ðsys CLK_ETHSYS_GP2>,
|
<ðsys CLK_ETHSYS_GP2>,
|
||||||
<ðsys CLK_ETHSYS_GP1>;
|
<ðsys CLK_ETHSYS_GP1>,
|
||||||
clock-names = "ethif", "esw", "gp2", "gp1";
|
<&apmixedsys CLK_APMIXED_TRGPLL>;
|
||||||
|
clock-names = "ethif", "esw", "gp2", "gp1", "trgpll";
|
||||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
|
||||||
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
|
||||||
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
|
||||||
@ -554,8 +604,6 @@
|
|||||||
mediatek,ethsys = <ðsys>;
|
mediatek,ethsys = <ðsys>;
|
||||||
mediatek,pctl = <&syscfg_pctl_a>;
|
mediatek,pctl = <&syscfg_pctl_a>;
|
||||||
|
|
||||||
mediatek,switch = <&gsw>;
|
|
||||||
|
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
@ -567,7 +615,7 @@
|
|||||||
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
phy-mode = "rgmii";
|
phy-mode = "trgmii";
|
||||||
|
|
||||||
fixed-link {
|
fixed-link {
|
||||||
speed = <1000>;
|
speed = <1000>;
|
||||||
@ -583,33 +631,9 @@
|
|||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
mdio-bus {
|
mdio0: mdio-bus {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
|
|
||||||
phy5: ethernet-phy@5 {
|
|
||||||
reg = <5>;
|
|
||||||
phy-mode = "rgmii-rxid";
|
|
||||||
};
|
|
||||||
|
|
||||||
phy1f: ethernet-phy@1f {
|
|
||||||
reg = <0x1f>;
|
|
||||||
phy-mode = "rgmii";
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
gsw: switch@1b100000 {
|
|
||||||
compatible = "mediatek,mt7623-gsw";
|
|
||||||
interrupt-parent = <&pio>;
|
|
||||||
interrupts = <168 IRQ_TYPE_EDGE_RISING>;
|
|
||||||
resets = <ðsys 2>;
|
|
||||||
reset-names = "eth";
|
|
||||||
clocks = <&apmixedsys CLK_APMIXED_TRGPLL>;
|
|
||||||
clock-names = "trgpll";
|
|
||||||
mt7530-supply = <&mt6323_vpa_reg>;
|
|
||||||
mediatek,pctl-regmap = <&syscfg_pctl_a>;
|
|
||||||
mediatek,ethsys = <ðsys>;
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
};
|
|
||||||
|
|||||||
@ -18,8 +18,8 @@
|
|||||||
#include <dt-bindings/gpio/gpio.h>
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "MediaTek MT7623 NAND evaluation board";
|
model = "MediaTek MT7623 NAND reference board";
|
||||||
compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
compatible = "mediatek,mt7623-rfb-nand", "mediatek,mt7623";
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
stdout-path = &uart2;
|
stdout-path = &uart2;
|
||||||
@ -280,6 +280,34 @@
|
|||||||
regulator-enable-ramp-delay = <216>;
|
regulator-enable-ramp-delay = <216>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
mt6323led: leds {
|
||||||
|
compatible = "mediatek,mt6323-led";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
led@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "LED0";
|
||||||
|
linux,default-trigger = "timer";
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
led@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "LED1";
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
led@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "LED2";
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
led@3 {
|
||||||
|
reg = <3>;
|
||||||
|
label = "LED3";
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -332,10 +360,16 @@
|
|||||||
<MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
|
<MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
|
||||||
<MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
|
<MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
|
||||||
<MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
|
<MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
|
||||||
<MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
|
|
||||||
<MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
|
<MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pins_eth_esw {
|
||||||
|
pinmux = <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>;
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <MTK_DRIVE_8mA>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
|
||||||
pins_eth_rst {
|
pins_eth_rst {
|
||||||
pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
|
pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
|
||||||
output-low;
|
output-low;
|
||||||
@ -426,7 +460,7 @@
|
|||||||
mac-address = [00 11 22 33 44 55];
|
mac-address = [00 11 22 33 44 55];
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
phy-mode = "rgmii";
|
phy-mode = "trgmii";
|
||||||
|
|
||||||
fixed-link {
|
fixed-link {
|
||||||
speed = <1000>;
|
speed = <1000>;
|
||||||
@ -435,13 +469,64 @@
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
&gsw {
|
&mdio0 {
|
||||||
|
switch@0 {
|
||||||
|
compatible = "mediatek,mt7530";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <ð_default>;
|
pinctrl-0 = <ð_default>;
|
||||||
mediatek,reset-pin = <&pio 15 0>;
|
|
||||||
status = "okay";
|
core-supply = <&mt6323_vpa_reg>;
|
||||||
|
io-supply = <&mt6323_vemc3v3_reg>;
|
||||||
|
reset-gpios = <&pio 33 0>;
|
||||||
|
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "lan0";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
reg = <4>;
|
||||||
|
label = "wan";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@6 {
|
||||||
|
reg = <6>;
|
||||||
|
label = "cpu";
|
||||||
|
ethernet = <&gmac1>;
|
||||||
|
phy-mode = "trgmii";
|
||||||
|
fixed-link {
|
||||||
|
speed = <1000>;
|
||||||
|
full-duplex;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
&pwm {
|
&pwm {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pwm_pins>;
|
pinctrl-0 = <&pwm_pins>;
|
||||||
|
|||||||
@ -18,8 +18,8 @@
|
|||||||
#include <dt-bindings/gpio/gpio.h>
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
model = "MediaTek MT7623 eMMC evaluation board";
|
model = "MediaTek MT7623 eMMC reference board";
|
||||||
compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
compatible = "mediatek,mt7623-rfb-emmc", "mediatek,mt7623";
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
stdout-path = &uart2;
|
stdout-path = &uart2;
|
||||||
@ -474,14 +474,6 @@
|
|||||||
&gmac2 {
|
&gmac2 {
|
||||||
mac-address = [00 11 22 33 44 55];
|
mac-address = [00 11 22 33 44 55];
|
||||||
status = "okay";
|
status = "okay";
|
||||||
phy-handle = <&phy5>;
|
|
||||||
};
|
|
||||||
|
|
||||||
&gsw {
|
|
||||||
pinctrl-names = "default";
|
|
||||||
pinctrl-0 = <ð_default>;
|
|
||||||
mediatek,reset-pin = <&pio 15 0>;
|
|
||||||
status = "okay";
|
|
||||||
};
|
};
|
||||||
|
|
||||||
&pwm {
|
&pwm {
|
||||||
|
|||||||
50
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-evb.dts
Normal file
50
target/linux/mediatek/files/arch/arm/boot/dts/mt7623-evb.dts
Normal file
@ -0,0 +1,50 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016 MediaTek Inc.
|
||||||
|
* Author: John Crispin <blogic@openwrt.org>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7623.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "MediaTek MT7623 evaluation board";
|
||||||
|
compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = &uart2;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0 0x80000000 0 0x40000000>;
|
||||||
|
};
|
||||||
|
/*
|
||||||
|
pwm_pins: pwm {
|
||||||
|
pins_pwm1 {
|
||||||
|
pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pins_pwm2 {
|
||||||
|
pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
|
||||||
|
};
|
||||||
|
};*/
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart2 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/*&pwm {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pwm_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};*/
|
||||||
@ -0,0 +1,79 @@
|
|||||||
|
From 3e96c653372d8852c45dcd3bd856975157a0fd6a Mon Sep 17 00:00:00 2001
|
||||||
|
From: Shunli Wang <shunli.wang@mediatek.com>
|
||||||
|
Date: Thu, 20 Oct 2016 16:56:37 +0800
|
||||||
|
Subject: [PATCH] soc: mediatek: Add MT2701 power dt-bindings
|
||||||
|
|
||||||
|
Add power dt-bindings for MT2701.
|
||||||
|
|
||||||
|
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
|
||||||
|
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
|
||||||
|
Acked-by: Rob Herring <robh@kernel.org>
|
||||||
|
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
|
||||||
|
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
||||||
|
---
|
||||||
|
.../devicetree/bindings/soc/mediatek/scpsys.txt | 13 +++++++----
|
||||||
|
include/dt-bindings/power/mt2701-power.h | 27 ++++++++++++++++++++++
|
||||||
|
2 files changed, 35 insertions(+), 5 deletions(-)
|
||||||
|
create mode 100644 include/dt-bindings/power/mt2701-power.h
|
||||||
|
|
||||||
|
Index: linux-4.9.14/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.14.orig/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||||
|
+++ linux-4.9.14/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
|
||||||
|
@@ -9,17 +9,20 @@ domain control.
|
||||||
|
|
||||||
|
The driver implements the Generic PM domain bindings described in
|
||||||
|
power/power_domain.txt. It provides the power domains defined in
|
||||||
|
-include/dt-bindings/power/mt8173-power.h.
|
||||||
|
+include/dt-bindings/power/mt8173-power.h and mt2701-power.h.
|
||||||
|
|
||||||
|
Required properties:
|
||||||
|
-- compatible: Must be "mediatek,mt8173-scpsys"
|
||||||
|
+- compatible: Should be one of:
|
||||||
|
+ - "mediatek,mt2701-scpsys"
|
||||||
|
+ - "mediatek,mt8173-scpsys"
|
||||||
|
- #power-domain-cells: Must be 1
|
||||||
|
- reg: Address range of the SCPSYS unit
|
||||||
|
- infracfg: must contain a phandle to the infracfg controller
|
||||||
|
- clock, clock-names: clocks according to the common clock binding.
|
||||||
|
- The clocks needed "mm", "mfg", "venc" and "venc_lt".
|
||||||
|
- These are the clocks which hardware needs to be enabled
|
||||||
|
- before enabling certain power domains.
|
||||||
|
+ These are clocks which hardware needs to be
|
||||||
|
+ enabled before enabling certain power domains.
|
||||||
|
+ Required clocks for MT2701: "mm", "mfg", "ethif"
|
||||||
|
+ Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
|
||||||
|
|
||||||
|
Optional properties:
|
||||||
|
- vdec-supply: Power supply for the vdec power domain
|
||||||
|
Index: linux-4.9.14/include/dt-bindings/power/mt2701-power.h
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null
|
||||||
|
+++ linux-4.9.14/include/dt-bindings/power/mt2701-power.h
|
||||||
|
@@ -0,0 +1,26 @@
|
||||||
|
+/*
|
||||||
|
+ * Copyright (C) 2015 MediaTek Inc.
|
||||||
|
+ *
|
||||||
|
+ * This program is free software: you can redistribute it and/or modify
|
||||||
|
+ * it under the terms of the GNU General Public License version 2 as
|
||||||
|
+ * published by the Free Software Foundation.
|
||||||
|
+ *
|
||||||
|
+ * This program is distributed in the hope that it will be useful,
|
||||||
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+ * GNU General Public License for more details.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
|
||||||
|
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
|
||||||
|
+
|
||||||
|
+#define MT2701_POWER_DOMAIN_CONN 0
|
||||||
|
+#define MT2701_POWER_DOMAIN_DISP 1
|
||||||
|
+#define MT2701_POWER_DOMAIN_IFR_MSC 2
|
||||||
|
+#define MT2701_POWER_DOMAIN_VDEC 3
|
||||||
|
+#define MT2701_POWER_DOMAIN_ISP 4
|
||||||
|
+#define MT2701_POWER_DOMAIN_BDP 5
|
||||||
|
+#define MT2701_POWER_DOMAIN_ETH 6
|
||||||
|
+#define MT2701_POWER_DOMAIN_HIF 7
|
||||||
|
+
|
||||||
|
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
|
||||||
@ -1,44 +0,0 @@
|
|||||||
From 7c5b29de78f1b15c5bde40a6ca4510fc09588457 Mon Sep 17 00:00:00 2001
|
|
||||||
From: Shunli Wang <shunli.wang@mediatek.com>
|
|
||||||
Date: Wed, 30 Dec 2015 14:41:45 +0800
|
|
||||||
Subject: [PATCH 004/102] soc: mediatek: Add MT2701 power dt-bindings
|
|
||||||
|
|
||||||
Add power dt-bindings for MT2701.
|
|
||||||
|
|
||||||
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
|
|
||||||
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
|
|
||||||
---
|
|
||||||
include/dt-bindings/power/mt2701-power.h | 27 +++++++++++++++++++++++++++
|
|
||||||
1 file changed, 27 insertions(+)
|
|
||||||
create mode 100644 include/dt-bindings/power/mt2701-power.h
|
|
||||||
|
|
||||||
--- /dev/null
|
|
||||||
+++ b/include/dt-bindings/power/mt2701-power.h
|
|
||||||
@@ -0,0 +1,27 @@
|
|
||||||
+/*
|
|
||||||
+ * Copyright (C) 2015 MediaTek Inc.
|
|
||||||
+ *
|
|
||||||
+ * This program is free software: you can redistribute it and/or modify
|
|
||||||
+ * it under the terms of the GNU General Public License version 2 as
|
|
||||||
+ * published by the Free Software Foundation.
|
|
||||||
+ *
|
|
||||||
+ * This program is distributed in the hope that it will be useful,
|
|
||||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
+ * GNU General Public License for more details.
|
|
||||||
+ */
|
|
||||||
+
|
|
||||||
+#ifndef _DT_BINDINGS_POWER_MT2701_POWER_H
|
|
||||||
+#define _DT_BINDINGS_POWER_MT2701_POWER_H
|
|
||||||
+
|
|
||||||
+#define MT2701_POWER_DOMAIN_CONN 0
|
|
||||||
+#define MT2701_POWER_DOMAIN_DISP 1
|
|
||||||
+#define MT2701_POWER_DOMAIN_MFG 2
|
|
||||||
+#define MT2701_POWER_DOMAIN_VDEC 3
|
|
||||||
+#define MT2701_POWER_DOMAIN_ISP 4
|
|
||||||
+#define MT2701_POWER_DOMAIN_BDP 5
|
|
||||||
+#define MT2701_POWER_DOMAIN_ETH 6
|
|
||||||
+#define MT2701_POWER_DOMAIN_HIF 7
|
|
||||||
+#define MT2701_POWER_DOMAIN_IFR_MSC 8
|
|
||||||
+
|
|
||||||
+#endif /* _DT_BINDINGS_POWER_MT2701_POWER_H */
|
|
||||||
@ -0,0 +1,491 @@
|
|||||||
|
From 6078c651947a148c1de543b54fe55af43a63043a Mon Sep 17 00:00:00 2001
|
||||||
|
From: James Liao <jamesjj.liao@mediatek.com>
|
||||||
|
Date: Thu, 20 Oct 2016 16:56:35 +0800
|
||||||
|
Subject: [PATCH 1/2] soc: mediatek: Refine scpsys to support multiple platform
|
||||||
|
|
||||||
|
Refine scpsys driver common code to support multiple SoC / platform.
|
||||||
|
|
||||||
|
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
|
||||||
|
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
|
||||||
|
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/soc/mediatek/mtk-scpsys.c | 348 +++++++++++++++++++++++---------------
|
||||||
|
1 file changed, 210 insertions(+), 138 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
|
||||||
|
index 837effe19907..722aac80e611 100644
|
||||||
|
--- a/drivers/soc/mediatek/mtk-scpsys.c
|
||||||
|
+++ b/drivers/soc/mediatek/mtk-scpsys.c
|
||||||
|
@@ -11,17 +11,15 @@
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
#include <linux/clk.h>
|
||||||
|
-#include <linux/delay.h>
|
||||||
|
+#include <linux/init.h>
|
||||||
|
#include <linux/io.h>
|
||||||
|
-#include <linux/kernel.h>
|
||||||
|
#include <linux/mfd/syscon.h>
|
||||||
|
-#include <linux/init.h>
|
||||||
|
#include <linux/of_device.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/pm_domain.h>
|
||||||
|
-#include <linux/regmap.h>
|
||||||
|
-#include <linux/soc/mediatek/infracfg.h>
|
||||||
|
#include <linux/regulator/consumer.h>
|
||||||
|
+#include <linux/soc/mediatek/infracfg.h>
|
||||||
|
+
|
||||||
|
#include <dt-bindings/power/mt8173-power.h>
|
||||||
|
|
||||||
|
#define SPM_VDE_PWR_CON 0x0210
|
||||||
|
@@ -34,6 +32,7 @@
|
||||||
|
#define SPM_MFG_2D_PWR_CON 0x02c0
|
||||||
|
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
|
||||||
|
#define SPM_USB_PWR_CON 0x02cc
|
||||||
|
+
|
||||||
|
#define SPM_PWR_STATUS 0x060c
|
||||||
|
#define SPM_PWR_STATUS_2ND 0x0610
|
||||||
|
|
||||||
|
@@ -55,12 +54,21 @@
|
||||||
|
#define PWR_STATUS_USB BIT(25)
|
||||||
|
|
||||||
|
enum clk_id {
|
||||||
|
- MT8173_CLK_NONE,
|
||||||
|
- MT8173_CLK_MM,
|
||||||
|
- MT8173_CLK_MFG,
|
||||||
|
- MT8173_CLK_VENC,
|
||||||
|
- MT8173_CLK_VENC_LT,
|
||||||
|
- MT8173_CLK_MAX,
|
||||||
|
+ CLK_NONE,
|
||||||
|
+ CLK_MM,
|
||||||
|
+ CLK_MFG,
|
||||||
|
+ CLK_VENC,
|
||||||
|
+ CLK_VENC_LT,
|
||||||
|
+ CLK_MAX,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const char * const clk_names[] = {
|
||||||
|
+ NULL,
|
||||||
|
+ "mm",
|
||||||
|
+ "mfg",
|
||||||
|
+ "venc",
|
||||||
|
+ "venc_lt",
|
||||||
|
+ NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define MAX_CLKS 2
|
||||||
|
@@ -76,98 +84,6 @@ struct scp_domain_data {
|
||||||
|
bool active_wakeup;
|
||||||
|
};
|
||||||
|
|
||||||
|
-static const struct scp_domain_data scp_domain_data[] = {
|
||||||
|
- [MT8173_POWER_DOMAIN_VDEC] = {
|
||||||
|
- .name = "vdec",
|
||||||
|
- .sta_mask = PWR_STATUS_VDEC,
|
||||||
|
- .ctl_offs = SPM_VDE_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(12, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_MM},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_VENC] = {
|
||||||
|
- .name = "venc",
|
||||||
|
- .sta_mask = PWR_STATUS_VENC,
|
||||||
|
- .ctl_offs = SPM_VEN_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_ISP] = {
|
||||||
|
- .name = "isp",
|
||||||
|
- .sta_mask = PWR_STATUS_ISP,
|
||||||
|
- .ctl_offs = SPM_ISP_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(13, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_MM},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_MM] = {
|
||||||
|
- .name = "mm",
|
||||||
|
- .sta_mask = PWR_STATUS_DISP,
|
||||||
|
- .ctl_offs = SPM_DIS_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(12, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_MM},
|
||||||
|
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
|
||||||
|
- MT8173_TOP_AXI_PROT_EN_MM_M1,
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_VENC_LT] = {
|
||||||
|
- .name = "venc_lt",
|
||||||
|
- .sta_mask = PWR_STATUS_VENC_LT,
|
||||||
|
- .ctl_offs = SPM_VEN2_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_AUDIO] = {
|
||||||
|
- .name = "audio",
|
||||||
|
- .sta_mask = PWR_STATUS_AUDIO,
|
||||||
|
- .ctl_offs = SPM_AUDIO_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_NONE},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_USB] = {
|
||||||
|
- .name = "usb",
|
||||||
|
- .sta_mask = PWR_STATUS_USB,
|
||||||
|
- .ctl_offs = SPM_USB_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_NONE},
|
||||||
|
- .active_wakeup = true,
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
|
||||||
|
- .name = "mfg_async",
|
||||||
|
- .sta_mask = PWR_STATUS_MFG_ASYNC,
|
||||||
|
- .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = 0,
|
||||||
|
- .clk_id = {MT8173_CLK_MFG},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_MFG_2D] = {
|
||||||
|
- .name = "mfg_2d",
|
||||||
|
- .sta_mask = PWR_STATUS_MFG_2D,
|
||||||
|
- .ctl_offs = SPM_MFG_2D_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(13, 12),
|
||||||
|
- .clk_id = {MT8173_CLK_NONE},
|
||||||
|
- },
|
||||||
|
- [MT8173_POWER_DOMAIN_MFG] = {
|
||||||
|
- .name = "mfg",
|
||||||
|
- .sta_mask = PWR_STATUS_MFG,
|
||||||
|
- .ctl_offs = SPM_MFG_PWR_CON,
|
||||||
|
- .sram_pdn_bits = GENMASK(13, 8),
|
||||||
|
- .sram_pdn_ack_bits = GENMASK(21, 16),
|
||||||
|
- .clk_id = {MT8173_CLK_NONE},
|
||||||
|
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
|
||||||
|
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
|
||||||
|
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
|
||||||
|
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
|
||||||
|
- },
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
-#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
|
||||||
|
-
|
||||||
|
struct scp;
|
||||||
|
|
||||||
|
struct scp_domain {
|
||||||
|
@@ -179,7 +95,7 @@ struct scp_domain {
|
||||||
|
};
|
||||||
|
|
||||||
|
struct scp {
|
||||||
|
- struct scp_domain domains[NUM_DOMAINS];
|
||||||
|
+ struct scp_domain *domains;
|
||||||
|
struct genpd_onecell_data pd_data;
|
||||||
|
struct device *dev;
|
||||||
|
void __iomem *base;
|
||||||
|
@@ -408,57 +324,55 @@ static bool scpsys_active_wakeup(struct device *dev)
|
||||||
|
return scpd->data->active_wakeup;
|
||||||
|
}
|
||||||
|
|
||||||
|
-static int scpsys_probe(struct platform_device *pdev)
|
||||||
|
+static void init_clks(struct platform_device *pdev, struct clk **clk)
|
||||||
|
+{
|
||||||
|
+ int i;
|
||||||
|
+
|
||||||
|
+ for (i = CLK_NONE + 1; i < CLK_MAX; i++)
|
||||||
|
+ clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static struct scp *init_scp(struct platform_device *pdev,
|
||||||
|
+ const struct scp_domain_data *scp_domain_data, int num)
|
||||||
|
{
|
||||||
|
struct genpd_onecell_data *pd_data;
|
||||||
|
struct resource *res;
|
||||||
|
- int i, j, ret;
|
||||||
|
+ int i, j;
|
||||||
|
struct scp *scp;
|
||||||
|
- struct clk *clk[MT8173_CLK_MAX];
|
||||||
|
+ struct clk *clk[CLK_MAX];
|
||||||
|
|
||||||
|
scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
|
||||||
|
if (!scp)
|
||||||
|
- return -ENOMEM;
|
||||||
|
+ return ERR_PTR(-ENOMEM);
|
||||||
|
|
||||||
|
scp->dev = &pdev->dev;
|
||||||
|
|
||||||
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
|
scp->base = devm_ioremap_resource(&pdev->dev, res);
|
||||||
|
if (IS_ERR(scp->base))
|
||||||
|
- return PTR_ERR(scp->base);
|
||||||
|
+ return ERR_CAST(scp->base);
|
||||||
|
+
|
||||||
|
+ scp->domains = devm_kzalloc(&pdev->dev,
|
||||||
|
+ sizeof(*scp->domains) * num, GFP_KERNEL);
|
||||||
|
+ if (!scp->domains)
|
||||||
|
+ return ERR_PTR(-ENOMEM);
|
||||||
|
|
||||||
|
pd_data = &scp->pd_data;
|
||||||
|
|
||||||
|
pd_data->domains = devm_kzalloc(&pdev->dev,
|
||||||
|
- sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
|
||||||
|
+ sizeof(*pd_data->domains) * num, GFP_KERNEL);
|
||||||
|
if (!pd_data->domains)
|
||||||
|
- return -ENOMEM;
|
||||||
|
-
|
||||||
|
- clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
|
||||||
|
- if (IS_ERR(clk[MT8173_CLK_MM]))
|
||||||
|
- return PTR_ERR(clk[MT8173_CLK_MM]);
|
||||||
|
-
|
||||||
|
- clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
|
||||||
|
- if (IS_ERR(clk[MT8173_CLK_MFG]))
|
||||||
|
- return PTR_ERR(clk[MT8173_CLK_MFG]);
|
||||||
|
-
|
||||||
|
- clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
|
||||||
|
- if (IS_ERR(clk[MT8173_CLK_VENC]))
|
||||||
|
- return PTR_ERR(clk[MT8173_CLK_VENC]);
|
||||||
|
-
|
||||||
|
- clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
|
||||||
|
- if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
|
||||||
|
- return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
|
||||||
|
+ return ERR_PTR(-ENOMEM);
|
||||||
|
|
||||||
|
scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
|
||||||
|
"infracfg");
|
||||||
|
if (IS_ERR(scp->infracfg)) {
|
||||||
|
dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
|
||||||
|
PTR_ERR(scp->infracfg));
|
||||||
|
- return PTR_ERR(scp->infracfg);
|
||||||
|
+ return ERR_CAST(scp->infracfg);
|
||||||
|
}
|
||||||
|
|
||||||
|
- for (i = 0; i < NUM_DOMAINS; i++) {
|
||||||
|
+ for (i = 0; i < num; i++) {
|
||||||
|
struct scp_domain *scpd = &scp->domains[i];
|
||||||
|
const struct scp_domain_data *data = &scp_domain_data[i];
|
||||||
|
|
||||||
|
@@ -467,13 +381,15 @@ static int scpsys_probe(struct platform_device *pdev)
|
||||||
|
if (PTR_ERR(scpd->supply) == -ENODEV)
|
||||||
|
scpd->supply = NULL;
|
||||||
|
else
|
||||||
|
- return PTR_ERR(scpd->supply);
|
||||||
|
+ return ERR_CAST(scpd->supply);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
- pd_data->num_domains = NUM_DOMAINS;
|
||||||
|
+ pd_data->num_domains = num;
|
||||||
|
|
||||||
|
- for (i = 0; i < NUM_DOMAINS; i++) {
|
||||||
|
+ init_clks(pdev, clk);
|
||||||
|
+
|
||||||
|
+ for (i = 0; i < num; i++) {
|
||||||
|
struct scp_domain *scpd = &scp->domains[i];
|
||||||
|
struct generic_pm_domain *genpd = &scpd->genpd;
|
||||||
|
const struct scp_domain_data *data = &scp_domain_data[i];
|
||||||
|
@@ -482,13 +398,37 @@ static int scpsys_probe(struct platform_device *pdev)
|
||||||
|
scpd->scp = scp;
|
||||||
|
|
||||||
|
scpd->data = data;
|
||||||
|
- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
|
||||||
|
- scpd->clk[j] = clk[data->clk_id[j]];
|
||||||
|
+
|
||||||
|
+ for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
|
||||||
|
+ struct clk *c = clk[data->clk_id[j]];
|
||||||
|
+
|
||||||
|
+ if (IS_ERR(c)) {
|
||||||
|
+ dev_err(&pdev->dev, "%s: clk unavailable\n",
|
||||||
|
+ data->name);
|
||||||
|
+ return ERR_CAST(c);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ scpd->clk[j] = c;
|
||||||
|
+ }
|
||||||
|
|
||||||
|
genpd->name = data->name;
|
||||||
|
genpd->power_off = scpsys_power_off;
|
||||||
|
genpd->power_on = scpsys_power_on;
|
||||||
|
genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return scp;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void mtk_register_power_domains(struct platform_device *pdev,
|
||||||
|
+ struct scp *scp, int num)
|
||||||
|
+{
|
||||||
|
+ struct genpd_onecell_data *pd_data;
|
||||||
|
+ int i, ret;
|
||||||
|
+
|
||||||
|
+ for (i = 0; i < num; i++) {
|
||||||
|
+ struct scp_domain *scpd = &scp->domains[i];
|
||||||
|
+ struct generic_pm_domain *genpd = &scpd->genpd;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initially turn on all domains to make the domains usable
|
||||||
|
@@ -507,6 +447,123 @@ static int scpsys_probe(struct platform_device *pdev)
|
||||||
|
* valid.
|
||||||
|
*/
|
||||||
|
|
||||||
|
+ pd_data = &scp->pd_data;
|
||||||
|
+
|
||||||
|
+ ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
|
||||||
|
+ if (ret)
|
||||||
|
+ dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * MT8173 power domain support
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+static const struct scp_domain_data scp_domain_data_mt8173[] = {
|
||||||
|
+ [MT8173_POWER_DOMAIN_VDEC] = {
|
||||||
|
+ .name = "vdec",
|
||||||
|
+ .sta_mask = PWR_STATUS_VDEC,
|
||||||
|
+ .ctl_offs = SPM_VDE_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(12, 12),
|
||||||
|
+ .clk_id = {CLK_MM},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_VENC] = {
|
||||||
|
+ .name = "venc",
|
||||||
|
+ .sta_mask = PWR_STATUS_VENC,
|
||||||
|
+ .ctl_offs = SPM_VEN_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
+ .clk_id = {CLK_MM, CLK_VENC},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_ISP] = {
|
||||||
|
+ .name = "isp",
|
||||||
|
+ .sta_mask = PWR_STATUS_ISP,
|
||||||
|
+ .ctl_offs = SPM_ISP_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(13, 12),
|
||||||
|
+ .clk_id = {CLK_MM},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_MM] = {
|
||||||
|
+ .name = "mm",
|
||||||
|
+ .sta_mask = PWR_STATUS_DISP,
|
||||||
|
+ .ctl_offs = SPM_DIS_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(12, 12),
|
||||||
|
+ .clk_id = {CLK_MM},
|
||||||
|
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
|
||||||
|
+ MT8173_TOP_AXI_PROT_EN_MM_M1,
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_VENC_LT] = {
|
||||||
|
+ .name = "venc_lt",
|
||||||
|
+ .sta_mask = PWR_STATUS_VENC_LT,
|
||||||
|
+ .ctl_offs = SPM_VEN2_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
+ .clk_id = {CLK_MM, CLK_VENC_LT},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_AUDIO] = {
|
||||||
|
+ .name = "audio",
|
||||||
|
+ .sta_mask = PWR_STATUS_AUDIO,
|
||||||
|
+ .ctl_offs = SPM_AUDIO_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_USB] = {
|
||||||
|
+ .name = "usb",
|
||||||
|
+ .sta_mask = PWR_STATUS_USB,
|
||||||
|
+ .ctl_offs = SPM_USB_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
|
||||||
|
+ .name = "mfg_async",
|
||||||
|
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
|
||||||
|
+ .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = 0,
|
||||||
|
+ .clk_id = {CLK_MFG},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_MFG_2D] = {
|
||||||
|
+ .name = "mfg_2d",
|
||||||
|
+ .sta_mask = PWR_STATUS_MFG_2D,
|
||||||
|
+ .ctl_offs = SPM_MFG_2D_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(13, 12),
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ },
|
||||||
|
+ [MT8173_POWER_DOMAIN_MFG] = {
|
||||||
|
+ .name = "mfg",
|
||||||
|
+ .sta_mask = PWR_STATUS_MFG,
|
||||||
|
+ .ctl_offs = SPM_MFG_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(13, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(21, 16),
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
|
||||||
|
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
|
||||||
|
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
|
||||||
|
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+#define NUM_DOMAINS_MT8173 ARRAY_SIZE(scp_domain_data_mt8173)
|
||||||
|
+
|
||||||
|
+static int __init scpsys_probe_mt8173(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ struct scp *scp;
|
||||||
|
+ struct genpd_onecell_data *pd_data;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ scp = init_scp(pdev, scp_domain_data_mt8173, NUM_DOMAINS_MT8173);
|
||||||
|
+ if (IS_ERR(scp))
|
||||||
|
+ return PTR_ERR(scp);
|
||||||
|
+
|
||||||
|
+ mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT8173);
|
||||||
|
+
|
||||||
|
+ pd_data = &scp->pd_data;
|
||||||
|
+
|
||||||
|
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
|
||||||
|
pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
|
||||||
|
if (ret && IS_ENABLED(CONFIG_PM))
|
||||||
|
@@ -517,21 +574,36 @@ static int scpsys_probe(struct platform_device *pdev)
|
||||||
|
if (ret && IS_ENABLED(CONFIG_PM))
|
||||||
|
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
|
||||||
|
|
||||||
|
- ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
|
||||||
|
- if (ret)
|
||||||
|
- dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
|
||||||
|
-
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
+/*
|
||||||
|
+ * scpsys driver init
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
static const struct of_device_id of_scpsys_match_tbl[] = {
|
||||||
|
{
|
||||||
|
.compatible = "mediatek,mt8173-scpsys",
|
||||||
|
+ .data = scpsys_probe_mt8173,
|
||||||
|
}, {
|
||||||
|
/* sentinel */
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
+static int scpsys_probe(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ int (*probe)(struct platform_device *);
|
||||||
|
+ const struct of_device_id *of_id;
|
||||||
|
+
|
||||||
|
+ of_id = of_match_node(of_scpsys_match_tbl, pdev->dev.of_node);
|
||||||
|
+ if (!of_id || !of_id->data)
|
||||||
|
+ return -EINVAL;
|
||||||
|
+
|
||||||
|
+ probe = of_id->data;
|
||||||
|
+
|
||||||
|
+ return probe(pdev);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static struct platform_driver scpsys_drv = {
|
||||||
|
.probe = scpsys_probe,
|
||||||
|
.driver = {
|
||||||
|
--
|
||||||
|
2.11.0
|
||||||
|
|
||||||
@ -0,0 +1,198 @@
|
|||||||
|
From 112ef1882e12094c823937f9d72f2f598db02df7 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Shunli Wang <shunli.wang@mediatek.com>
|
||||||
|
Date: Thu, 20 Oct 2016 16:56:38 +0800
|
||||||
|
Subject: [PATCH 2/2] soc: mediatek: Add MT2701 scpsys driver
|
||||||
|
|
||||||
|
Add scpsys driver for MT2701.
|
||||||
|
|
||||||
|
mtk-scpsys now supports MT8173 (arm64) and MT2701 (arm). So it should
|
||||||
|
be enabled on both arm64 and arm platforms.
|
||||||
|
|
||||||
|
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
|
||||||
|
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
|
||||||
|
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
|
||||||
|
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/soc/mediatek/Kconfig | 2 +-
|
||||||
|
drivers/soc/mediatek/mtk-scpsys.c | 117 +++++++++++++++++++++++++++++++++++++-
|
||||||
|
2 files changed, 117 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
Index: linux-4.9.14/drivers/soc/mediatek/Kconfig
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.14.orig/drivers/soc/mediatek/Kconfig
|
||||||
|
+++ linux-4.9.14/drivers/soc/mediatek/Kconfig
|
||||||
|
@@ -23,7 +23,7 @@ config MTK_PMIC_WRAP
|
||||||
|
config MTK_SCPSYS
|
||||||
|
bool "MediaTek SCPSYS Support"
|
||||||
|
depends on ARCH_MEDIATEK || COMPILE_TEST
|
||||||
|
- default ARM64 && ARCH_MEDIATEK
|
||||||
|
+ default ARCH_MEDIATEK
|
||||||
|
select REGMAP
|
||||||
|
select MTK_INFRACFG
|
||||||
|
select PM_GENERIC_DOMAINS if PM
|
||||||
|
Index: linux-4.9.14/drivers/soc/mediatek/mtk-scpsys.c
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.14.orig/drivers/soc/mediatek/mtk-scpsys.c
|
||||||
|
+++ linux-4.9.14/drivers/soc/mediatek/mtk-scpsys.c
|
||||||
|
@@ -20,6 +20,7 @@
|
||||||
|
#include <linux/regulator/consumer.h>
|
||||||
|
#include <linux/soc/mediatek/infracfg.h>
|
||||||
|
|
||||||
|
+#include <dt-bindings/power/mt2701-power.h>
|
||||||
|
#include <dt-bindings/power/mt8173-power.h>
|
||||||
|
|
||||||
|
#define SPM_VDE_PWR_CON 0x0210
|
||||||
|
@@ -27,8 +28,13 @@
|
||||||
|
#define SPM_VEN_PWR_CON 0x0230
|
||||||
|
#define SPM_ISP_PWR_CON 0x0238
|
||||||
|
#define SPM_DIS_PWR_CON 0x023c
|
||||||
|
+#define SPM_CONN_PWR_CON 0x0280
|
||||||
|
#define SPM_VEN2_PWR_CON 0x0298
|
||||||
|
-#define SPM_AUDIO_PWR_CON 0x029c
|
||||||
|
+#define SPM_AUDIO_PWR_CON 0x029c /* MT8173 */
|
||||||
|
+#define SPM_BDP_PWR_CON 0x029c /* MT2701 */
|
||||||
|
+#define SPM_ETH_PWR_CON 0x02a0
|
||||||
|
+#define SPM_HIF_PWR_CON 0x02a4
|
||||||
|
+#define SPM_IFR_MSC_PWR_CON 0x02a8
|
||||||
|
#define SPM_MFG_2D_PWR_CON 0x02c0
|
||||||
|
#define SPM_MFG_ASYNC_PWR_CON 0x02c4
|
||||||
|
#define SPM_USB_PWR_CON 0x02cc
|
||||||
|
@@ -42,10 +48,15 @@
|
||||||
|
#define PWR_ON_2ND_BIT BIT(3)
|
||||||
|
#define PWR_CLK_DIS_BIT BIT(4)
|
||||||
|
|
||||||
|
+#define PWR_STATUS_CONN BIT(1)
|
||||||
|
#define PWR_STATUS_DISP BIT(3)
|
||||||
|
#define PWR_STATUS_MFG BIT(4)
|
||||||
|
#define PWR_STATUS_ISP BIT(5)
|
||||||
|
#define PWR_STATUS_VDEC BIT(7)
|
||||||
|
+#define PWR_STATUS_BDP BIT(14)
|
||||||
|
+#define PWR_STATUS_ETH BIT(15)
|
||||||
|
+#define PWR_STATUS_HIF BIT(16)
|
||||||
|
+#define PWR_STATUS_IFR_MSC BIT(17)
|
||||||
|
#define PWR_STATUS_VENC_LT BIT(20)
|
||||||
|
#define PWR_STATUS_VENC BIT(21)
|
||||||
|
#define PWR_STATUS_MFG_2D BIT(22)
|
||||||
|
@@ -59,6 +70,7 @@ enum clk_id {
|
||||||
|
CLK_MFG,
|
||||||
|
CLK_VENC,
|
||||||
|
CLK_VENC_LT,
|
||||||
|
+ CLK_ETHIF,
|
||||||
|
CLK_MAX,
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -68,6 +80,7 @@ static const char * const clk_names[] =
|
||||||
|
"mfg",
|
||||||
|
"venc",
|
||||||
|
"venc_lt",
|
||||||
|
+ "ethif",
|
||||||
|
NULL,
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -455,6 +468,96 @@ static void mtk_register_power_domains(s
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
+ * MT2701 power domain support
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+static const struct scp_domain_data scp_domain_data_mt2701[] = {
|
||||||
|
+ [MT2701_POWER_DOMAIN_CONN] = {
|
||||||
|
+ .name = "conn",
|
||||||
|
+ .sta_mask = PWR_STATUS_CONN,
|
||||||
|
+ .ctl_offs = SPM_CONN_PWR_CON,
|
||||||
|
+ .bus_prot_mask = 0x0104,
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_DISP] = {
|
||||||
|
+ .name = "disp",
|
||||||
|
+ .sta_mask = PWR_STATUS_DISP,
|
||||||
|
+ .ctl_offs = SPM_DIS_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .clk_id = {CLK_MM},
|
||||||
|
+ .bus_prot_mask = 0x0002,
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_VDEC] = {
|
||||||
|
+ .name = "vdec",
|
||||||
|
+ .sta_mask = PWR_STATUS_VDEC,
|
||||||
|
+ .ctl_offs = SPM_VDE_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(12, 12),
|
||||||
|
+ .clk_id = {CLK_MM},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_ISP] = {
|
||||||
|
+ .name = "isp",
|
||||||
|
+ .sta_mask = PWR_STATUS_ISP,
|
||||||
|
+ .ctl_offs = SPM_ISP_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(13, 12),
|
||||||
|
+ .clk_id = {CLK_MM},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_BDP] = {
|
||||||
|
+ .name = "bdp",
|
||||||
|
+ .sta_mask = PWR_STATUS_BDP,
|
||||||
|
+ .ctl_offs = SPM_BDP_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_ETH] = {
|
||||||
|
+ .name = "eth",
|
||||||
|
+ .sta_mask = PWR_STATUS_ETH,
|
||||||
|
+ .ctl_offs = SPM_ETH_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
+ .clk_id = {CLK_ETHIF},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_HIF] = {
|
||||||
|
+ .name = "hif",
|
||||||
|
+ .sta_mask = PWR_STATUS_HIF,
|
||||||
|
+ .ctl_offs = SPM_HIF_PWR_CON,
|
||||||
|
+ .sram_pdn_bits = GENMASK(11, 8),
|
||||||
|
+ .sram_pdn_ack_bits = GENMASK(15, 12),
|
||||||
|
+ .clk_id = {CLK_ETHIF},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+ [MT2701_POWER_DOMAIN_IFR_MSC] = {
|
||||||
|
+ .name = "ifr_msc",
|
||||||
|
+ .sta_mask = PWR_STATUS_IFR_MSC,
|
||||||
|
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
|
||||||
|
+ .clk_id = {CLK_NONE},
|
||||||
|
+ .active_wakeup = true,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+#define NUM_DOMAINS_MT2701 ARRAY_SIZE(scp_domain_data_mt2701)
|
||||||
|
+
|
||||||
|
+static int __init scpsys_probe_mt2701(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ struct scp *scp;
|
||||||
|
+
|
||||||
|
+ scp = init_scp(pdev, scp_domain_data_mt2701, NUM_DOMAINS_MT2701);
|
||||||
|
+ if (IS_ERR(scp))
|
||||||
|
+ return PTR_ERR(scp);
|
||||||
|
+
|
||||||
|
+ mtk_register_power_domains(pdev, scp, NUM_DOMAINS_MT2701);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
* MT8173 power domain support
|
||||||
|
*/
|
||||||
|
|
||||||
|
@@ -583,6 +686,9 @@ static int __init scpsys_probe_mt8173(st
|
||||||
|
|
||||||
|
static const struct of_device_id of_scpsys_match_tbl[] = {
|
||||||
|
{
|
||||||
|
+ .compatible = "mediatek,mt2701-scpsys",
|
||||||
|
+ .data = scpsys_probe_mt2701,
|
||||||
|
+ }, {
|
||||||
|
.compatible = "mediatek,mt8173-scpsys",
|
||||||
|
.data = scpsys_probe_mt8173,
|
||||||
|
}, {
|
||||||
@ -13,36 +13,10 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||||||
5 files changed, 279 insertions(+)
|
5 files changed, 279 insertions(+)
|
||||||
create mode 100644 drivers/pwm/pwm-mediatek.c
|
create mode 100644 drivers/pwm/pwm-mediatek.c
|
||||||
|
|
||||||
--- a/arch/arm/boot/dts/mt7623-evb.dts
|
Index: linux-4.9.17/drivers/pwm/Kconfig
|
||||||
+++ b/arch/arm/boot/dts/mt7623-evb.dts
|
===================================================================
|
||||||
@@ -26,8 +26,25 @@
|
--- linux-4.9.17.orig/drivers/pwm/Kconfig
|
||||||
memory {
|
+++ linux-4.9.17/drivers/pwm/Kconfig
|
||||||
reg = <0 0x80000000 0 0x40000000>;
|
|
||||||
};
|
|
||||||
+/*
|
|
||||||
+ pwm_pins: pwm {
|
|
||||||
+ pins_pwm1 {
|
|
||||||
+ pinmux = <MT7623_PIN_204_PWM1_FUNC_PWM1>;
|
|
||||||
+ };
|
|
||||||
+
|
|
||||||
+ pins_pwm2 {
|
|
||||||
+ pinmux = <MT7623_PIN_205_PWM2_FUNC_PWM2>;
|
|
||||||
+ };
|
|
||||||
+ };*/
|
|
||||||
+
|
|
||||||
};
|
|
||||||
|
|
||||||
&uart2 {
|
|
||||||
status = "okay";
|
|
||||||
};
|
|
||||||
+
|
|
||||||
+/*&pwm {
|
|
||||||
+ pinctrl-names = "default";
|
|
||||||
+ pinctrl-0 = <&pwm_pins>;
|
|
||||||
+ status = "okay";
|
|
||||||
+};*/
|
|
||||||
--- a/drivers/pwm/Kconfig
|
|
||||||
+++ b/drivers/pwm/Kconfig
|
|
||||||
@@ -282,6 +282,15 @@ config PWM_MTK_DISP
|
@@ -282,6 +282,15 @@ config PWM_MTK_DISP
|
||||||
To compile this driver as a module, choose M here: the module
|
To compile this driver as a module, choose M here: the module
|
||||||
will be called pwm-mtk-disp.
|
will be called pwm-mtk-disp.
|
||||||
@ -59,8 +33,10 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||||||
config PWM_MXS
|
config PWM_MXS
|
||||||
tristate "Freescale MXS PWM support"
|
tristate "Freescale MXS PWM support"
|
||||||
depends on ARCH_MXS && OF
|
depends on ARCH_MXS && OF
|
||||||
--- a/drivers/pwm/Makefile
|
Index: linux-4.9.17/drivers/pwm/Makefile
|
||||||
+++ b/drivers/pwm/Makefile
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/drivers/pwm/Makefile
|
||||||
|
+++ linux-4.9.17/drivers/pwm/Makefile
|
||||||
@@ -25,6 +25,7 @@ obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
|
@@ -25,6 +25,7 @@ obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o
|
||||||
obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
|
obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o
|
||||||
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
|
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
|
||||||
@ -69,8 +45,10 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||||||
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
|
obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
|
||||||
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
|
obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
|
||||||
obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
|
obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
|
||||||
|
Index: linux-4.9.17/drivers/pwm/pwm-mediatek.c
|
||||||
|
===================================================================
|
||||||
--- /dev/null
|
--- /dev/null
|
||||||
+++ b/drivers/pwm/pwm-mediatek.c
|
+++ linux-4.9.17/drivers/pwm/pwm-mediatek.c
|
||||||
@@ -0,0 +1,230 @@
|
@@ -0,0 +1,230 @@
|
||||||
+/*
|
+/*
|
||||||
+ * Mediatek Pulse Width Modulator driver
|
+ * Mediatek Pulse Width Modulator driver
|
||||||
|
|||||||
43
target/linux/mediatek/patches-4.9/0083-mfd-led3.patch
Normal file
43
target/linux/mediatek/patches-4.9/0083-mfd-led3.patch
Normal file
@ -0,0 +1,43 @@
|
|||||||
|
From patchwork Fri Feb 24 18:47:21 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [v4,4/4] mfd: mt6397: Add MT6323 LED support into MT6397 driver
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9591021
|
||||||
|
Message-Id: <1487962041-6548-5-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
|
||||||
|
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
|
||||||
|
<mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
|
||||||
|
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Date: Sat, 25 Feb 2017 02:47:21 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
Add compatible string as "mt6323-led" that will make
|
||||||
|
the OF core spawn child devices for the LED subnode
|
||||||
|
of that MT6323 MFD device.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/mfd/mt6397-core.c | 4 ++++
|
||||||
|
1 file changed, 4 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
|
||||||
|
index e14d8b0..8e601c8 100644
|
||||||
|
--- a/drivers/mfd/mt6397-core.c
|
||||||
|
+++ b/drivers/mfd/mt6397-core.c
|
||||||
|
@@ -48,6 +48,10 @@
|
||||||
|
.name = "mt6323-regulator",
|
||||||
|
.of_compatible = "mediatek,mt6323-regulator"
|
||||||
|
},
|
||||||
|
+ {
|
||||||
|
+ .name = "mt6323-led",
|
||||||
|
+ .of_compatible = "mediatek,mt6323-led"
|
||||||
|
+ },
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mfd_cell mt6397_devs[] = {
|
||||||
94
target/linux/mediatek/patches-4.9/0085-pmic-led0.patch
Normal file
94
target/linux/mediatek/patches-4.9/0085-pmic-led0.patch
Normal file
@ -0,0 +1,94 @@
|
|||||||
|
From patchwork Mon Mar 20 06:47:24 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [v6,1/4] dt-bindings: leds: Add document bindings for leds-mt6323
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9633073
|
||||||
|
Message-Id: <1489992447-13007-2-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
|
||||||
|
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
|
||||||
|
<mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
|
||||||
|
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Date: Mon, 20 Mar 2017 14:47:24 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
This patch adds documentation for devicetree bindings for LED support on
|
||||||
|
MT6323 PMIC.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
---
|
||||||
|
.../devicetree/bindings/leds/leds-mt6323.txt | 60 ++++++++++++++++++++++
|
||||||
|
1 file changed, 60 insertions(+)
|
||||||
|
create mode 100644 Documentation/devicetree/bindings/leds/leds-mt6323.txt
|
||||||
|
|
||||||
|
diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Documentation/devicetree/bindings/leds/leds-mt6323.txt
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000..ac38472
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/Documentation/devicetree/bindings/leds/leds-mt6323.txt
|
||||||
|
@@ -0,0 +1,60 @@
|
||||||
|
+Device Tree Bindings for LED support on MT6323 PMIC
|
||||||
|
+
|
||||||
|
+MT6323 LED controller is subfunction provided by MT6323 PMIC, so the LED
|
||||||
|
+controllers are defined as the subnode of the function node provided by MT6323
|
||||||
|
+PMIC controller that is being defined as one kind of Muti-Function Device (MFD)
|
||||||
|
+using shared bus called PMIC wrapper for each subfunction to access remote
|
||||||
|
+MT6323 PMIC hardware.
|
||||||
|
+
|
||||||
|
+For MT6323 MFD bindings see:
|
||||||
|
+Documentation/devicetree/bindings/mfd/mt6397.txt
|
||||||
|
+For MediaTek PMIC wrapper bindings see:
|
||||||
|
+Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
|
||||||
|
+
|
||||||
|
+Required properties:
|
||||||
|
+- compatible : Must be "mediatek,mt6323-led"
|
||||||
|
+- address-cells : Must be 1
|
||||||
|
+- size-cells : Must be 0
|
||||||
|
+
|
||||||
|
+Each led is represented as a child node of the mediatek,mt6323-led that
|
||||||
|
+describes the initial behavior for each LED physically and currently only four
|
||||||
|
+LED child nodes can be supported.
|
||||||
|
+
|
||||||
|
+Required properties for the LED child node:
|
||||||
|
+- reg : LED channel number (0..3)
|
||||||
|
+
|
||||||
|
+Optional properties for the LED child node:
|
||||||
|
+- label : See Documentation/devicetree/bindings/leds/common.txt
|
||||||
|
+- linux,default-trigger : See Documentation/devicetree/bindings/leds/common.txt
|
||||||
|
+- default-state: See Documentation/devicetree/bindings/leds/common.txt
|
||||||
|
+
|
||||||
|
+Example:
|
||||||
|
+
|
||||||
|
+ mt6323: pmic {
|
||||||
|
+ compatible = "mediatek,mt6323";
|
||||||
|
+
|
||||||
|
+ ...
|
||||||
|
+
|
||||||
|
+ mt6323led: leds {
|
||||||
|
+ compatible = "mediatek,mt6323-led";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+
|
||||||
|
+ led@0 {
|
||||||
|
+ reg = <0>;
|
||||||
|
+ label = "LED0";
|
||||||
|
+ linux,default-trigger = "timer";
|
||||||
|
+ default-state = "on";
|
||||||
|
+ };
|
||||||
|
+ led@1 {
|
||||||
|
+ reg = <1>;
|
||||||
|
+ label = "LED1";
|
||||||
|
+ default-state = "off";
|
||||||
|
+ };
|
||||||
|
+ led@2 {
|
||||||
|
+ reg = <2>;
|
||||||
|
+ label = "LED2";
|
||||||
|
+ default-state = "on";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
40
target/linux/mediatek/patches-4.9/0086-pmic-led1.patch
Normal file
40
target/linux/mediatek/patches-4.9/0086-pmic-led1.patch
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
From patchwork Mon Mar 20 06:47:25 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [v6,
|
||||||
|
2/4] dt-bindings: mfd: Add the description for LED as the sub module
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9633089
|
||||||
|
Message-Id: <1489992447-13007-3-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
|
||||||
|
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
|
||||||
|
<mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
|
||||||
|
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Date: Mon, 20 Mar 2017 14:47:25 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
This patch adds description for LED as the sub-module on MT6397/MT6323
|
||||||
|
multifunction device.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
---
|
||||||
|
Documentation/devicetree/bindings/mfd/mt6397.txt | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentation/devicetree/bindings/mfd/mt6397.txt
|
||||||
|
index c568d52..522a3bb 100644
|
||||||
|
--- a/Documentation/devicetree/bindings/mfd/mt6397.txt
|
||||||
|
+++ b/Documentation/devicetree/bindings/mfd/mt6397.txt
|
||||||
|
@@ -6,6 +6,7 @@ MT6397/MT6323 is a multifunction device with the following sub modules:
|
||||||
|
- Audio codec
|
||||||
|
- GPIO
|
||||||
|
- Clock
|
||||||
|
+- LED
|
||||||
|
|
||||||
|
It is interfaced to host controller using SPI interface by a proprietary hardware
|
||||||
|
called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap.
|
||||||
558
target/linux/mediatek/patches-4.9/0087-pmic-led2.patch
Normal file
558
target/linux/mediatek/patches-4.9/0087-pmic-led2.patch
Normal file
@ -0,0 +1,558 @@
|
|||||||
|
From patchwork Mon Mar 20 06:47:26 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [v6,3/4] leds: Add LED support for MT6323 PMIC
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9633081
|
||||||
|
Message-Id: <1489992447-13007-4-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
|
||||||
|
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
|
||||||
|
<mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
|
||||||
|
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Date: Mon, 20 Mar 2017 14:47:26 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
MT6323 PMIC is a multi-function device that includes LED function.
|
||||||
|
It allows attaching up to 4 LEDs which can either be on, off or dimmed
|
||||||
|
and/or blinked with the controller.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
Reviewed-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/leds/Kconfig | 8 +
|
||||||
|
drivers/leds/Makefile | 1 +
|
||||||
|
drivers/leds/leds-mt6323.c | 502 +++++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
3 files changed, 511 insertions(+)
|
||||||
|
create mode 100644 drivers/leds/leds-mt6323.c
|
||||||
|
|
||||||
|
Index: linux-4.9.17/drivers/leds/Kconfig
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/drivers/leds/Kconfig
|
||||||
|
+++ linux-4.9.17/drivers/leds/Kconfig
|
||||||
|
@@ -117,6 +117,14 @@ config LEDS_MIKROTIK_RB532
|
||||||
|
This option enables support for the so called "User LED" of
|
||||||
|
Mikrotik's Routerboard 532.
|
||||||
|
|
||||||
|
+config LEDS_MT6323
|
||||||
|
+ tristate "LED Support for Mediatek MT6323 PMIC"
|
||||||
|
+ depends on LEDS_CLASS
|
||||||
|
+ depends on MFD_MT6397
|
||||||
|
+ help
|
||||||
|
+ This option enables support for on-chip LED drivers found on
|
||||||
|
+ Mediatek MT6323 PMIC.
|
||||||
|
+
|
||||||
|
config LEDS_S3C24XX
|
||||||
|
tristate "LED Support for Samsung S3C24XX GPIO LEDs"
|
||||||
|
depends on LEDS_CLASS
|
||||||
|
Index: linux-4.9.17/drivers/leds/leds-mt6323.c
|
||||||
|
===================================================================
|
||||||
|
--- /dev/null
|
||||||
|
+++ linux-4.9.17/drivers/leds/leds-mt6323.c
|
||||||
|
@@ -0,0 +1,502 @@
|
||||||
|
+/*
|
||||||
|
+ * LED driver for Mediatek MT6323 PMIC
|
||||||
|
+ *
|
||||||
|
+ * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
|
||||||
|
+ *
|
||||||
|
+ * This program is free software; you can redistribute it and/or
|
||||||
|
+ * modify it under the terms of the GNU General Public License as
|
||||||
|
+ * published by the Free Software Foundation; either version 2 of
|
||||||
|
+ * the License, or (at your option) any later version.
|
||||||
|
+ *
|
||||||
|
+ * This program is distributed in the hope that it will be useful,
|
||||||
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+ * GNU General Public License for more details.
|
||||||
|
+ */
|
||||||
|
+#include <linux/kernel.h>
|
||||||
|
+#include <linux/leds.h>
|
||||||
|
+#include <linux/mfd/mt6323/registers.h>
|
||||||
|
+#include <linux/mfd/mt6397/core.h>
|
||||||
|
+#include <linux/module.h>
|
||||||
|
+#include <linux/of.h>
|
||||||
|
+#include <linux/platform_device.h>
|
||||||
|
+#include <linux/regmap.h>
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * Register field for MT6323_TOP_CKPDN0 to enable
|
||||||
|
+ * 32K clock common for LED device.
|
||||||
|
+ */
|
||||||
|
+#define MT6323_RG_DRV_32K_CK_PDN BIT(11)
|
||||||
|
+#define MT6323_RG_DRV_32K_CK_PDN_MASK BIT(11)
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * Register field for MT6323_TOP_CKPDN2 to enable
|
||||||
|
+ * individual clock for LED device.
|
||||||
|
+ */
|
||||||
|
+#define MT6323_RG_ISINK_CK_PDN(i) BIT(i)
|
||||||
|
+#define MT6323_RG_ISINK_CK_PDN_MASK(i) BIT(i)
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * Register field for MT6323_TOP_CKCON1 to select
|
||||||
|
+ * clock source.
|
||||||
|
+ */
|
||||||
|
+#define MT6323_RG_ISINK_CK_SEL_MASK(i) (BIT(10) << (i))
|
||||||
|
+
|
||||||
|
+/*
|
||||||
|
+ * Register for MT6323_ISINK_CON0 to setup the
|
||||||
|
+ * duty cycle of the blink.
|
||||||
|
+ */
|
||||||
|
+#define MT6323_ISINK_CON0(i) (MT6323_ISINK0_CON0 + 0x8 * (i))
|
||||||
|
+#define MT6323_ISINK_DIM_DUTY_MASK (0x1f << 8)
|
||||||
|
+#define MT6323_ISINK_DIM_DUTY(i) (((i) << 8) & \
|
||||||
|
+ MT6323_ISINK_DIM_DUTY_MASK)
|
||||||
|
+
|
||||||
|
+/* Register to setup the period of the blink. */
|
||||||
|
+#define MT6323_ISINK_CON1(i) (MT6323_ISINK0_CON1 + 0x8 * (i))
|
||||||
|
+#define MT6323_ISINK_DIM_FSEL_MASK (0xffff)
|
||||||
|
+#define MT6323_ISINK_DIM_FSEL(i) ((i) & MT6323_ISINK_DIM_FSEL_MASK)
|
||||||
|
+
|
||||||
|
+/* Register to control the brightness. */
|
||||||
|
+#define MT6323_ISINK_CON2(i) (MT6323_ISINK0_CON2 + 0x8 * (i))
|
||||||
|
+#define MT6323_ISINK_CH_STEP_SHIFT 12
|
||||||
|
+#define MT6323_ISINK_CH_STEP_MASK (0x7 << 12)
|
||||||
|
+#define MT6323_ISINK_CH_STEP(i) (((i) << 12) & \
|
||||||
|
+ MT6323_ISINK_CH_STEP_MASK)
|
||||||
|
+#define MT6323_ISINK_SFSTR0_TC_MASK (0x3 << 1)
|
||||||
|
+#define MT6323_ISINK_SFSTR0_TC(i) (((i) << 1) & \
|
||||||
|
+ MT6323_ISINK_SFSTR0_TC_MASK)
|
||||||
|
+#define MT6323_ISINK_SFSTR0_EN_MASK BIT(0)
|
||||||
|
+#define MT6323_ISINK_SFSTR0_EN BIT(0)
|
||||||
|
+
|
||||||
|
+/* Register to LED channel enablement. */
|
||||||
|
+#define MT6323_ISINK_CH_EN_MASK(i) BIT(i)
|
||||||
|
+#define MT6323_ISINK_CH_EN(i) BIT(i)
|
||||||
|
+
|
||||||
|
+#define MT6323_MAX_PERIOD 10000
|
||||||
|
+#define MT6323_MAX_LEDS 4
|
||||||
|
+#define MT6323_MAX_BRIGHTNESS 6
|
||||||
|
+#define MT6323_UNIT_DUTY 3125
|
||||||
|
+#define MT6323_CAL_HW_DUTY(o, p) DIV_ROUND_CLOSEST((o) * 100000ul,\
|
||||||
|
+ (p) * MT6323_UNIT_DUTY)
|
||||||
|
+
|
||||||
|
+struct mt6323_leds;
|
||||||
|
+
|
||||||
|
+/**
|
||||||
|
+ * struct mt6323_led - state container for the LED device
|
||||||
|
+ * @id: the identifier in MT6323 LED device
|
||||||
|
+ * @parent: the pointer to MT6323 LED controller
|
||||||
|
+ * @cdev: LED class device for this LED device
|
||||||
|
+ * @current_brightness: current state of the LED device
|
||||||
|
+ */
|
||||||
|
+struct mt6323_led {
|
||||||
|
+ int id;
|
||||||
|
+ struct mt6323_leds *parent;
|
||||||
|
+ struct led_classdev cdev;
|
||||||
|
+ enum led_brightness current_brightness;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+/**
|
||||||
|
+ * struct mt6323_leds - state container for holding LED controller
|
||||||
|
+ * of the driver
|
||||||
|
+ * @dev: the device pointer
|
||||||
|
+ * @hw: the underlying hardware providing shared
|
||||||
|
+ * bus for the register operations
|
||||||
|
+ * @lock: the lock among process context
|
||||||
|
+ * @led: the array that contains the state of individual
|
||||||
|
+ * LED device
|
||||||
|
+ */
|
||||||
|
+struct mt6323_leds {
|
||||||
|
+ struct device *dev;
|
||||||
|
+ struct mt6397_chip *hw;
|
||||||
|
+ /* protect among process context */
|
||||||
|
+ struct mutex lock;
|
||||||
|
+ struct mt6323_led *led[MT6323_MAX_LEDS];
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static int mt6323_led_hw_brightness(struct led_classdev *cdev,
|
||||||
|
+ enum led_brightness brightness)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ struct mt6323_leds *leds = led->parent;
|
||||||
|
+ struct regmap *regmap = leds->hw->regmap;
|
||||||
|
+ u32 con2_mask = 0, con2_val = 0;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * Setup current output for the corresponding
|
||||||
|
+ * brightness level.
|
||||||
|
+ */
|
||||||
|
+ con2_mask |= MT6323_ISINK_CH_STEP_MASK |
|
||||||
|
+ MT6323_ISINK_SFSTR0_TC_MASK |
|
||||||
|
+ MT6323_ISINK_SFSTR0_EN_MASK;
|
||||||
|
+ con2_val |= MT6323_ISINK_CH_STEP(brightness - 1) |
|
||||||
|
+ MT6323_ISINK_SFSTR0_TC(2) |
|
||||||
|
+ MT6323_ISINK_SFSTR0_EN;
|
||||||
|
+
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON2(led->id),
|
||||||
|
+ con2_mask, con2_val);
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_hw_off(struct led_classdev *cdev)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ struct mt6323_leds *leds = led->parent;
|
||||||
|
+ struct regmap *regmap = leds->hw->regmap;
|
||||||
|
+ unsigned int status;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ status = MT6323_ISINK_CH_EN(led->id);
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
|
||||||
|
+ MT6323_ISINK_CH_EN_MASK(led->id), ~status);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ usleep_range(100, 300);
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
|
||||||
|
+ MT6323_RG_ISINK_CK_PDN_MASK(led->id),
|
||||||
|
+ MT6323_RG_ISINK_CK_PDN(led->id));
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static enum led_brightness
|
||||||
|
+mt6323_get_led_hw_brightness(struct led_classdev *cdev)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ struct mt6323_leds *leds = led->parent;
|
||||||
|
+ struct regmap *regmap = leds->hw->regmap;
|
||||||
|
+ unsigned int status;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ ret = regmap_read(regmap, MT6323_TOP_CKPDN2, &status);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ if (status & MT6323_RG_ISINK_CK_PDN_MASK(led->id))
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ ret = regmap_read(regmap, MT6323_ISINK_EN_CTRL, &status);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ if (!(status & MT6323_ISINK_CH_EN(led->id)))
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ ret = regmap_read(regmap, MT6323_ISINK_CON2(led->id), &status);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ return ((status & MT6323_ISINK_CH_STEP_MASK)
|
||||||
|
+ >> MT6323_ISINK_CH_STEP_SHIFT) + 1;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_hw_on(struct led_classdev *cdev,
|
||||||
|
+ enum led_brightness brightness)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ struct mt6323_leds *leds = led->parent;
|
||||||
|
+ struct regmap *regmap = leds->hw->regmap;
|
||||||
|
+ unsigned int status;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * Setup required clock source, enable the corresponding
|
||||||
|
+ * clock and channel and let work with continuous blink as
|
||||||
|
+ * the default.
|
||||||
|
+ */
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_TOP_CKCON1,
|
||||||
|
+ MT6323_RG_ISINK_CK_SEL_MASK(led->id), 0);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ status = MT6323_RG_ISINK_CK_PDN(led->id);
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_TOP_CKPDN2,
|
||||||
|
+ MT6323_RG_ISINK_CK_PDN_MASK(led->id),
|
||||||
|
+ ~status);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ usleep_range(100, 300);
|
||||||
|
+
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_EN_CTRL,
|
||||||
|
+ MT6323_ISINK_CH_EN_MASK(led->id),
|
||||||
|
+ MT6323_ISINK_CH_EN(led->id));
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ ret = mt6323_led_hw_brightness(cdev, brightness);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
|
||||||
|
+ MT6323_ISINK_DIM_DUTY_MASK,
|
||||||
|
+ MT6323_ISINK_DIM_DUTY(31));
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
|
||||||
|
+ MT6323_ISINK_DIM_FSEL_MASK,
|
||||||
|
+ MT6323_ISINK_DIM_FSEL(1000));
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_set_blink(struct led_classdev *cdev,
|
||||||
|
+ unsigned long *delay_on,
|
||||||
|
+ unsigned long *delay_off)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ struct mt6323_leds *leds = led->parent;
|
||||||
|
+ struct regmap *regmap = leds->hw->regmap;
|
||||||
|
+ unsigned long period;
|
||||||
|
+ u8 duty_hw;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * Units are in ms, if over the hardware able
|
||||||
|
+ * to support, fallback into software blink
|
||||||
|
+ */
|
||||||
|
+ period = *delay_on + *delay_off;
|
||||||
|
+
|
||||||
|
+ if (period > MT6323_MAX_PERIOD)
|
||||||
|
+ return -EINVAL;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * LED subsystem requires a default user
|
||||||
|
+ * friendly blink pattern for the LED so using
|
||||||
|
+ * 1Hz duty cycle 50% here if without specific
|
||||||
|
+ * value delay_on and delay off being assigned.
|
||||||
|
+ */
|
||||||
|
+ if (!*delay_on && !*delay_off) {
|
||||||
|
+ *delay_on = 500;
|
||||||
|
+ *delay_off = 500;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * Calculate duty_hw based on the percentage of period during
|
||||||
|
+ * which the led is ON.
|
||||||
|
+ */
|
||||||
|
+ duty_hw = MT6323_CAL_HW_DUTY(*delay_on, period);
|
||||||
|
+
|
||||||
|
+ /* hardware doesn't support zero duty cycle. */
|
||||||
|
+ if (!duty_hw)
|
||||||
|
+ return -EINVAL;
|
||||||
|
+
|
||||||
|
+ mutex_lock(&leds->lock);
|
||||||
|
+ /*
|
||||||
|
+ * Set max_brightness as the software blink behavior
|
||||||
|
+ * when no blink brightness.
|
||||||
|
+ */
|
||||||
|
+ if (!led->current_brightness) {
|
||||||
|
+ ret = mt6323_led_hw_on(cdev, cdev->max_brightness);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ goto out;
|
||||||
|
+ led->current_brightness = cdev->max_brightness;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON0(led->id),
|
||||||
|
+ MT6323_ISINK_DIM_DUTY_MASK,
|
||||||
|
+ MT6323_ISINK_DIM_DUTY(duty_hw - 1));
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ goto out;
|
||||||
|
+
|
||||||
|
+ ret = regmap_update_bits(regmap, MT6323_ISINK_CON1(led->id),
|
||||||
|
+ MT6323_ISINK_DIM_FSEL_MASK,
|
||||||
|
+ MT6323_ISINK_DIM_FSEL(period - 1));
|
||||||
|
+out:
|
||||||
|
+ mutex_unlock(&leds->lock);
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_set_brightness(struct led_classdev *cdev,
|
||||||
|
+ enum led_brightness brightness)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ struct mt6323_leds *leds = led->parent;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ mutex_lock(&leds->lock);
|
||||||
|
+
|
||||||
|
+ if (!led->current_brightness && brightness) {
|
||||||
|
+ ret = mt6323_led_hw_on(cdev, brightness);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ goto out;
|
||||||
|
+ } else if (brightness) {
|
||||||
|
+ ret = mt6323_led_hw_brightness(cdev, brightness);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ goto out;
|
||||||
|
+ } else {
|
||||||
|
+ ret = mt6323_led_hw_off(cdev);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ goto out;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ led->current_brightness = brightness;
|
||||||
|
+out:
|
||||||
|
+ mutex_unlock(&leds->lock);
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_set_dt_default(struct led_classdev *cdev,
|
||||||
|
+ struct device_node *np)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_led *led = container_of(cdev, struct mt6323_led, cdev);
|
||||||
|
+ const char *state;
|
||||||
|
+ int ret = 0;
|
||||||
|
+
|
||||||
|
+ led->cdev.name = of_get_property(np, "label", NULL) ? : np->name;
|
||||||
|
+ led->cdev.default_trigger = of_get_property(np,
|
||||||
|
+ "linux,default-trigger",
|
||||||
|
+ NULL);
|
||||||
|
+
|
||||||
|
+ state = of_get_property(np, "default-state", NULL);
|
||||||
|
+ if (state) {
|
||||||
|
+ if (!strcmp(state, "keep")) {
|
||||||
|
+ ret = mt6323_get_led_hw_brightness(cdev);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+ led->current_brightness = ret;
|
||||||
|
+ ret = 0;
|
||||||
|
+ } else if (!strcmp(state, "on")) {
|
||||||
|
+ ret =
|
||||||
|
+ mt6323_led_set_brightness(cdev, cdev->max_brightness);
|
||||||
|
+ } else {
|
||||||
|
+ ret = mt6323_led_set_brightness(cdev, LED_OFF);
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_probe(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ struct device *dev = &pdev->dev;
|
||||||
|
+ struct device_node *np = pdev->dev.of_node;
|
||||||
|
+ struct device_node *child;
|
||||||
|
+ struct mt6397_chip *hw = dev_get_drvdata(pdev->dev.parent);
|
||||||
|
+ struct mt6323_leds *leds;
|
||||||
|
+ struct mt6323_led *led;
|
||||||
|
+ int ret;
|
||||||
|
+ unsigned int status;
|
||||||
|
+ u32 reg;
|
||||||
|
+
|
||||||
|
+ leds = devm_kzalloc(dev, sizeof(*leds), GFP_KERNEL);
|
||||||
|
+ if (!leds)
|
||||||
|
+ return -ENOMEM;
|
||||||
|
+
|
||||||
|
+ platform_set_drvdata(pdev, leds);
|
||||||
|
+ leds->dev = dev;
|
||||||
|
+
|
||||||
|
+ /*
|
||||||
|
+ * leds->hw points to the underlying bus for the register
|
||||||
|
+ * controlled.
|
||||||
|
+ */
|
||||||
|
+ leds->hw = hw;
|
||||||
|
+ mutex_init(&leds->lock);
|
||||||
|
+
|
||||||
|
+ status = MT6323_RG_DRV_32K_CK_PDN;
|
||||||
|
+ ret = regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
|
||||||
|
+ MT6323_RG_DRV_32K_CK_PDN_MASK, ~status);
|
||||||
|
+ if (ret < 0) {
|
||||||
|
+ dev_err(leds->dev,
|
||||||
|
+ "Failed to update MT6323_TOP_CKPDN0 Register\n");
|
||||||
|
+ return ret;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ for_each_available_child_of_node(np, child) {
|
||||||
|
+ ret = of_property_read_u32(child, "reg", ®);
|
||||||
|
+ if (ret) {
|
||||||
|
+ dev_err(dev, "Failed to read led 'reg' property\n");
|
||||||
|
+ goto put_child_node;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ if (reg < 0 || reg > MT6323_MAX_LEDS || leds->led[reg]) {
|
||||||
|
+ dev_err(dev, "Invalid led reg %u\n", reg);
|
||||||
|
+ ret = -EINVAL;
|
||||||
|
+ goto put_child_node;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ led = devm_kzalloc(dev, sizeof(*led), GFP_KERNEL);
|
||||||
|
+ if (!led) {
|
||||||
|
+ ret = -ENOMEM;
|
||||||
|
+ goto put_child_node;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ leds->led[reg] = led;
|
||||||
|
+ leds->led[reg]->id = reg;
|
||||||
|
+ leds->led[reg]->cdev.max_brightness = MT6323_MAX_BRIGHTNESS;
|
||||||
|
+ leds->led[reg]->cdev.brightness_set_blocking =
|
||||||
|
+ mt6323_led_set_brightness;
|
||||||
|
+ leds->led[reg]->cdev.blink_set = mt6323_led_set_blink;
|
||||||
|
+ leds->led[reg]->cdev.brightness_get =
|
||||||
|
+ mt6323_get_led_hw_brightness;
|
||||||
|
+ leds->led[reg]->parent = leds;
|
||||||
|
+
|
||||||
|
+ ret = mt6323_led_set_dt_default(&leds->led[reg]->cdev, child);
|
||||||
|
+ if (ret < 0) {
|
||||||
|
+ dev_err(leds->dev,
|
||||||
|
+ "Failed to LED set default from devicetree\n");
|
||||||
|
+ goto put_child_node;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ ret = devm_led_classdev_register(dev, &leds->led[reg]->cdev);
|
||||||
|
+ if (ret) {
|
||||||
|
+ dev_err(&pdev->dev, "Failed to register LED: %d\n",
|
||||||
|
+ ret);
|
||||||
|
+ goto put_child_node;
|
||||||
|
+ }
|
||||||
|
+ leds->led[reg]->cdev.dev->of_node = child;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+put_child_node:
|
||||||
|
+ of_node_put(child);
|
||||||
|
+ return ret;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mt6323_led_remove(struct platform_device *pdev)
|
||||||
|
+{
|
||||||
|
+ struct mt6323_leds *leds = platform_get_drvdata(pdev);
|
||||||
|
+ int i;
|
||||||
|
+
|
||||||
|
+ /* Turn the LEDs off on driver removal. */
|
||||||
|
+ for (i = 0 ; leds->led[i] ; i++)
|
||||||
|
+ mt6323_led_hw_off(&leds->led[i]->cdev);
|
||||||
|
+
|
||||||
|
+ regmap_update_bits(leds->hw->regmap, MT6323_TOP_CKPDN0,
|
||||||
|
+ MT6323_RG_DRV_32K_CK_PDN_MASK,
|
||||||
|
+ MT6323_RG_DRV_32K_CK_PDN);
|
||||||
|
+
|
||||||
|
+ mutex_destroy(&leds->lock);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct of_device_id mt6323_led_dt_match[] = {
|
||||||
|
+ { .compatible = "mediatek,mt6323-led" },
|
||||||
|
+ {},
|
||||||
|
+};
|
||||||
|
+MODULE_DEVICE_TABLE(of, mt6323_led_dt_match);
|
||||||
|
+
|
||||||
|
+static struct platform_driver mt6323_led_driver = {
|
||||||
|
+ .probe = mt6323_led_probe,
|
||||||
|
+ .remove = mt6323_led_remove,
|
||||||
|
+ .driver = {
|
||||||
|
+ .name = "mt6323-led",
|
||||||
|
+ .of_match_table = mt6323_led_dt_match,
|
||||||
|
+ },
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+module_platform_driver(mt6323_led_driver);
|
||||||
|
+
|
||||||
|
+MODULE_DESCRIPTION("LED driver for Mediatek MT6323 PMIC");
|
||||||
|
+MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
|
||||||
|
+MODULE_LICENSE("GPL");
|
||||||
44
target/linux/mediatek/patches-4.9/0088-pmic-led3.patch
Normal file
44
target/linux/mediatek/patches-4.9/0088-pmic-led3.patch
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
From patchwork Mon Mar 20 06:47:27 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [v6,
|
||||||
|
4/4] mfd: mt6397: Align the placement at which the mfd_cell of LED is
|
||||||
|
defined
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9633079
|
||||||
|
Message-Id: <1489992447-13007-5-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <rpurdie@rpsys.net>, <jacek.anaszewski@gmail.com>, <lee.jones@linaro.org>,
|
||||||
|
<matthias.bgg@gmail.com>, <pavel@ucw.cz>, <robh+dt@kernel.org>,
|
||||||
|
<mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, keyhaede@gmail.com,
|
||||||
|
Sean Wang <sean.wang@mediatek.com>, linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, linux-leds@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Date: Mon, 20 Mar 2017 14:47:27 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
Align the placement as which the mfd_cell of LED is defined as the other
|
||||||
|
members done on the structure.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
Acked-by: Lee Jones <lee.jones@linaro.org>
|
||||||
|
---
|
||||||
|
drivers/mfd/mt6397-core.c | 3 +--
|
||||||
|
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||||
|
|
||||||
|
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
|
||||||
|
index 8e601c8..04a601f 100644
|
||||||
|
--- a/drivers/mfd/mt6397-core.c
|
||||||
|
+++ b/drivers/mfd/mt6397-core.c
|
||||||
|
@@ -47,8 +47,7 @@
|
||||||
|
{
|
||||||
|
.name = "mt6323-regulator",
|
||||||
|
.of_compatible = "mediatek,mt6323-regulator"
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
+ }, {
|
||||||
|
.name = "mt6323-led",
|
||||||
|
.of_compatible = "mediatek,mt6323-led"
|
||||||
|
},
|
||||||
127
target/linux/mediatek/patches-4.9/0091-dsa1.patch
Normal file
127
target/linux/mediatek/patches-4.9/0091-dsa1.patch
Normal file
@ -0,0 +1,127 @@
|
|||||||
|
From patchwork Wed Mar 29 09:38:19 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [net-next,v3,1/5] dt-bindings: net: dsa: add Mediatek MT7530 binding
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9651093
|
||||||
|
Message-Id: <1490780303-18598-2-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
|
||||||
|
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
|
||||||
|
<robh+dt@kernel.org>, <mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
|
||||||
|
netdev@vger.kernel.org, sean.wang@mediatek.com,
|
||||||
|
linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
|
||||||
|
Date: Wed, 29 Mar 2017 17:38:19 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
Add device-tree binding for Mediatek MT7530 switch.
|
||||||
|
|
||||||
|
Cc: devicetree@vger.kernel.org
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
Acked-by: Rob Herring <robh@kernel.org>
|
||||||
|
---
|
||||||
|
.../devicetree/bindings/net/dsa/mt7530.txt | 92 ++++++++++++++++++++++
|
||||||
|
1 file changed, 92 insertions(+)
|
||||||
|
create mode 100644 Documentation/devicetree/bindings/net/dsa/mt7530.txt
|
||||||
|
|
||||||
|
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000..a9bc27b
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
|
||||||
|
@@ -0,0 +1,92 @@
|
||||||
|
+Mediatek MT7530 Ethernet switch
|
||||||
|
+================================
|
||||||
|
+
|
||||||
|
+Required properties:
|
||||||
|
+
|
||||||
|
+- compatible: Must be compatible = "mediatek,mt7530";
|
||||||
|
+- #address-cells: Must be 1.
|
||||||
|
+- #size-cells: Must be 0.
|
||||||
|
+- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
|
||||||
|
+ on multi-chip module belong to MT7623A has or the remotely standalone
|
||||||
|
+ chip as the function MT7623N reference board provided for.
|
||||||
|
+- core-supply: Phandle to the regulator node necessary for the core power.
|
||||||
|
+- io-supply: Phandle to the regulator node necessary for the I/O power.
|
||||||
|
+ See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
|
||||||
|
+ for details for the regulator setup on these boards.
|
||||||
|
+
|
||||||
|
+If the property mediatek,mcm isn't defined, following property is required
|
||||||
|
+
|
||||||
|
+- reset-gpios: Should be a gpio specifier for a reset line.
|
||||||
|
+
|
||||||
|
+Else, following properties are required
|
||||||
|
+
|
||||||
|
+- resets : Phandle pointing to the system reset controller with
|
||||||
|
+ line index for the ethsys.
|
||||||
|
+- reset-names : Should be set to "mcm".
|
||||||
|
+
|
||||||
|
+Required properties for the child nodes within ports container:
|
||||||
|
+
|
||||||
|
+- reg: Port address described must be 6 for CPU port and from 0 to 5 for
|
||||||
|
+ user ports.
|
||||||
|
+- phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
|
||||||
|
+ "cpu".
|
||||||
|
+
|
||||||
|
+See Documentation/devicetree/bindings/dsa/dsa.txt for a list of additional
|
||||||
|
+required, optional properties and how the integrated switch subnodes must
|
||||||
|
+be specified.
|
||||||
|
+
|
||||||
|
+Example:
|
||||||
|
+
|
||||||
|
+ &mdio0 {
|
||||||
|
+ switch@0 {
|
||||||
|
+ compatible = "mediatek,mt7530";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <0>;
|
||||||
|
+
|
||||||
|
+ core-supply = <&mt6323_vpa_reg>;
|
||||||
|
+ io-supply = <&mt6323_vemc3v3_reg>;
|
||||||
|
+ reset-gpios = <&pio 33 0>;
|
||||||
|
+
|
||||||
|
+ ports {
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ reg = <0>;
|
||||||
|
+ port@0 {
|
||||||
|
+ reg = <0>;
|
||||||
|
+ label = "lan0";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@1 {
|
||||||
|
+ reg = <1>;
|
||||||
|
+ label = "lan1";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@2 {
|
||||||
|
+ reg = <2>;
|
||||||
|
+ label = "lan2";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@3 {
|
||||||
|
+ reg = <3>;
|
||||||
|
+ label = "lan3";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@4 {
|
||||||
|
+ reg = <4>;
|
||||||
|
+ label = "wan";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ port@6 {
|
||||||
|
+ reg = <6>;
|
||||||
|
+ label = "cpu";
|
||||||
|
+ ethernet = <&gmac0>;
|
||||||
|
+ phy-mode = "trgmii";
|
||||||
|
+ fixed-link {
|
||||||
|
+ speed = <1000>;
|
||||||
|
+ full-duplex;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
@ -0,0 +1,95 @@
|
|||||||
|
From 81cdbda2a08375b9d5915567d2210bf2433e7332 Mon Sep 17 00:00:00 2001
|
||||||
|
From: John Crispin <john@phrozen.org>
|
||||||
|
Date: Sat, 23 Apr 2016 11:57:21 +0200
|
||||||
|
Subject: [PATCH 081/102] net-next: mediatek: fix DQL support
|
||||||
|
|
||||||
|
The MTK ethernet core has 2 MACs both sitting on the same DMA ring. The
|
||||||
|
current code will assign the TX traffic of each MAC to its own DQL. This
|
||||||
|
results in the amount of data, that DQL says is in the queue incorrect. As
|
||||||
|
the data from multiple devices is infact enqueued. This makes any decision
|
||||||
|
based on these value non deterministic. Fix this by tracking all TX
|
||||||
|
traffic, regardless of the MAC it belongs to in the DQL of all devices
|
||||||
|
using the DMA.
|
||||||
|
|
||||||
|
Signed-off-by: John Crispin <john@phrozen.org>
|
||||||
|
---
|
||||||
|
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 33 ++++++++++++++++-----------
|
||||||
|
1 file changed, 20 insertions(+), 13 deletions(-)
|
||||||
|
|
||||||
|
Index: linux-4.9.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.14.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
+++ linux-4.9.14/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
@@ -706,7 +706,16 @@ static int mtk_tx_map(struct sk_buff *sk
|
||||||
|
WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
|
||||||
|
(!nr_frags * TX_DMA_LS0)));
|
||||||
|
|
||||||
|
- netdev_sent_queue(dev, skb->len);
|
||||||
|
+ /* we have a single DMA ring so BQL needs to be updated for all devices
|
||||||
|
+ * sitting on this ring
|
||||||
|
+ */
|
||||||
|
+ for (i = 0; i < MTK_MAC_COUNT; i++) {
|
||||||
|
+ if (!eth->netdev[i])
|
||||||
|
+ continue;
|
||||||
|
+
|
||||||
|
+ netdev_sent_queue(eth->netdev[i], skb->len);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
skb_tx_timestamp(skb);
|
||||||
|
|
||||||
|
ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
|
||||||
|
@@ -998,21 +1007,18 @@ static int mtk_poll_tx(struct mtk_eth *e
|
||||||
|
struct mtk_tx_dma *desc;
|
||||||
|
struct sk_buff *skb;
|
||||||
|
struct mtk_tx_buf *tx_buf;
|
||||||
|
- unsigned int done[MTK_MAX_DEVS];
|
||||||
|
- unsigned int bytes[MTK_MAX_DEVS];
|
||||||
|
+ int total = 0, done = 0;
|
||||||
|
+ unsigned int bytes = 0;
|
||||||
|
u32 cpu, dma;
|
||||||
|
static int condition;
|
||||||
|
- int total = 0, i;
|
||||||
|
-
|
||||||
|
- memset(done, 0, sizeof(done));
|
||||||
|
- memset(bytes, 0, sizeof(bytes));
|
||||||
|
+ int i;
|
||||||
|
|
||||||
|
cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
|
||||||
|
dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
|
||||||
|
|
||||||
|
desc = mtk_qdma_phys_to_virt(ring, cpu);
|
||||||
|
|
||||||
|
- while ((cpu != dma) && budget) {
|
||||||
|
+ while ((cpu != dma) && done < budget) {
|
||||||
|
u32 next_cpu = desc->txd2;
|
||||||
|
int mac;
|
||||||
|
|
||||||
|
@@ -1032,9 +1038,8 @@ static int mtk_poll_tx(struct mtk_eth *e
|
||||||
|
}
|
||||||
|
|
||||||
|
if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
|
||||||
|
- bytes[mac] += skb->len;
|
||||||
|
- done[mac]++;
|
||||||
|
- budget--;
|
||||||
|
+ bytes += skb->len;
|
||||||
|
+ done++;
|
||||||
|
}
|
||||||
|
mtk_tx_unmap(eth, tx_buf);
|
||||||
|
|
||||||
|
@@ -1046,11 +1051,13 @@ static int mtk_poll_tx(struct mtk_eth *e
|
||||||
|
|
||||||
|
mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
|
||||||
|
|
||||||
|
+ /* we have a single DMA ring so BQL needs to be updated for all devices
|
||||||
|
+ * sitting on this ring
|
||||||
|
+ */
|
||||||
|
for (i = 0; i < MTK_MAC_COUNT; i++) {
|
||||||
|
- if (!eth->netdev[i] || !done[i])
|
||||||
|
+ if (!eth->netdev[i])
|
||||||
|
continue;
|
||||||
|
- netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
|
||||||
|
- total += done[i];
|
||||||
|
+ netdev_completed_queue(eth->netdev[i], done, bytes);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (mtk_queue_stopped(eth) &&
|
||||||
219
target/linux/mediatek/patches-4.9/0092-dsa2.patch
Normal file
219
target/linux/mediatek/patches-4.9/0092-dsa2.patch
Normal file
@ -0,0 +1,219 @@
|
|||||||
|
From patchwork Wed Mar 29 09:38:20 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [net-next,v3,2/5] net-next: dsa: add Mediatek tag RX/TX handler
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9651099
|
||||||
|
Message-Id: <1490780303-18598-3-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
|
||||||
|
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
|
||||||
|
<robh+dt@kernel.org>, <mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
|
||||||
|
netdev@vger.kernel.org, sean.wang@mediatek.com,
|
||||||
|
linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
|
||||||
|
Date: Wed, 29 Mar 2017 17:38:20 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
Add the support for the 4-bytes tag for DSA port distinguishing inserted
|
||||||
|
allowing receiving and transmitting the packet via the particular port.
|
||||||
|
The tag is being added after the source MAC address in the ethernet
|
||||||
|
header.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
Signed-off-by: Landen Chao <Landen.Chao@mediatek.com>
|
||||||
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||||
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||||
|
---
|
||||||
|
include/net/dsa.h | 1 +
|
||||||
|
net/dsa/Kconfig | 2 +
|
||||||
|
net/dsa/Makefile | 1 +
|
||||||
|
net/dsa/dsa.c | 3 ++
|
||||||
|
net/dsa/dsa_priv.h | 3 ++
|
||||||
|
net/dsa/tag_mtk.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||||
|
6 files changed, 127 insertions(+)
|
||||||
|
create mode 100644 net/dsa/tag_mtk.c
|
||||||
|
|
||||||
|
diff --git a/include/net/dsa.h b/include/net/dsa.h
|
||||||
|
index 4e13e69..3276547 100644
|
||||||
|
--- a/include/net/dsa.h
|
||||||
|
+++ b/include/net/dsa.h
|
||||||
|
@@ -31,6 +31,7 @@ enum dsa_tag_protocol {
|
||||||
|
DSA_TAG_PROTO_EDSA,
|
||||||
|
DSA_TAG_PROTO_BRCM,
|
||||||
|
DSA_TAG_PROTO_QCA,
|
||||||
|
+ DSA_TAG_PROTO_MTK,
|
||||||
|
DSA_TAG_LAST, /* MUST BE LAST */
|
||||||
|
};
|
||||||
|
|
||||||
|
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
|
||||||
|
index 9649238..d78789b 100644
|
||||||
|
--- a/net/dsa/Kconfig
|
||||||
|
+++ b/net/dsa/Kconfig
|
||||||
|
@@ -31,4 +31,6 @@ config NET_DSA_TAG_TRAILER
|
||||||
|
config NET_DSA_TAG_QCA
|
||||||
|
bool
|
||||||
|
|
||||||
|
+config NET_DSA_TAG_MTK
|
||||||
|
+ bool
|
||||||
|
endif
|
||||||
|
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
|
||||||
|
index 31d3437..9b1d478 100644
|
||||||
|
--- a/net/dsa/Makefile
|
||||||
|
+++ b/net/dsa/Makefile
|
||||||
|
@@ -8,3 +8,4 @@ dsa_core-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
|
||||||
|
dsa_core-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
|
||||||
|
dsa_core-$(CONFIG_NET_DSA_TAG_TRAILER) += tag_trailer.o
|
||||||
|
dsa_core-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
|
||||||
|
+dsa_core-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
|
||||||
|
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
|
||||||
|
index b6d4f6a..617f736 100644
|
||||||
|
--- a/net/dsa/dsa.c
|
||||||
|
+++ b/net/dsa/dsa.c
|
||||||
|
@@ -53,6 +53,9 @@ static struct sk_buff *dsa_slave_notag_xmit(struct sk_buff *skb,
|
||||||
|
#ifdef CONFIG_NET_DSA_TAG_QCA
|
||||||
|
[DSA_TAG_PROTO_QCA] = &qca_netdev_ops,
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_NET_DSA_TAG_MTK
|
||||||
|
+ [DSA_TAG_PROTO_MTK] = &mtk_netdev_ops,
|
||||||
|
+#endif
|
||||||
|
[DSA_TAG_PROTO_NONE] = &none_ops,
|
||||||
|
};
|
||||||
|
|
||||||
|
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
|
||||||
|
index 0706a51..2a31399 100644
|
||||||
|
--- a/net/dsa/dsa_priv.h
|
||||||
|
+++ b/net/dsa/dsa_priv.h
|
||||||
|
@@ -85,4 +85,7 @@ int dsa_slave_create(struct dsa_switch *ds, struct device *parent,
|
||||||
|
/* tag_qca.c */
|
||||||
|
extern const struct dsa_device_ops qca_netdev_ops;
|
||||||
|
|
||||||
|
+/* tag_mtk.c */
|
||||||
|
+extern const struct dsa_device_ops mtk_netdev_ops;
|
||||||
|
+
|
||||||
|
#endif
|
||||||
|
diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
|
||||||
|
new file mode 100644
|
||||||
|
index 0000000..833a9d6
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/net/dsa/tag_mtk.c
|
||||||
|
@@ -0,0 +1,117 @@
|
||||||
|
+/*
|
||||||
|
+ * Mediatek DSA Tag support
|
||||||
|
+ * Copyright (C) 2017 Landen Chao <landen.chao@mediatek.com>
|
||||||
|
+ * Sean Wang <sean.wang@mediatek.com>
|
||||||
|
+ * This program is free software; you can redistribute it and/or modify
|
||||||
|
+ * it under the terms of the GNU General Public License version 2 and
|
||||||
|
+ * only version 2 as published by the Free Software Foundation.
|
||||||
|
+ *
|
||||||
|
+ * This program is distributed in the hope that it will be useful,
|
||||||
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
+ * GNU General Public License for more details.
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <linux/etherdevice.h>
|
||||||
|
+#include "dsa_priv.h"
|
||||||
|
+
|
||||||
|
+#define MTK_HDR_LEN 4
|
||||||
|
+#define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
|
||||||
|
+#define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0)
|
||||||
|
+
|
||||||
|
+static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
|
||||||
|
+ struct net_device *dev)
|
||||||
|
+{
|
||||||
|
+ struct dsa_slave_priv *p = netdev_priv(dev);
|
||||||
|
+ u8 *mtk_tag;
|
||||||
|
+
|
||||||
|
+ if (skb_cow_head(skb, MTK_HDR_LEN) < 0)
|
||||||
|
+ goto out_free;
|
||||||
|
+
|
||||||
|
+ skb_push(skb, MTK_HDR_LEN);
|
||||||
|
+
|
||||||
|
+ memmove(skb->data, skb->data + MTK_HDR_LEN, 2 * ETH_ALEN);
|
||||||
|
+
|
||||||
|
+ /* Build the tag after the MAC Source Address */
|
||||||
|
+ mtk_tag = skb->data + 2 * ETH_ALEN;
|
||||||
|
+ mtk_tag[0] = 0;
|
||||||
|
+ mtk_tag[1] = (1 << p->dp->index) & MTK_HDR_XMIT_DP_BIT_MASK;
|
||||||
|
+ mtk_tag[2] = 0;
|
||||||
|
+ mtk_tag[3] = 0;
|
||||||
|
+
|
||||||
|
+ return skb;
|
||||||
|
+
|
||||||
|
+out_free:
|
||||||
|
+ kfree_skb(skb);
|
||||||
|
+ return NULL;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev,
|
||||||
|
+ struct packet_type *pt, struct net_device *orig_dev)
|
||||||
|
+{
|
||||||
|
+ struct dsa_switch_tree *dst = dev->dsa_ptr;
|
||||||
|
+ struct dsa_switch *ds;
|
||||||
|
+ int port;
|
||||||
|
+ __be16 *phdr, hdr;
|
||||||
|
+
|
||||||
|
+ if (unlikely(!dst))
|
||||||
|
+ goto out_drop;
|
||||||
|
+
|
||||||
|
+ skb = skb_unshare(skb, GFP_ATOMIC);
|
||||||
|
+ if (!skb)
|
||||||
|
+ goto out;
|
||||||
|
+
|
||||||
|
+ if (unlikely(!pskb_may_pull(skb, MTK_HDR_LEN)))
|
||||||
|
+ goto out_drop;
|
||||||
|
+
|
||||||
|
+ /* The MTK header is added by the switch between src addr
|
||||||
|
+ * and ethertype at this point, skb->data points to 2 bytes
|
||||||
|
+ * after src addr so header should be 2 bytes right before.
|
||||||
|
+ */
|
||||||
|
+ phdr = (__be16 *)(skb->data - 2);
|
||||||
|
+ hdr = ntohs(*phdr);
|
||||||
|
+
|
||||||
|
+ /* Remove MTK tag and recalculate checksum. */
|
||||||
|
+ skb_pull_rcsum(skb, MTK_HDR_LEN);
|
||||||
|
+
|
||||||
|
+ memmove(skb->data - ETH_HLEN,
|
||||||
|
+ skb->data - ETH_HLEN - MTK_HDR_LEN,
|
||||||
|
+ 2 * ETH_ALEN);
|
||||||
|
+
|
||||||
|
+ /* This protocol doesn't support cascading multiple
|
||||||
|
+ * switches so it's safe to assume the switch is first
|
||||||
|
+ * in the tree.
|
||||||
|
+ */
|
||||||
|
+ ds = dst->ds[0];
|
||||||
|
+ if (!ds)
|
||||||
|
+ goto out_drop;
|
||||||
|
+
|
||||||
|
+ /* Get source port information */
|
||||||
|
+ port = (hdr & MTK_HDR_RECV_SOURCE_PORT_MASK);
|
||||||
|
+ if (!ds->ports[port].netdev)
|
||||||
|
+ goto out_drop;
|
||||||
|
+
|
||||||
|
+ /* Update skb & forward the frame accordingly */
|
||||||
|
+ skb_push(skb, ETH_HLEN);
|
||||||
|
+
|
||||||
|
+ skb->pkt_type = PACKET_HOST;
|
||||||
|
+ skb->dev = ds->ports[port].netdev;
|
||||||
|
+ skb->protocol = eth_type_trans(skb, skb->dev);
|
||||||
|
+
|
||||||
|
+ skb->dev->stats.rx_packets++;
|
||||||
|
+ skb->dev->stats.rx_bytes += skb->len;
|
||||||
|
+
|
||||||
|
+ netif_receive_skb(skb);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+out_drop:
|
||||||
|
+ kfree_skb(skb);
|
||||||
|
+out:
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+const struct dsa_device_ops mtk_netdev_ops = {
|
||||||
|
+ .xmit = mtk_tag_xmit,
|
||||||
|
+ .rcv = mtk_tag_rcv,
|
||||||
|
+};
|
||||||
67
target/linux/mediatek/patches-4.9/0092-dsa3.patch
Normal file
67
target/linux/mediatek/patches-4.9/0092-dsa3.patch
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
From patchwork Wed Mar 29 09:38:21 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [net-next, v3,
|
||||||
|
3/5] net-next: ethernet: mediatek: add CDM able to recognize the tag
|
||||||
|
for DSA
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9651091
|
||||||
|
Message-Id: <1490780303-18598-4-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
|
||||||
|
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
|
||||||
|
<robh+dt@kernel.org>, <mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
|
||||||
|
netdev@vger.kernel.org, sean.wang@mediatek.com,
|
||||||
|
linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
|
||||||
|
Date: Wed, 29 Mar 2017 17:38:21 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
The patch adds the setup for allowing CDM can recognize these packets with
|
||||||
|
carrying port-distinguishing tag. Otherwise, these tagging packets will be
|
||||||
|
handled incorrectly by CDM. The setup is also working out for general
|
||||||
|
untag packets as well.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
Signed-off-by: Landen Chao <Landen.Chao@mediatek.com>
|
||||||
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||||
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 ++++++
|
||||||
|
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++++
|
||||||
|
2 files changed, 10 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
index 9e75768..c21ed99 100644
|
||||||
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
@@ -1846,6 +1846,12 @@ static int mtk_hw_init(struct mtk_eth *eth)
|
||||||
|
/* GE2, Force 1000M/FD, FC ON */
|
||||||
|
mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
|
||||||
|
|
||||||
|
+ /* Indicates CDM to parse the MTK special tag from CPU
|
||||||
|
+ * which also is working out for untag packets.
|
||||||
|
+ */
|
||||||
|
+ val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
|
||||||
|
+ mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
|
||||||
|
+
|
||||||
|
/* Enable RX VLan Offloading */
|
||||||
|
mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
|
||||||
|
|
||||||
|
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||||
|
index 99b1c8e..996024d 100644
|
||||||
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||||
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||||
|
@@ -70,6 +70,10 @@
|
||||||
|
/* Frame Engine Interrupt Grouping Register */
|
||||||
|
#define MTK_FE_INT_GRP 0x20
|
||||||
|
|
||||||
|
+/* CDMP Ingress Control Register */
|
||||||
|
+#define MTK_CDMQ_IG_CTRL 0x1400
|
||||||
|
+#define MTK_CDMQ_STAG_EN BIT(0)
|
||||||
|
+
|
||||||
|
/* CDMP Exgress Control Register */
|
||||||
|
#define MTK_CDMP_EG_CTRL 0x404
|
||||||
|
|
||||||
46
target/linux/mediatek/patches-4.9/0092-dsa4.patch
Normal file
46
target/linux/mediatek/patches-4.9/0092-dsa4.patch
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
From patchwork Wed Mar 29 09:38:22 2017
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
Subject: [net-next, v3,
|
||||||
|
4/5] net-next: ethernet: mediatek: add device_node of GMAC pointing
|
||||||
|
into the netdev instance
|
||||||
|
From: sean.wang@mediatek.com
|
||||||
|
X-Patchwork-Id: 9651097
|
||||||
|
Message-Id: <1490780303-18598-5-git-send-email-sean.wang@mediatek.com>
|
||||||
|
To: <andrew@lunn.ch>, <f.fainelli@gmail.com>,
|
||||||
|
<vivien.didelot@savoirfairelinux.com>, <matthias.bgg@gmail.com>,
|
||||||
|
<robh+dt@kernel.org>, <mark.rutland@arm.com>
|
||||||
|
Cc: devicetree@vger.kernel.org, Landen.Chao@mediatek.com, keyhaede@gmail.com,
|
||||||
|
netdev@vger.kernel.org, sean.wang@mediatek.com,
|
||||||
|
linux-kernel@vger.kernel.org,
|
||||||
|
linux-mediatek@lists.infradead.org, objelf@gmail.com, davem@davemloft.net
|
||||||
|
Date: Wed, 29 Mar 2017 17:38:22 +0800
|
||||||
|
|
||||||
|
From: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
|
||||||
|
the patch adds the setup of the corresponding device node of GMAC into the
|
||||||
|
netdev instance which could allow other modules such as DSA to find the
|
||||||
|
instance through the node in dt-bindings using of_find_net_device_by_node()
|
||||||
|
call.
|
||||||
|
|
||||||
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
||||||
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
||||||
|
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 2 ++
|
||||||
|
1 file changed, 2 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
index c21ed99..84b09a4 100644
|
||||||
|
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
@@ -2323,6 +2323,8 @@ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
|
||||||
|
eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
|
||||||
|
|
||||||
|
eth->netdev[id]->irq = eth->irq[0];
|
||||||
|
+ eth->netdev[id]->dev.of_node = np;
|
||||||
|
+
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
free_netdev:
|
||||||
1608
target/linux/mediatek/patches-4.9/0092-dsa5.patch
Normal file
1608
target/linux/mediatek/patches-4.9/0092-dsa5.patch
Normal file
File diff suppressed because it is too large
Load Diff
98
target/linux/mediatek/patches-4.9/0093-dsa-compat.patch
Normal file
98
target/linux/mediatek/patches-4.9/0093-dsa-compat.patch
Normal file
@ -0,0 +1,98 @@
|
|||||||
|
Index: linux-4.9.17/drivers/net/dsa/mt7530.c
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/drivers/net/dsa/mt7530.c
|
||||||
|
+++ linux-4.9.17/drivers/net/dsa/mt7530.c
|
||||||
|
@@ -834,6 +834,7 @@ mt7530_port_bridge_join(struct dsa_switc
|
||||||
|
int i;
|
||||||
|
|
||||||
|
mutex_lock(&priv->reg_mutex);
|
||||||
|
+ priv->bridge_dev[port] = bridge;
|
||||||
|
|
||||||
|
for (i = 0; i < MT7530_NUM_PORTS; i++) {
|
||||||
|
/* Add this port to the port matrix of the other ports in the
|
||||||
|
@@ -841,7 +842,7 @@ mt7530_port_bridge_join(struct dsa_switc
|
||||||
|
* and not being setup until the port becomes enabled.
|
||||||
|
*/
|
||||||
|
if (ds->enabled_port_mask & BIT(i) && i != port) {
|
||||||
|
- if (ds->ports[i].bridge_dev != bridge)
|
||||||
|
+ if (priv->bridge_dev[i] != bridge)
|
||||||
|
continue;
|
||||||
|
if (priv->ports[i].enable)
|
||||||
|
mt7530_set(priv, MT7530_PCR_P(i),
|
||||||
|
@@ -864,8 +865,7 @@ mt7530_port_bridge_join(struct dsa_switc
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
-mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
|
||||||
|
- struct net_device *bridge)
|
||||||
|
+mt7530_port_bridge_leave(struct dsa_switch *ds, int port)
|
||||||
|
{
|
||||||
|
struct mt7530_priv *priv = ds->priv;
|
||||||
|
int i;
|
||||||
|
@@ -878,7 +878,7 @@ mt7530_port_bridge_leave(struct dsa_swit
|
||||||
|
* is kept and not being setup until the port becomes enabled.
|
||||||
|
*/
|
||||||
|
if (ds->enabled_port_mask & BIT(i) && i != port) {
|
||||||
|
- if (ds->ports[i].bridge_dev != bridge)
|
||||||
|
+ if (priv->bridge_dev[i] != priv->bridge_dev[port])
|
||||||
|
continue;
|
||||||
|
if (priv->ports[i].enable)
|
||||||
|
mt7530_clear(priv, MT7530_PCR_P(i),
|
||||||
|
@@ -890,6 +890,7 @@ mt7530_port_bridge_leave(struct dsa_swit
|
||||||
|
/* Set the cpu port to be the only one in the port matrix of
|
||||||
|
* this port.
|
||||||
|
*/
|
||||||
|
+ priv->bridge_dev[port] = NULL;
|
||||||
|
if (priv->ports[port].enable)
|
||||||
|
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
|
||||||
|
PCR_MATRIX(BIT(MT7530_CPU_PORT)));
|
||||||
|
@@ -1033,7 +1034,7 @@ mt7530_probe(struct mdio_device *mdiodev
|
||||||
|
if (!priv)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
- priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
|
||||||
|
+ priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
|
||||||
|
if (!priv->ds)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
@@ -1076,12 +1077,13 @@ mt7530_probe(struct mdio_device *mdiodev
|
||||||
|
priv->bus = mdiodev->bus;
|
||||||
|
priv->dev = &mdiodev->dev;
|
||||||
|
priv->ds->priv = priv;
|
||||||
|
+ priv->ds->dev = &mdiodev->dev;
|
||||||
|
priv->ds->ops = &mt7530_switch_ops;
|
||||||
|
mutex_init(&priv->reg_mutex);
|
||||||
|
lpriv = priv;
|
||||||
|
dev_set_drvdata(&mdiodev->dev, priv);
|
||||||
|
|
||||||
|
- return dsa_register_switch(priv->ds, &mdiodev->dev);
|
||||||
|
+ return dsa_register_switch(priv->ds, priv->ds->dev->of_node);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void
|
||||||
|
Index: linux-4.9.17/drivers/net/dsa/mt7530.h
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/drivers/net/dsa/mt7530.h
|
||||||
|
+++ linux-4.9.17/drivers/net/dsa/mt7530.h
|
||||||
|
@@ -379,6 +379,8 @@ struct mt7530_priv {
|
||||||
|
struct mt7530_port ports[MT7530_NUM_PORTS];
|
||||||
|
/* protect among processes for registers access*/
|
||||||
|
struct mutex reg_mutex;
|
||||||
|
+
|
||||||
|
+ struct net_device *bridge_dev[MT7530_NUM_PORTS];
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mt7530_hw_stats {
|
||||||
|
Index: linux-4.9.17/net/dsa/tag_mtk.c
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/net/dsa/tag_mtk.c
|
||||||
|
+++ linux-4.9.17/net/dsa/tag_mtk.c
|
||||||
|
@@ -35,7 +35,7 @@ static struct sk_buff *mtk_tag_xmit(stru
|
||||||
|
/* Build the tag after the MAC Source Address */
|
||||||
|
mtk_tag = skb->data + 2 * ETH_ALEN;
|
||||||
|
mtk_tag[0] = 0;
|
||||||
|
- mtk_tag[1] = (1 << p->dp->index) & MTK_HDR_XMIT_DP_BIT_MASK;
|
||||||
|
+ mtk_tag[1] = (1 << p->port) & MTK_HDR_XMIT_DP_BIT_MASK;
|
||||||
|
mtk_tag[2] = 0;
|
||||||
|
mtk_tag[3] = 0;
|
||||||
|
|
||||||
40
target/linux/mediatek/patches-4.9/0094-net-affinity.patch
Normal file
40
target/linux/mediatek/patches-4.9/0094-net-affinity.patch
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
Index: linux-4.9.17/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
+++ linux-4.9.17/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||||
|
@@ -2459,15 +2459,23 @@ static int mtk_probe(struct platform_dev
|
||||||
|
goto err_deinit_hw;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ for (i = 0; i < 3; i++) {
|
||||||
|
+ int cpu = i % num_online_cpus();
|
||||||
|
+
|
||||||
|
+ cpumask_set_cpu(cpu, ð->affinity_mask[i]);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
|
||||||
|
dev_name(eth->dev), eth);
|
||||||
|
if (err)
|
||||||
|
goto err_free_dev;
|
||||||
|
+ irq_set_affinity_hint(eth->irq[1], ð->affinity_mask[1]);
|
||||||
|
|
||||||
|
err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
|
||||||
|
dev_name(eth->dev), eth);
|
||||||
|
if (err)
|
||||||
|
goto err_free_dev;
|
||||||
|
+ irq_set_affinity_hint(eth->irq[2], ð->affinity_mask[2]);
|
||||||
|
|
||||||
|
err = mtk_mdio_init(eth);
|
||||||
|
if (err)
|
||||||
|
Index: linux-4.9.17/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||||
|
===================================================================
|
||||||
|
--- linux-4.9.17.orig/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||||
|
+++ linux-4.9.17/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||||
|
@@ -539,6 +539,7 @@ struct mtk_eth {
|
||||||
|
struct net_device *netdev[MTK_MAX_DEVS];
|
||||||
|
struct mtk_mac *mac[MTK_MAX_DEVS];
|
||||||
|
int irq[3];
|
||||||
|
+ cpumask_t affinity_mask[3];
|
||||||
|
u32 msg_enable;
|
||||||
|
unsigned long sysclk;
|
||||||
|
struct regmap *ethsys;
|
||||||
File diff suppressed because it is too large
Load Diff
@ -7,9 +7,6 @@
|
|||||||
|
|
||||||
define Profile/Default
|
define Profile/Default
|
||||||
NAME:=Default Profile (minimum package set)
|
NAME:=Default Profile (minimum package set)
|
||||||
PACKAGES:= \
|
|
||||||
kmod-usb-core kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \
|
|
||||||
kmod-usb3
|
|
||||||
endef
|
endef
|
||||||
|
|
||||||
define Profile/Default/Description
|
define Profile/Default/Description
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user