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realtek: add support for D-Link DGS-1210-20
Hardware specification ---------------------- * RTL8382M SoC, 1 MIPS 4KEc core @ 500MHz * 128MB DRAM * 32MB NOR Flash * 16 x 10/100/1000BASE-T ports - Internal PHY with 8 ports (RTL8218B) - External PHY with 8 ports (RTL8218B) * 4 x Gigabit RJ45/SFP Combo ports - External PHY with 4 SFP ports (RTL8214FC) * Power LED * Reset button on front panel * UART (115200 8N1) via unpopulated standard 0.1" pin header marked J6 UART pinout ----------- [o]ooo|J6 | ||`------ GND | |`------- RX | `-------- TX `---------- Vcc (3V3) Boot initramfs image from U-Boot -------------------------------- 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. Press CTRL+C keys to get into real U-Boot prompt 3. Init network with `rtk network on` command 4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl838x-d-link_dgs-1210-20-initramfs-kernel.bin` command 5. Boot the image with `bootm` command To install, upload the sysupgrade image to the OEM webpage or sysupgrade from the system running from initramfs image. It has been developed and tested on device with F1 revision. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> [correct initramfs image name] Signed-off-by: Sander Vanheule <sander@svanheule.net>
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@ -9,6 +9,7 @@ board=$(board_name)
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case "$board" in
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case "$board" in
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d-link,dgs-1210-16|\
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d-link,dgs-1210-16|\
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d-link,dgs-1210-20|\
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d-link,dgs-1210-28|\
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d-link,dgs-1210-28|\
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d-link,dgs-1210-10p|\
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d-link,dgs-1210-10p|\
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zyxel,gs1900-8|\
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zyxel,gs1900-8|\
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104
target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts
Normal file
104
target/linux/realtek/dts-5.10/rtl8382_d-link_dgs-1210-20.dts
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@ -0,0 +1,104 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl8382_d-link_dgs-1210.dtsi"
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/ {
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compatible = "d-link,dgs-1210-20", "realtek,rtl838x-soc";
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model = "D-Link DGS-1210-20";
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
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open-source;
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio1: rtl8231-gpio {
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compatible = "realtek,rtl8231-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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indirect-access-bus-id = <0>;
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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EXTERNAL_SFP_PHY(24)
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EXTERNAL_SFP_PHY(25)
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EXTERNAL_SFP_PHY(26)
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EXTERNAL_SFP_PHY(27)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 1, qsgmii)
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SWITCH_PORT(1, 2, qsgmii)
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SWITCH_PORT(2, 3, qsgmii)
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SWITCH_PORT(3, 4, qsgmii)
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SWITCH_PORT(4, 5, qsgmii)
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SWITCH_PORT(5, 6, qsgmii)
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SWITCH_PORT(6, 7, qsgmii)
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SWITCH_PORT(7, 8, qsgmii)
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SWITCH_PORT(8, 9, internal)
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SWITCH_PORT(9, 10, internal)
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SWITCH_PORT(10, 11, internal)
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SWITCH_PORT(11, 12, internal)
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SWITCH_PORT(12, 13, internal)
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SWITCH_PORT(13, 14, internal)
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SWITCH_PORT(14, 15, internal)
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SWITCH_PORT(15, 16, internal)
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SWITCH_PORT(24, 17, qsgmii)
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SWITCH_PORT(25, 18, qsgmii)
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SWITCH_PORT(26, 19, qsgmii)
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SWITCH_PORT(27, 20, qsgmii)
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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@ -30,6 +30,12 @@ define Device/d-link_dgs-1210-16
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endef
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endef
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TARGET_DEVICES += d-link_dgs-1210-16
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TARGET_DEVICES += d-link_dgs-1210-16
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define Device/d-link_dgs-1210-20
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$(Device/d-link_dgs-1210)
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DEVICE_MODEL := DGS-1210-20
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endef
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TARGET_DEVICES += d-link_dgs-1210-20
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define Device/d-link_dgs-1210-28
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define Device/d-link_dgs-1210-28
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$(Device/d-link_dgs-1210)
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$(Device/d-link_dgs-1210)
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DEVICE_MODEL := DGS-1210-28
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DEVICE_MODEL := DGS-1210-28
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