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ramips: add MT7620 MIB support for switch and port
Move definitions to header. Replace array size definitions with macro. Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com> [merged into 0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch] Signed-off-by: Mathias Kresin <dev@kresin.me> Acked-by: John Crispin <john@phrozen.org>
This commit is contained in:
parent
8459d85fa3
commit
5f38d1ad85
@ -5,13 +5,15 @@ Subject: [PATCH 513/513] net: mediatek: add swconfig driver for gsw_mt762x
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/net/ethernet/mediatek/Makefile | 4 +-
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drivers/net/ethernet/mediatek/mt7530.c | 804 +++++++++++++++++++++++++++
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drivers/net/ethernet/mediatek/mt7530.h | 20 +
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +-
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
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drivers/net/ethernet/mediatek/soc_mt7620.c | 1 +
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6 files changed, 835 insertions(+), 4 deletions(-)
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drivers/net/ethernet/mediatek/Makefile | 4 +-
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drivers/net/ethernet/mediatek/gsw_mt7620.c | 3 +
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drivers/net/ethernet/mediatek/gsw_mt7620.h | 3 +
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drivers/net/ethernet/mediatek/mt7530.c | 884 ++++++++++++++++++++++++++++
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drivers/net/ethernet/mediatek/mt7530.h | 186 ++++++
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 9 +-
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
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drivers/net/ethernet/mediatek/soc_mt7620.c | 1 +
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8 files changed, 1087 insertions(+), 4 deletions(-)
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create mode 100644 drivers/net/ethernet/mediatek/mt7530.c
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create mode 100644 drivers/net/ethernet/mediatek/mt7530.h
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@ -26,9 +28,40 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620) += gsw_mt7620.o mt7530.o
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+obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621) += gsw_mt7621.o mt7530.o
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk-eth-soc.o
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--- a/drivers/net/ethernet/mediatek/gsw_mt7620.c
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+++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
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@@ -67,6 +67,9 @@ static void mt7620_hw_init(struct mt7620
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rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
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mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
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+ /* Enable MIB stats */
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+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
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+
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if (of_property_read_bool(np, "mediatek,mt7530")) {
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u32 val;
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--- a/drivers/net/ethernet/mediatek/gsw_mt7620.h
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+++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
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@@ -35,6 +35,8 @@
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#define GSW_MDIO_ADDR_SHIFT 20
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#define GSW_MDIO_REG_SHIFT 25
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+#define GSW_REG_MIB_CNT_EN 0x4000
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+
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#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
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#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
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#define GSW_REG_SMACCR0 0x3fE4
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@@ -76,6 +78,7 @@
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#define PHY_PRE_EN BIT(30)
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#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
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+
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enum {
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/* Global attributes. */
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GSW_ATTR_ENABLE_VLAN,
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/mt7530.c
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@@ -0,0 +1,804 @@
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@@ -0,0 +1,884 @@
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+/*
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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@ -41,6 +74,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
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+ */
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+
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+#include <linux/if.h>
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@ -107,49 +141,50 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ const char *name;
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+};
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+
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+#define MT7621_MIB_COUNTER_BASE 0x4000
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+#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
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+#define MT7621_STATS_TDPC 0x00
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+#define MT7621_STATS_TCRC 0x04
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+#define MT7621_STATS_TUPC 0x08
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+#define MT7621_STATS_TMPC 0x0C
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+#define MT7621_STATS_TBPC 0x10
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+#define MT7621_STATS_TCEC 0x14
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+#define MT7621_STATS_TSCEC 0x18
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+#define MT7621_STATS_TMCEC 0x1C
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+#define MT7621_STATS_TDEC 0x20
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+#define MT7621_STATS_TLCEC 0x24
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+#define MT7621_STATS_TXCEC 0x28
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+#define MT7621_STATS_TPPC 0x2C
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+#define MT7621_STATS_TL64PC 0x30
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+#define MT7621_STATS_TL65PC 0x34
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+#define MT7621_STATS_TL128PC 0x38
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+#define MT7621_STATS_TL256PC 0x3C
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+#define MT7621_STATS_TL512PC 0x40
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+#define MT7621_STATS_TL1024PC 0x44
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+#define MT7621_STATS_TOC 0x48
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+#define MT7621_STATS_RDPC 0x60
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+#define MT7621_STATS_RFPC 0x64
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+#define MT7621_STATS_RUPC 0x68
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+#define MT7621_STATS_RMPC 0x6C
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+#define MT7621_STATS_RBPC 0x70
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+#define MT7621_STATS_RAEPC 0x74
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+#define MT7621_STATS_RCEPC 0x78
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+#define MT7621_STATS_RUSPC 0x7C
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+#define MT7621_STATS_RFEPC 0x80
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+#define MT7621_STATS_ROSPC 0x84
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+#define MT7621_STATS_RJEPC 0x88
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+#define MT7621_STATS_RPPC 0x8C
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+#define MT7621_STATS_RL64PC 0x90
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+#define MT7621_STATS_RL65PC 0x94
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+#define MT7621_STATS_RL128PC 0x98
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+#define MT7621_STATS_RL256PC 0x9C
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+#define MT7621_STATS_RL512PC 0xA0
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+#define MT7621_STATS_RL1024PC 0xA4
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+#define MT7621_STATS_ROC 0xA8
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+#define MT7621_STATS_RDPC_CTRL 0xB0
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+#define MT7621_STATS_RDPC_ING 0xB4
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+#define MT7621_STATS_RDPC_ARL 0xB8
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+static const struct mt7xxx_mib_desc mt7620_mibs[] = {
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+ MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
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+ MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
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+};
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+
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+static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
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+ MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
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+};
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+
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+static const struct mt7xxx_mib_desc mt7621_mibs[] = {
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+ MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
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@ -650,35 +685,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ return 0;
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+}
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+
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+static const struct switch_attr mt7530_global[] = {
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+ {
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+ .type = SWITCH_TYPE_INT,
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+ .name = "enable_vlan",
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+ .description = "VLAN mode (1:enabled)",
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+ .max = 1,
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+ .id = MT7530_ATTR_ENABLE_VLAN,
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+ .get = mt7530_get_vlan_enable,
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+ .set = mt7530_set_vlan_enable,
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+ },
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+};
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+
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+static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
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+{
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+ unsigned int port_base;
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+ u64 t;
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+ u64 lo;
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+
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+ port_base = MT7621_MIB_COUNTER_BASE +
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+ MT7621_MIB_COUNTER_PORT_OFFSET * port;
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+
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+ t = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
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+ lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
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+ if (mt7621_mibs[i].size == 2) {
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+ u64 hi;
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+
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+ hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
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+ t |= hi << 32;
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+ lo |= hi << 32;
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+ }
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+
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+ return t;
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+ return lo;
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+}
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+
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+static int mt7621_sw_get_port_mib(struct switch_dev *dev,
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@ -695,7 +718,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ len += snprintf(buf + len, sizeof(buf) - len,
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+ "Port %d MIB counters\n", val->port_vlan);
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+
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+ for (i = 0; i < sizeof(mt7621_mibs) / sizeof(*mt7621_mibs); ++i) {
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+ for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
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+ u64 counter;
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+ len += snprintf(buf + len, sizeof(buf) - len,
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+ "%-11s: ", mt7621_mibs[i].name);
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@ -709,6 +732,89 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+ return 0;
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+}
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+
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+static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
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+{
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+ return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
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+}
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+
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+static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
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+{
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+ return mt7530_r32(priv,
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+ MT7620_MIB_COUNTER_BASE_PORT +
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+ (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
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+ mt7620_port_mibs[i].offset);
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+}
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+
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+static int mt7530_sw_get_mib(struct switch_dev *dev,
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+ const struct switch_attr *attr,
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+ struct switch_val *val)
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+{
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+ static char buf[4096];
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+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
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+ int i, len = 0;
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+
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+ len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
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+
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+ for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
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+ u64 counter;
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+ len += snprintf(buf + len, sizeof(buf) - len,
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+ "%-11s: ", mt7620_mibs[i].name);
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+ counter = get_mib_counter_7620(priv, i);
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+ len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
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+ counter);
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+ }
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+
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+ val->value.s = buf;
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+ val->len = len;
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+ return 0;
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+}
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+
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+static int mt7530_sw_get_port_mib(struct switch_dev *dev,
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+ const struct switch_attr *attr,
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+ struct switch_val *val)
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+{
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+ static char buf[4096];
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+ struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
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+ int i, len = 0;
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+
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+ if (val->port_vlan >= MT7530_NUM_PORTS)
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+ return -EINVAL;
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+
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+ len += snprintf(buf + len, sizeof(buf) - len,
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+ "Port %d MIB counters\n", val->port_vlan);
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+
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+ for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
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+ u64 counter;
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+ len += snprintf(buf + len, sizeof(buf) - len,
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+ "%-11s: ", mt7620_port_mibs[i].name);
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+ counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
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+ len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
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+ counter);
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+ }
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+
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+ val->value.s = buf;
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+ val->len = len;
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+ return 0;
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+}
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+
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+static const struct switch_attr mt7530_global[] = {
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+ {
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+ .type = SWITCH_TYPE_INT,
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+ .name = "enable_vlan",
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+ .description = "VLAN mode (1:enabled)",
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+ .max = 1,
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+ .id = MT7530_ATTR_ENABLE_VLAN,
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+ .get = mt7530_get_vlan_enable,
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+ .set = mt7530_set_vlan_enable,
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+ }, {
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+ .type = SWITCH_TYPE_STRING,
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+ .name = "mib",
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+ .description = "Get MIB counters for switch",
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+ .get = mt7530_sw_get_mib,
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+ .set = NULL,
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+ },
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+};
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+
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+static const struct switch_attr mt7621_port[] = {
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+ {
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+ .type = SWITCH_TYPE_STRING,
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@ -720,6 +826,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+};
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+
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+static const struct switch_attr mt7530_port[] = {
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+ {
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+ .type = SWITCH_TYPE_STRING,
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+ .name = "mib",
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+ .description = "Get MIB counters for port",
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+ .get = mt7530_sw_get_port_mib,
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+ .set = NULL,
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+ },
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+};
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+
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+static const struct switch_attr mt7530_vlan[] = {
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@ -835,7 +948,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
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+}
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--- /dev/null
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||||
+++ b/drivers/net/ethernet/mediatek/mt7530.h
|
||||
@@ -0,0 +1,20 @@
|
||||
@@ -0,0 +1,186 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
@ -848,11 +961,177 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
|
||||
+ * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _MT7530_H__
|
||||
+#define _MT7530_H__
|
||||
+
|
||||
+#define MT7620_MIB_COUNTER_BASE_PORT 0x4000
|
||||
+#define MT7620_MIB_COUNTER_PORT_OFFSET 0x100
|
||||
+#define MT7620_MIB_COUNTER_BASE 0x1010
|
||||
+
|
||||
+/* PPE Accounting Group #0 Byte Counter */
|
||||
+#define MT7620_MIB_STATS_PPE_AC_BCNT0 0x000
|
||||
+
|
||||
+/* PPE Accounting Group #0 Packet Counter */
|
||||
+#define MT7620_MIB_STATS_PPE_AC_PCNT0 0x004
|
||||
+
|
||||
+/* PPE Accounting Group #63 Byte Counter */
|
||||
+#define MT7620_MIB_STATS_PPE_AC_BCNT63 0x1F8
|
||||
+
|
||||
+/* PPE Accounting Group #63 Packet Counter */
|
||||
+#define MT7620_MIB_STATS_PPE_AC_PCNT63 0x1FC
|
||||
+
|
||||
+/* PPE Meter Group #0 */
|
||||
+#define MT7620_MIB_STATS_PPE_MTR_CNT0 0x200
|
||||
+
|
||||
+/* PPE Meter Group #63 */
|
||||
+#define MT7620_MIB_STATS_PPE_MTR_CNT63 0x2FC
|
||||
+
|
||||
+/* Transmit good byte count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_TX_GBCNT 0x300
|
||||
+
|
||||
+/* Transmit good packet count for CPU GDM (exclude flow control frames) */
|
||||
+#define MT7620_MIB_STATS_GDM1_TX_GPCNT 0x304
|
||||
+
|
||||
+/* Transmit abort count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT 0x308
|
||||
+
|
||||
+/* Transmit collision count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_TX_COLCNT 0x30C
|
||||
+
|
||||
+/* Received good byte count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_GBCNT1 0x320
|
||||
+
|
||||
+/* Received good packet count for CPU GDM (exclude flow control frame) */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_GPCNT1 0x324
|
||||
+
|
||||
+/* Received overflow error packet count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_OERCNT 0x328
|
||||
+
|
||||
+/* Received FCS error packet count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_FERCNT 0x32C
|
||||
+
|
||||
+/* Received too short error packet count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_SERCNT 0x330
|
||||
+
|
||||
+/* Received too long error packet count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_LERCNT 0x334
|
||||
+
|
||||
+/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_CERCNT 0x338
|
||||
+
|
||||
+/* Received flow control pkt count for CPU GDM */
|
||||
+#define MT7620_MIB_STATS_GDM1_RX_FCCNT 0x33C
|
||||
+
|
||||
+/* Transmit good byte count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_TX_GBCNT 0x340
|
||||
+
|
||||
+/* Transmit good packet count for PPE GDM (exclude flow control frames) */
|
||||
+#define MT7620_MIB_STATS_GDM2_TX_GPCNT 0x344
|
||||
+
|
||||
+/* Transmit abort count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT 0x348
|
||||
+
|
||||
+/* Transmit collision count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_TX_COLCNT 0x34C
|
||||
+
|
||||
+/* Received good byte count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_GBCNT 0x360
|
||||
+
|
||||
+/* Received good packet count for PPE GDM (exclude flow control frame) */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_GPCNT 0x364
|
||||
+
|
||||
+/* Received overflow error packet count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_OERCNT 0x368
|
||||
+
|
||||
+/* Received FCS error packet count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_FERCNT 0x36C
|
||||
+
|
||||
+/* Received too short error packet count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_SERCNT 0x370
|
||||
+
|
||||
+/* Received too long error packet count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_LERCNT 0x374
|
||||
+
|
||||
+/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_CERCNT 0x378
|
||||
+
|
||||
+/* Received flow control pkt count for PPE GDM */
|
||||
+#define MT7620_MIB_STATS_GDM2_RX_FCCNT 0x37C
|
||||
+
|
||||
+/* Tx Packet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_TGPCN 0x10
|
||||
+
|
||||
+/* Tx Bad Octet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_TBOCN 0x14
|
||||
+
|
||||
+/* Tx Good Octet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_TGOCN 0x18
|
||||
+
|
||||
+/* Tx Event Packet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_TEPCN 0x1C
|
||||
+
|
||||
+/* Rx Packet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_RGPCN 0x20
|
||||
+
|
||||
+/* Rx Bad Octet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_RBOCN 0x24
|
||||
+
|
||||
+/* Rx Good Octet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_RGOCN 0x28
|
||||
+
|
||||
+/* Rx Event Packet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_REPC1N 0x2C
|
||||
+
|
||||
+/* Rx Event Packet Counter of Port n */
|
||||
+#define MT7620_MIB_STATS_PORT_REPC2N 0x30
|
||||
+
|
||||
+#define MT7621_MIB_COUNTER_BASE 0x4000
|
||||
+#define MT7621_MIB_COUNTER_PORT_OFFSET 0x100
|
||||
+#define MT7621_STATS_TDPC 0x00
|
||||
+#define MT7621_STATS_TCRC 0x04
|
||||
+#define MT7621_STATS_TUPC 0x08
|
||||
+#define MT7621_STATS_TMPC 0x0C
|
||||
+#define MT7621_STATS_TBPC 0x10
|
||||
+#define MT7621_STATS_TCEC 0x14
|
||||
+#define MT7621_STATS_TSCEC 0x18
|
||||
+#define MT7621_STATS_TMCEC 0x1C
|
||||
+#define MT7621_STATS_TDEC 0x20
|
||||
+#define MT7621_STATS_TLCEC 0x24
|
||||
+#define MT7621_STATS_TXCEC 0x28
|
||||
+#define MT7621_STATS_TPPC 0x2C
|
||||
+#define MT7621_STATS_TL64PC 0x30
|
||||
+#define MT7621_STATS_TL65PC 0x34
|
||||
+#define MT7621_STATS_TL128PC 0x38
|
||||
+#define MT7621_STATS_TL256PC 0x3C
|
||||
+#define MT7621_STATS_TL512PC 0x40
|
||||
+#define MT7621_STATS_TL1024PC 0x44
|
||||
+#define MT7621_STATS_TOC 0x48
|
||||
+#define MT7621_STATS_RDPC 0x60
|
||||
+#define MT7621_STATS_RFPC 0x64
|
||||
+#define MT7621_STATS_RUPC 0x68
|
||||
+#define MT7621_STATS_RMPC 0x6C
|
||||
+#define MT7621_STATS_RBPC 0x70
|
||||
+#define MT7621_STATS_RAEPC 0x74
|
||||
+#define MT7621_STATS_RCEPC 0x78
|
||||
+#define MT7621_STATS_RUSPC 0x7C
|
||||
+#define MT7621_STATS_RFEPC 0x80
|
||||
+#define MT7621_STATS_ROSPC 0x84
|
||||
+#define MT7621_STATS_RJEPC 0x88
|
||||
+#define MT7621_STATS_RPPC 0x8C
|
||||
+#define MT7621_STATS_RL64PC 0x90
|
||||
+#define MT7621_STATS_RL65PC 0x94
|
||||
+#define MT7621_STATS_RL128PC 0x98
|
||||
+#define MT7621_STATS_RL256PC 0x9C
|
||||
+#define MT7621_STATS_RL512PC 0xA0
|
||||
+#define MT7621_STATS_RL1024PC 0xA4
|
||||
+#define MT7621_STATS_ROC 0xA8
|
||||
+#define MT7621_STATS_RDPC_CTRL 0xB0
|
||||
+#define MT7621_STATS_RDPC_ING 0xB4
|
||||
+#define MT7621_STATS_RDPC_ARL 0xB8
|
||||
+
|
||||
+int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
|
||||
+
|
||||
+#endif
|
||||
|
@ -1,6 +1,6 @@
|
||||
--- a/drivers/net/ethernet/mediatek/mt7530.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mt7530.c
|
||||
@@ -539,6 +539,7 @@ mt7530_apply_config(struct switch_dev *d
|
||||
@@ -541,6 +541,7 @@ mt7530_apply_config(struct switch_dev *d
|
||||
u8 etags = priv->vlan_entries[i].etags;
|
||||
u32 val;
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
/* vid of vlan */
|
||||
val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
|
||||
if (i % 2 == 0) {
|
||||
@@ -549,7 +550,7 @@ mt7530_apply_config(struct switch_dev *d
|
||||
@@ -551,7 +552,7 @@ mt7530_apply_config(struct switch_dev *d
|
||||
val |= (vid << 12);
|
||||
}
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
|
||||
@ -17,7 +17,7 @@
|
||||
/* vlan port membership */
|
||||
if (member)
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
|
||||
@@ -569,7 +570,11 @@ mt7530_apply_config(struct switch_dev *d
|
||||
@@ -571,7 +572,11 @@ mt7530_apply_config(struct switch_dev *d
|
||||
mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
|
||||
|
||||
/* write to vlan table */
|
||||
|
Loading…
Reference in New Issue
Block a user