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mediatek: backport recent DTS improvements for MT7622 SoC
Daniel Golle: 190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch Rui Salvaterra: 191-arm64-dts-mt7622-specify-the-L2-cache-topology.patch 192-arm64-dts-mt7622-specify-the-number-of-DMA-requests.patch Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 26 Apr 2022 20:51:36 +0100
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From: Daniel Golle <daniel@makrotopia.org>
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To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
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linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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Cc: Rob Herring <robh+dt@kernel.org>,
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Matthias Brugger <matthias.bgg@gmail.com>
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Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
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Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
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With the current range specified for the CPU interface there is an
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error message at boot:
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GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
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Setting irqchip.gicv2_force_probe=1 in bootargs results in:
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GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
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GIC: Adjusting CPU interface base to 0x000000001032f000
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GIC: Using split EOI/Deactivate mode
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Using the adjusted CPU interface base and 8K size results in only the
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final line remaining and fully working system as well as /proc/interrupts
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showing additional IPI3,4,5,6:
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IPI3: 0 0 CPU stop (for crash dump) interrupts
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IPI4: 0 0 Timer broadcast interrupts
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IPI5: 0 0 IRQ work interrupts
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IPI6: 0 0 CPU wake-up interrupts
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -339,7 +339,7 @@
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10310000 0 0x1000>,
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- <0 0x10320000 0 0x1000>,
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+ <0 0x1032f000 0 0x2000>,
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<0 0x10340000 0 0x2000>,
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<0 0x10360000 0 0x2000>;
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};
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Subject: [PATCH] arm64: dts: mt7622: specify the L2 cache topology
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Date: Thu, 28 Apr 2022 23:57:55 +0100
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On an MT7622 system, the kernel complains of not being able to detect the cache
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hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in
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order to fix this.
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Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -80,6 +80,7 @@
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enable-method = "psci";
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clock-frequency = <1300000000>;
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cci-control-port = <&cci_control2>;
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+ next-level-cache = <&L2>;
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};
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cpu1: cpu@1 {
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@@ -94,6 +95,12 @@
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enable-method = "psci";
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clock-frequency = <1300000000>;
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cci-control-port = <&cci_control2>;
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+ next-level-cache = <&L2>;
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+ };
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+
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+ L2: l2-cache {
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+ compatible = "cache";
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+ cache-level = <2>;
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};
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};
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From patchwork Fri Apr 29 08:42:25 2022
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Fri, 29 Apr 2022 01:42:31 -0700 (PDT)
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From: Rui Salvaterra <rsalvaterra@gmail.com>
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To: linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
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Cc: matthias.bgg@gmail.com, ryder.lee@mediatek.com, daniel@makrotopia.org,
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Rui Salvaterra <rsalvaterra@gmail.com>
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Subject: [PATCH] arm64: dts: mt7622: specify the number of DMA requests
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Date: Fri, 29 Apr 2022 09:42:25 +0100
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The MT7622 device tree never bothered to specify the number of virtual DMA
|
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channels for the HSDMA controller, always falling back to the default value of
|
||||
3. Make this value explicit, in order to avoid the following dmesg notification:
|
||||
|
||||
mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property
|
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Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
|
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---
|
||||
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 +
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1 file changed, 1 insertion(+)
|
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -940,6 +940,7 @@
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||||
clock-names = "hsdma";
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
|
||||
#dma-cells = <1>;
|
||||
+ dma-requests = <3>;
|
||||
};
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pcie_mirror: pcie-mirror@10000400 {
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Reference in New Issue
Block a user