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fix bcm4710 cache fixes

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SVN-Revision: 5132
This commit is contained in:
Felix Fietkau 2006-10-15 21:55:14 +00:00
parent 233fbc4726
commit 57e4908e51
1 changed files with 9 additions and 9 deletions
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18
target/linux/brcm-2.6/patches/003-bcm4710_cache_fixes.patch
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@ -5,7 +5,7 @@ diff -Nur linux-2.6.17/arch/mips/kernel/genex.S linux-2.6.17-owrt/arch/mips/kern
.set push .set push
.set mips3 .set mips3
.set noat .set noat
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+ nop + nop
+ nop + nop
+#endif +#endif
@ -19,12 +19,12 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/bitops.h> #include <linux/bitops.h>
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+#include "../bcm947xx/include/typedefs.h" +#include "../bcm947xx/include/typedefs.h"
+#include "../bcm947xx/include/sbconfig.h" +#include "../bcm947xx/include/sbconfig.h"
+#include "../bcm947xx/include/mipsinc.h"
+#include <asm/paccess.h> +#include <asm/paccess.h>
+#endif +#endif
+
#include <asm/bcache.h> #include <asm/bcache.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/cache.h> #include <asm/cache.h>
@ -84,7 +84,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
static inline void coherency_setup(void) static inline void coherency_setup(void)
{ {
change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT); change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365) +#ifdef CONFIG_BCM947XX
+ if (BCM330X(current_cpu_data.processor_id)) { + if (BCM330X(current_cpu_data.processor_id)) {
+ __u32 cm = read_c0_diag(); + __u32 cm = read_c0_diag();
+ /* Enable icache */ + /* Enable icache */
@ -103,7 +103,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/c-r4k.c linux-2.6.17-owrt/arch/mips/mm/c-r4k
set_uncached_handler (0x100, &except_vec2_generic, 0x80); set_uncached_handler (0x100, &except_vec2_generic, 0x80);
+ +
+ /* Check if special workarounds are required */ + /* Check if special workarounds are required */
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) { + if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
+ printk("Enabling BCM4710A0 cache workarounds.\n"); + printk("Enabling BCM4710A0 cache workarounds.\n");
+ bcm4710 = 1; + bcm4710 = 1;
@ -120,7 +120,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex
/* #define DEBUG_TLB */ /* #define DEBUG_TLB */
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+extern int bcm4710; +extern int bcm4710;
+#endif +#endif
+ +
@ -131,7 +131,7 @@ diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex
memset(relocs, 0, sizeof(relocs)); memset(relocs, 0, sizeof(relocs));
memset(final_handler, 0, sizeof(final_handler)); memset(final_handler, 0, sizeof(final_handler));
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+ if (bcm4710) { + if (bcm4710) {
+ i_nop(&p); + i_nop(&p);
+ } + }
@ -147,7 +147,7 @@ diff -Nur linux-2.6.17/include/asm-mips/r4kcache.h linux-2.6.17-owrt/include/asm
#include <asm/cpu-features.h> #include <asm/cpu-features.h>
#include <asm/mipsmtregs.h> #include <asm/mipsmtregs.h>
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate) +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
+ +
+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr)) +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
@ -345,7 +345,7 @@ diff -Nur linux-2.6.17/include/asm-mips/stackframe.h linux-2.6.17-owrt/include/a
.macro RESTORE_SP_AND_RET .macro RESTORE_SP_AND_RET
LONG_L sp, PT_R29(sp) LONG_L sp, PT_R29(sp)
.set mips3 .set mips3
+#ifdef CONFIG_BCM4710 +#ifdef CONFIG_BCM947XX
+ nop + nop
+ nop + nop
+#endif +#endif