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ramips: mt7620: add rgmii delays support
At this moment mt7620 ethernet driver doesn't support rgmii delays configuration. SoC MT7620 have bits 2 and 3 in GPC1 an GPC2 to configure delays for rx and tx rgmii interface. This patch adds rx/tx rgmii delay configuration from dts. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
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@ -46,6 +46,10 @@
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#define GSW_REG_IMR 0x7008
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#define GSW_REG_IMR 0x7008
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#define GSW_REG_ISR 0x700c
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#define GSW_REG_ISR 0x700c
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#define GSW_REG_GPC1 0x7014
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#define GSW_REG_GPC1 0x7014
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#define GSW_REG_GPC2 0x701c
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#define GSW_REG_GPCx_TXDELAY BIT(3)
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#define GSW_REG_GPCx_RXDELAY BIT(2)
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#define GSW_REG_MAC_P0_MCR 0x100
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#define GSW_REG_MAC_P0_MCR 0x100
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#define GSW_REG_MAC_P1_MCR 0x200
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#define GSW_REG_MAC_P1_MCR 0x200
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@ -146,6 +146,8 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
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int phy_mode, size, id;
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int phy_mode, size, id;
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int shift = 12;
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int shift = 12;
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u32 val, mask = 0;
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u32 val, mask = 0;
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u32 val_delay = 0;
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u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
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int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
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int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
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if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
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if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
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@ -175,6 +177,25 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
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switch (phy_mode) {
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switch (phy_mode) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII:
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mask = 0;
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mask = 0;
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/* Do not touch rx/tx delay in this state to avoid problems with
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* backward compability.
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*/
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mask_delay = 0;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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mask = 0;
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val_delay |= GSW_REG_GPCx_TXDELAY;
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val_delay &= ~GSW_REG_GPCx_RXDELAY;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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mask = 0;
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val_delay &= ~GSW_REG_GPCx_TXDELAY;
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val_delay &= ~GSW_REG_GPCx_RXDELAY;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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mask = 0;
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val_delay &= ~GSW_REG_GPCx_TXDELAY;
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val_delay |= GSW_REG_GPCx_RXDELAY;
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break;
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break;
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_MII:
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mask = 1;
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mask = 1;
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@ -196,6 +217,19 @@ static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
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val |= mask << shift;
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val |= mask << shift;
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rt_sysc_w32(val, SYSC_REG_CFG1);
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rt_sysc_w32(val, SYSC_REG_CFG1);
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if (id == 4) {
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val = mtk_switch_r32(gsw, GSW_REG_GPC2);
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val &= ~(mask_delay);
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val |= val_delay & mask_delay;
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mtk_switch_w32(gsw, val, GSW_REG_GPC2);
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}
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else if (id == 5) {
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val = mtk_switch_r32(gsw, GSW_REG_GPC1);
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val &= ~(mask_delay);
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val |= val_delay & mask_delay;
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mtk_switch_w32(gsw, val, GSW_REG_GPC1);
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}
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if (priv->phy->phy_fixed[id]) {
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if (priv->phy->phy_fixed[id]) {
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const __be32 *link = priv->phy->phy_fixed[id];
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const __be32 *link = priv->phy->phy_fixed[id];
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int tx_fc, rx_fc;
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int tx_fc, rx_fc;
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