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lantiq: ltq-ptm: use platform_get_irq to get irqs

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This is required for linux-6.1 compatibility.

IRQs are not automatically mapped from HW to virtual IRQ numbers when
the IRQ domain is registered. This happens when the IRQ number is read
from the device tree based on the IRQ domain from the device tree now.
In kernel 5.15 it was done when the IRQ domain was registered.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
This commit is contained in:
Martin Schiller 2024-04-12 08:56:24 +02:00
parent 7bc487c12e
commit 52719d90c2
8 changed files with 24 additions and 34 deletions
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16
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.c
View File

@ -1491,8 +1491,14 @@ static int ltq_ptm_probe(struct platform_device *pdev)
goto REGISTER_NETDEV_FAIL;
}
g_ptm_priv_data.irq = platform_get_irq(pdev, 0);
if (g_ptm_priv_data.irq < 0) {
err("platform_get_irq fail");
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
/* register interrupt handler */
ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
err("IRQ may be occupied by other driver, please reconfig to disable it.");
@ -1502,7 +1508,7 @@ static int ltq_ptm_probe(struct platform_device *pdev)
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
disable_irq(PPE_MAILBOX_IGU1_INT);
disable_irq(g_ptm_priv_data.irq);
ret = ifx_pp32_start(0);
if ( ret ) {
@ -1512,7 +1518,7 @@ static int ltq_ptm_probe(struct platform_device *pdev)
IFX_REG_W32(0, MBOX_IGU1_IER);
IFX_REG_W32(~0, MBOX_IGU1_ISRC);
enable_irq(PPE_MAILBOX_IGU1_INT);
enable_irq(g_ptm_priv_data.irq);
proc_file_create();
@ -1534,7 +1540,7 @@ static int ltq_ptm_probe(struct platform_device *pdev)
return 0;
PP32_START_FAIL:
free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
i = ARRAY_SIZE(g_net_dev);
REGISTER_NETDEV_FAIL:
@ -1572,7 +1578,7 @@ static int ltq_ptm_remove(struct platform_device *pdev)
ifx_pp32_stop(0);
free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
unregister_netdev(g_net_dev[i]);

2
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_adsl.h
View File

@ -35,7 +35,6 @@
#include "ifxmips_ptm_fw_regs_adsl.h"
#define CONFIG_IFXMIPS_DSL_CPE_MEI
#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
@ -104,6 +103,7 @@ struct ptm_itf {
struct ptm_priv_data {
struct ptm_itf itf[MAX_ITF_NUMBER];
int irq;
void *rx_desc_base;
void *tx_desc_base;

5
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_amazon_se.h
View File

@ -176,11 +176,6 @@
#define EMA_ALIGNMENT 4
/*
* Mailbox IGU1 Interrupt
*/
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL13
#endif // IFXMIPS_PTM_PPE_AMAZON_SE_H

6
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h
View File

@ -203,11 +203,5 @@
#define SW_P2_CTL SW_REG(0x00C)
/*
* Mailbox IGU1 Interrupt
*/
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
#endif // IFXMIPS_PTM_PPE_AR9_H

5
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_danube.h
View File

@ -125,11 +125,6 @@
#define EMA_ALIGNMENT 4
/*
* Mailbox IGU1 Interrupt
*/
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
#endif // IFXMIPS_PTM_PPE_DANUBE_H

5
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_vr9.h
View File

@ -195,11 +195,6 @@
#define PDMA_ALIGNMENT 32 // same as Central DMA because of descriptor swap
#define EMA_ALIGNMENT PDMA_ALIGNMENT
/*
* Mailbox IGU1 Interrupt
*/
#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24
#endif // IFXMIPS_PTM_PPE_VR9_H

16
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.c
View File

@ -1013,8 +1013,14 @@ static int ltq_ptm_probe(struct platform_device *pdev)
goto REGISTER_NETDEV_FAIL;
}
g_ptm_priv_data.irq = platform_get_irq(pdev, 0);
if (g_ptm_priv_data.irq < 0) {
err("platform_get_irq fail");
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
/* register interrupt handler */
ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
ret = request_irq(g_ptm_priv_data.irq, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
if ( ret ) {
if ( ret == -EBUSY ) {
err("IRQ may be occupied by other driver, please reconfig to disable it.");
@ -1024,7 +1030,7 @@ static int ltq_ptm_probe(struct platform_device *pdev)
}
goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
}
disable_irq(PPE_MAILBOX_IGU1_INT);
disable_irq(g_ptm_priv_data.irq);
ret = ifx_pp32_start(0);
if ( ret ) {
@ -1034,7 +1040,7 @@ static int ltq_ptm_probe(struct platform_device *pdev)
IFX_REG_W32(1 << 16, MBOX_IGU1_IER); // enable SWAP interrupt
IFX_REG_W32(~0, MBOX_IGU1_ISRC);
enable_irq(PPE_MAILBOX_IGU1_INT);
enable_irq(g_ptm_priv_data.irq);
ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
if ( g_showtime ) {
@ -1052,7 +1058,7 @@ static int ltq_ptm_probe(struct platform_device *pdev)
return 0;
PP32_START_FAIL:
free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
i = ARRAY_SIZE(g_net_dev);
REGISTER_NETDEV_FAIL:
@ -1080,7 +1086,7 @@ static int ltq_ptm_remove(struct platform_device *pdev)
ifx_pp32_stop(0);
free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
free_irq(g_ptm_priv_data.irq, &g_ptm_priv_data);
for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
unregister_netdev(g_net_dev[i]);

3
package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vdsl.h
View File

@ -31,8 +31,6 @@
#include "ifxmips_ptm_ppe_common.h"
#include "ifxmips_ptm_fw_regs_vdsl.h"
#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24)
#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r))
#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r))
#define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r))
@ -99,6 +97,7 @@ struct ptm_itf {
struct ptm_priv_data {
struct ptm_itf itf[MAX_ITF_NUMBER];
int irq;
};