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bcm63xx: fix USB base registers and IRQs for BCM6328
SVN-Revision: 33005
This commit is contained in:
Jonas Gorski
parent
a0fb060211
commit
4feeda756e
@ -0,0 +1,26 @@
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From 960e1ef3c5b2d69a4a5a6984b6408d65221dd86c Mon Sep 17 00:00:00 2001
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From: Kevin Cernekee <cernekee@gmail.com>
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Date: Sat, 23 Jun 2012 04:14:55 +0000
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Subject: [PATCH 06/81] MIPS: BCM63XX: Fix USB IRQ definitions for 6328
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OHCI/EHCI are in the high (second) word. Not currently used by any
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driver.
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -602,8 +602,8 @@ enum bcm63xx_irq {
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#define BCM_6328_ENET0_IRQ 0
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#define BCM_6328_ENET1_IRQ 0
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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-#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
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-#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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+#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
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+#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
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#define BCM_6328_PCMCIA_IRQ 0
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#define BCM_6328_ENET0_RXDMA_IRQ 0
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#define BCM_6328_ENET0_TXDMA_IRQ 0
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@ -0,0 +1,62 @@
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From 21bb8141c205ae48d331787debb6b272add90ac7 Mon Sep 17 00:00:00 2001
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From: Kevin Cernekee <cernekee@gmail.com>
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Date: Sat, 23 Jun 2012 04:14:54 +0000
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Subject: [PATCH 05/81] MIPS: BCM63XX: Add register definitions for USBD
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dependencies
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The USB 2.0 device depends on some functionality in other blocks, such
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as GPIO and USBH. Add those register definitions here.
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Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 6 +++---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 8 ++++++++
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2 files changed, 11 insertions(+), 3 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -184,9 +184,9 @@ enum bcm63xx_regs_set {
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#define BCM_6328_SPI_BASE (0xdeadbeef)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xdeadbeef)
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-#define BCM_6328_OHCI0_BASE (0xdeadbeef)
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+#define BCM_6328_OHCI0_BASE (0xb0002600)
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#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
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-#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
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+#define BCM_6328_USBH_PRIV_BASE (0xb0002700)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6328_PCIE_BASE (0xb0e40000)
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@@ -199,7 +199,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_ENETDMAC_BASE (0xb000da00)
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#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
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#define BCM_6328_ENETSW_BASE (0xb0e00000)
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-#define BCM_6328_EHCI0_BASE (0x10002500)
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+#define BCM_6328_EHCI0_BASE (0xb0002500)
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#define BCM_6328_SDRAM_BASE (0xdeadbeef)
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#define BCM_6328_MEMC_BASE (0xdeadbeef)
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#define BCM_6328_DDR_BASE (0xb0003000)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -543,6 +543,12 @@
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#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
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+#define GPIO_PINMUX_OTHR_REG 0x24
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+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
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+#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
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+#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
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+#define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
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+
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#define GPIO_BASEMODE_6368_REG 0x38
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#define GPIO_BASEMODE_6368_UART2 0x1
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#define GPIO_BASEMODE_6368_GPIO 0x0
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@@ -770,6 +776,8 @@
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#define USBH_PRIV_SWAP_6358_REG 0x0
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#define USBH_PRIV_SWAP_6368_REG 0x1c
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+#define USBH_PRIV_SWAP_USBD_SHIFT 6
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+#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
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#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
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#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
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#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
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@ -34,7 +34,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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+#define BCM_6328_HSSPI_BASE (0xb0001000)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xdeadbeef)
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#define BCM_6328_OHCI0_BASE (0xdeadbeef)
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#define BCM_6328_OHCI0_BASE (0xb0002600)
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@@ -227,6 +230,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_UART1_BASE (0xdeadbeef)
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#define BCM_6338_GPIO_BASE (0xfffe0400)
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@ -104,8 +104,8 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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#define BCM_6328_ENET1_IRQ 0
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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+#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
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#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
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#define BCM_6328_PCMCIA_IRQ 0
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@@ -640,6 +652,7 @@ enum bcm63xx_irq {
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#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
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@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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[IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1231,4 +1231,51 @@
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@@ -1239,4 +1239,51 @@
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#define PCIE_DEVICE_OFFSET 0x8000
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@ -472,7 +472,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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#define SOFTRESET_6368_SPI_MASK (1 << 0)
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#define SOFTRESET_6368_MPI_MASK (1 << 3)
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#define SOFTRESET_6368_EPHY_MASK (1 << 6)
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@@ -1174,6 +1227,12 @@
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@@ -1182,6 +1235,12 @@
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#define SERDES_PCIE_EN (1 << 0)
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#define SERDES_PCIE_EXD_EN (1 << 15)
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@ -11,7 +11,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1223,7 +1223,8 @@
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@@ -1231,7 +1231,8 @@
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/*************************************************************************
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* _REG relative to RSET_MISC
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*************************************************************************/
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@ -205,7 +205,7 @@ Subject: [PATCH 31/63] bcm63xx_enet: add support for bcm6368 internal ethernet s
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#endif /* ! BCM63XX_DEV_ENET_H_ */
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -803,10 +803,60 @@
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@@ -809,10 +809,60 @@
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* _REG relative to RSET_ENETSW
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*************************************************************************/
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@ -10,7 +10,7 @@ Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -832,6 +832,19 @@
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@@ -838,6 +838,19 @@
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#define ENETSW_PORTOV_FDX_MASK (1 << 1)
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#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
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@ -84,7 +84,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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return -ENODEV;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -608,6 +608,7 @@
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@@ -614,6 +614,7 @@
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#define GPIO_STRAPBUS_REG 0x40
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#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
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#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
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@ -92,7 +92,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
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#define STRAPBUS_6368_BOOT_SEL_NAND 0
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#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
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@@ -1300,6 +1301,7 @@
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@@ -1308,6 +1309,7 @@
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#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
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#define MISC_STRAPBUS_6328_REG 0x240
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@ -40,7 +40,7 @@ Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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return spi_register_board_info(bcm63xx_spi_flash_info,
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1296,6 +1296,7 @@
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@@ -1304,6 +1304,7 @@
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#define MISC_STRAPBUS_6362_REG 0x14
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#define STRAPBUS_6362_FCVO_SHIFT 1
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@ -76,7 +76,7 @@ Subject: [PATCH 58/84] MIPS: BCM63XX: enable SPI controller for BCM6362
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#endif
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1215,6 +1215,22 @@
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@@ -1223,6 +1223,22 @@
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#define SPI_6358_MSG_TAIL 0x709
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#define SPI_6358_RX_TAIL 0x70B
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