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mac80211: rework MT7620 PA/LNA RF calibration
This patch makes some improvements to the MT7620 RF calibration.
1. Move MT7620 PA/LNA calibration code to dedicated functions.
2. Restore RF and BBP registers before R-Calibration.
3. Do Rx DCOC calibration again before RXIQ calibration.
4. Use SoC specific AGC initial LNA value.
5. Correct MAC_RX_EN mask in rt2800_r_calibration()[1].
[1] This change may fix the "BBP/RF register access failed" error:
ieee80211 phy0: rt2800_wait_bbp_rf_ready: Error - BBP/RF register access failed, aborting
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
(cherry picked from commit 2824fa6963)
This commit is contained in:
Shiji Yang
Daniel Golle
parent
b2d264dc68
commit
4f1a7e8897
@ -0,0 +1,434 @@
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From: Shiji Yang <yangshiji66@outlook.com>
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Date: Tue, 25 Jul 2023 20:05:06 +0800
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Subject: [PATCH] wifi: rt2x00: rework MT7620 PA/LNA RF calibration
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1. Move MT7620 PA/LNA calibration code to dedicated functions.
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Calibration stage 1 is executed before configuring channels and
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stage 2 is executed after configuring channels.
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2. For external PA/LNA devices, restore RF and BBP registers before
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R-Calibration.
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3. Do Rx DCOC calibration again before RXIQ calibration.
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4. Correct MAC_SYS_CTRL register RX mask to 0x08 in R-Calibration
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function. For MAC_SYS_CTRL register, Bit[2] controls MAC_TX_EN
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and Bit[3] controls MAC_RX_EN (Bit index starts from 0).
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5. Move the channel configuration code from rt2800_vco_calibration()
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to the rt2800_config_channel().
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6. Use MT7620 SOC specific AGC initial LNA value instead of the
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RT5592's value.
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7. Adjust the register operation sequence according to the vendor
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driver code. This may not be useful, but it can make things
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clearer when developers try to review it.
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Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
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---
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.../net/wireless/ralink/rt2x00/rt2800lib.c | 318 +++++++++++-------
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drivers/net/wireless/ralink/rt2x00/rt2x00.h | 6 +
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2 files changed, 194 insertions(+), 130 deletions(-)
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--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
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@@ -62,6 +62,9 @@ MODULE_PARM_DESC(watchdog, "Enable watch
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rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
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H2M_MAILBOX_CSR_OWNER, (__reg))
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+static void rt6352_init_palna_stage1(struct rt2x00_dev *rt2x00dev);
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+static void rt6352_init_palna_stage2(struct rt2x00_dev *rt2x00dev);
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+
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static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
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{
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/* check for rt2872 on SoC */
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@@ -3881,14 +3884,6 @@ static void rt2800_config_channel_rf7620
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rfcsr |= tx_agc_fc;
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rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
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}
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-
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- if (conf_is_ht40(conf)) {
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- rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
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- rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
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- } else {
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- rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
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- rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
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- }
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}
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static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
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@@ -4151,6 +4146,9 @@ static void rt2800_config_channel(struct
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rt2800_txpower_to_dev(rt2x00dev, rf->channel,
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info->default_power3);
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+ if (rt2x00_rt(rt2x00dev, RT6352))
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+ rt6352_init_palna_stage1(rt2x00dev);
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+
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switch (rt2x00dev->chip.rt) {
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case RT3883:
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rt3883_bbp_adjust(rt2x00dev, rf);
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@@ -4457,89 +4455,65 @@ static void rt2800_config_channel(struct
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usleep_range(1000, 1500);
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}
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- if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
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+ if (rt2x00_rt(rt2x00dev, RT5592)) {
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reg = 0x10;
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- if (!conf_is_ht40(conf)) {
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- if (rt2x00_rt(rt2x00dev, RT6352) &&
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- rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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- reg |= 0x5;
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- } else {
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- reg |= 0xa;
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- }
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- }
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+ if (!conf_is_ht40(conf))
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+ reg |= 0xa;
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rt2800_bbp_write(rt2x00dev, 195, 141);
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rt2800_bbp_write(rt2x00dev, 196, reg);
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- /* AGC init.
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- * Despite the vendor driver using different values here for
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- * RT6352 chip, we use 0x1c for now. This may have to be changed
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- * once TSSI got implemented.
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- */
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reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
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rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
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-
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- if (rt2x00_rt(rt2x00dev, RT5592))
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- rt2800_iq_calibrate(rt2x00dev, rf->channel);
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+
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+ rt2800_iq_calibrate(rt2x00dev, rf->channel);
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}
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if (rt2x00_rt(rt2x00dev, RT6352)) {
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- if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
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- &rt2x00dev->cap_flags)) {
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- reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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- reg |= 0x00000101;
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- rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
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-
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- reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
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- reg |= 0x00000101;
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- rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
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-
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
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- rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
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+ /* BBP for GLRT BW */
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+ if (conf_is_ht40(conf)) {
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+ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
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+ rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
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+ } else {
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+ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
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+ rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
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- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
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- 0x36303636);
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- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
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- 0x6C6C6B6C);
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- rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
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- 0x6C6C6B6C);
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
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+ rt2x00_has_cap_external_lna_bg(rt2x00dev))
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+ rt2800_bbp_glrt_write(rt2x00dev, 141, 0x15);
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}
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- if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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- reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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- reg |= 0x00000101;
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- rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
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-
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- reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
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- reg |= 0x00000101;
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- rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
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-
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
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- rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
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- rt2800_bbp_write(rt2x00dev, 75, 0x68);
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- rt2800_bbp_write(rt2x00dev, 76, 0x4C);
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- rt2800_bbp_write(rt2x00dev, 79, 0x1C);
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- rt2800_bbp_write(rt2x00dev, 80, 0x0C);
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- rt2800_bbp_write(rt2x00dev, 82, 0xB6);
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- /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in
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- * config channel function in dependence of channel and
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- * HT20/HT40 so don't touch it
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- */
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+ if (rt2x00dev->default_ant.rx_chain_num == 1) {
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+ rt2800_bbp_write(rt2x00dev, 91, 0x07);
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+ rt2800_bbp_write(rt2x00dev, 95, 0x1A);
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+ rt2800_bbp_write(rt2x00dev, 195, 128);
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+ rt2800_bbp_write(rt2x00dev, 196, 0xA0);
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+ rt2800_bbp_write(rt2x00dev, 195, 170);
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+ rt2800_bbp_write(rt2x00dev, 196, 0x12);
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+ rt2800_bbp_write(rt2x00dev, 195, 171);
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+ rt2800_bbp_write(rt2x00dev, 196, 0x10);
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+ } else {
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+ rt2800_bbp_write(rt2x00dev, 91, 0x06);
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+ rt2800_bbp_write(rt2x00dev, 95, 0x9A);
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+ rt2800_bbp_write(rt2x00dev, 195, 128);
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+ rt2800_bbp_write(rt2x00dev, 196, 0xE0);
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+ rt2800_bbp_write(rt2x00dev, 195, 170);
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+ rt2800_bbp_write(rt2x00dev, 196, 0x30);
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+ rt2800_bbp_write(rt2x00dev, 195, 171);
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+ rt2800_bbp_write(rt2x00dev, 196, 0x30);
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}
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+
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+ /* AGC init */
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+ reg = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
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+ rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
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+
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+ /* On 11A, We should delay and wait RF/BBP to be stable
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+ * and the appropriate time should be 1000 micro seconds
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+ * 2005/06/05 - On 11G, we also need this delay time.
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+ * Otherwise it's difficult to pass the WHQL.
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+ */
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+ usleep_range(1000, 1500);
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+
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+ rt6352_init_palna_stage2(rt2x00dev);
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}
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bbp = rt2800_bbp_read(rt2x00dev, 4);
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@@ -5649,43 +5623,6 @@ void rt2800_vco_calibration(struct rt2x0
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}
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}
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rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
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-
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- if (rt2x00_rt(rt2x00dev, RT6352)) {
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- if (rt2x00dev->default_ant.rx_chain_num == 1) {
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- rt2800_bbp_write(rt2x00dev, 91, 0x07);
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- rt2800_bbp_write(rt2x00dev, 95, 0x1A);
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- rt2800_bbp_write(rt2x00dev, 195, 128);
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- rt2800_bbp_write(rt2x00dev, 196, 0xA0);
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- rt2800_bbp_write(rt2x00dev, 195, 170);
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- rt2800_bbp_write(rt2x00dev, 196, 0x12);
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- rt2800_bbp_write(rt2x00dev, 195, 171);
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- rt2800_bbp_write(rt2x00dev, 196, 0x10);
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- } else {
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- rt2800_bbp_write(rt2x00dev, 91, 0x06);
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- rt2800_bbp_write(rt2x00dev, 95, 0x9A);
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- rt2800_bbp_write(rt2x00dev, 195, 128);
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- rt2800_bbp_write(rt2x00dev, 196, 0xE0);
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- rt2800_bbp_write(rt2x00dev, 195, 170);
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- rt2800_bbp_write(rt2x00dev, 196, 0x30);
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- rt2800_bbp_write(rt2x00dev, 195, 171);
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- rt2800_bbp_write(rt2x00dev, 196, 0x30);
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- }
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-
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- if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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- rt2800_bbp_write(rt2x00dev, 75, 0x68);
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- rt2800_bbp_write(rt2x00dev, 76, 0x4C);
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- rt2800_bbp_write(rt2x00dev, 79, 0x1C);
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- rt2800_bbp_write(rt2x00dev, 80, 0x0C);
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- rt2800_bbp_write(rt2x00dev, 82, 0xB6);
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- }
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-
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- /* On 11A, We should delay and wait RF/BBP to be stable
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- * and the appropriate time should be 1000 micro seconds
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- * 2005/06/05 - On 11G, we also need this delay time.
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- * Otherwise it's difficult to pass the WHQL.
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- */
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- usleep_range(1000, 1500);
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- }
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}
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EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
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@@ -8650,7 +8587,7 @@ static void rt2800_r_calibration(struct
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rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
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maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
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- maccfg &= (~0x04);
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+ maccfg &= (~0x08);
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rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
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if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
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@@ -10688,30 +10625,151 @@ static void rt2800_init_rfcsr_6352(struc
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rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
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rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
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}
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+}
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- rt6352_enable_pa_pin(rt2x00dev, 0);
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- rt2800_r_calibration(rt2x00dev);
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- rt2800_rf_self_txdc_cal(rt2x00dev);
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- rt2800_rxdcoc_calibration(rt2x00dev);
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- rt2800_bw_filter_calibration(rt2x00dev, true);
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- rt2800_bw_filter_calibration(rt2x00dev, false);
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- rt2800_loft_iq_calibration(rt2x00dev);
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- rt2800_rxiq_calibration(rt2x00dev);
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- rt6352_enable_pa_pin(rt2x00dev, 1);
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+static void rt6352_init_ext_palna(struct rt2x00_dev *rt2x00dev)
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+{
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+ u32 reg;
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+
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+ if (rt2x00_has_cap_external_pa(rt2x00dev)) {
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+ reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
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+ reg |= 0x00000101;
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+ rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
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+
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+ reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
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+ reg |= 0x00000101;
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+ rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
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+ }
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- if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
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+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
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rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
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+ }
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+
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
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+ rt2x00_has_cap_external_pa(rt2x00dev)) {
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
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+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
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+ }
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+
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
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+ rt2x00_has_cap_external_pa(rt2x00dev)) {
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+ rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
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+ }
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+
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+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
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+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
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rt2800_bbp_write(rt2x00dev, 75, 0x68);
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rt2800_bbp_write(rt2x00dev, 76, 0x4C);
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rt2800_bbp_write(rt2x00dev, 79, 0x1C);
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rt2800_bbp_write(rt2x00dev, 80, 0x0C);
|
||||
rt2800_bbp_write(rt2x00dev, 82, 0xB6);
|
||||
- /* bank 0 RF reg 42 and glrt BBP reg 141 will be set in config
|
||||
- * channel function in dependence of channel and HT20/HT40,
|
||||
- * so don't touch them here.
|
||||
- */
|
||||
+ }
|
||||
+
|
||||
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
|
||||
+ rt2x00_has_cap_external_pa(rt2x00dev)) {
|
||||
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
|
||||
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C6B6C);
|
||||
+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C6B6C);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void rt6352_restore_rf_bbp(struct rt2x00_dev *rt2x00dev)
|
||||
+{
|
||||
+ if (rt2x00_has_cap_external_pa(rt2x00dev)) {
|
||||
+ rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
|
||||
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
|
||||
+ }
|
||||
+
|
||||
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
|
||||
+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
|
||||
+ }
|
||||
+
|
||||
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
|
||||
+ rt2x00_has_cap_external_pa(rt2x00dev))
|
||||
+ {
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
|
||||
+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
|
||||
+ }
|
||||
+
|
||||
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1 &&
|
||||
+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
|
||||
+ rt2800_bbp_write(rt2x00dev, 75, 0x60);
|
||||
+ rt2800_bbp_write(rt2x00dev, 76, 0x44);
|
||||
+ rt2800_bbp_write(rt2x00dev, 79, 0x1C);
|
||||
+ rt2800_bbp_write(rt2x00dev, 80, 0x0C);
|
||||
+ rt2800_bbp_write(rt2x00dev, 82, 0xB6);
|
||||
+ }
|
||||
+
|
||||
+ if (rt2800_hw_get_chippkg(rt2x00dev) == 1
|
||||
+ && rt2x00_has_cap_external_pa(rt2x00dev)) {
|
||||
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363A);
|
||||
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
|
||||
+ rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/* MT7620 PA/LNA initialization before switching channels */
|
||||
+static void rt6352_init_palna_stage1(struct rt2x00_dev *rt2x00dev)
|
||||
+{
|
||||
+ if (rt2x00_has_cap_external_pa(rt2x00dev) ||
|
||||
+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
|
||||
+ rt6352_enable_pa_pin(rt2x00dev, 0);
|
||||
+ rt6352_restore_rf_bbp(rt2x00dev);
|
||||
+ }
|
||||
+
|
||||
+ rt2800_r_calibration(rt2x00dev);
|
||||
+}
|
||||
+
|
||||
+/* MT7620 PA/LNA initialization after switching channels */
|
||||
+static void rt6352_init_palna_stage2(struct rt2x00_dev *rt2x00dev)
|
||||
+{
|
||||
+ rt2800_rf_self_txdc_cal(rt2x00dev);
|
||||
+ rt2800_rxdcoc_calibration(rt2x00dev);
|
||||
+ rt2800_bw_filter_calibration(rt2x00dev, true);
|
||||
+ rt2800_bw_filter_calibration(rt2x00dev, false);
|
||||
+ rt2800_loft_iq_calibration(rt2x00dev);
|
||||
+
|
||||
+ /* missing DPD Calibration for devices using internal PA */
|
||||
+
|
||||
+ rt2800_rxdcoc_calibration(rt2x00dev);
|
||||
+ rt2800_rxiq_calibration(rt2x00dev);
|
||||
+
|
||||
+ if(rt2x00_has_cap_external_pa(rt2x00dev) ||
|
||||
+ rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
|
||||
+ rt6352_enable_pa_pin(rt2x00dev, 1);
|
||||
+ rt6352_init_ext_palna(rt2x00dev);
|
||||
}
|
||||
}
|
||||
|
||||
--- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
|
||||
+++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
|
||||
@@ -1277,6 +1277,12 @@ rt2x00_has_cap_external_lna_bg(struct rt
|
||||
}
|
||||
|
||||
static inline bool
|
||||
+rt2x00_has_cap_external_pa(struct rt2x00_dev *rt2x00dev)
|
||||
+{
|
||||
+ return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_EXTERNAL_PA_TX0);
|
||||
+}
|
||||
+
|
||||
+static inline bool
|
||||
rt2x00_has_cap_double_antenna(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
return rt2x00_has_cap_flag(rt2x00dev, CAPABILITY_DOUBLE_ANTENNA);
|
||||
Loading…
Reference in New Issue
Block a user