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realtek: add support for HPE 1920-8g-poe+
Hardware information: --------------------- - RTL8380 SoC - 8 Gigabit RJ45 PoE ports (built-in RTL8218B) - 2 SFP ports (built-in SerDes) - RJ45 RS232 port on front panel - 32 MiB NOR Flash - 128 MiB DDR3 DRAM - PT7A7514 watchdog - PoE chips: Nuvoton M0516LDE + BCM59121 Known issues: --------------------- - PoE LEDs are uncontrolled. (Manual taken fromf2f09bc002) Booting initramfs image: ------------------------ - Prepare a FTP or TFTP server serving the OpenWrt initramfs image and connect the server to a switch port. - Connect to the console port of the device and enter the extended boot menu by typing Ctrl+B when prompted. - Choose the menu option "<3> Enter Ethernet SubMenu". - Set network parameters via the option "<5> Modify Ethernet Parameter". Enter the FTP/TFTP filename as "Load File Name" ("Target File Name" can be left blank, it is not required for booting from RAM). Note that the configuration is saved on flash, so it only needs to be done once. - Select "<1> Download Application Program To SDRAM And Run". Initial installation: --------------------- - Boot an initramfs image as described above, then use sysupgrade to install OpenWrt permanently. After initial installation, the bootloader needs to be configured to load the correct image file - Enter the extended boot menu again and choose "<4> File Control", then select "<2> Set Application File type". - Enter the number of the file "openwrt-kernel.bin" (should be 1), and use the option "<1> +Main" to select it as boot image. - Choose "<0> Exit To Main Menu" and then "<1> Boot System". NOTE: The bootloader on these devices can only boot from the VFS filesystem which normally spans most of the flash. With OpenWrt, only the first part of the firmware partition contains a valid filesystem, the rest is used for rootfs. As the bootloader does not know about this, you must not do any file operations in the bootloader, as this may corrupt the OpenWrt installation (selecting the boot image is an exception, as it only stores a flag in the bootloader data, but doesn't write to the filesystem). Example PoE config file (/etc/config/poe): --------------------- config global option budget '180' config port option enable '1' option id '1' option name 'lan8' option poe_plus '1' option priority '2' config port option enable '1' option id '2' option name 'lan7' option poe_plus '1' option priority '2' config port option enable '1' option id '3' option name 'lan6' option poe_plus '1' option priority '2' config port option enable '1' option id '4' option name 'lan5' option poe_plus '1' option priority '2' config port option enable '1' option id '5' option name 'lan4' option poe_plus '1' option priority '2' config port option enable '1' option id '6' option name 'lan3' option poe_plus '1' option priority '2' config port option enable '1' option id '7' option name 'lan2' option poe_plus '1' option priority '2' config port option enable '1' option id '8' option name 'lan1' option poe_plus '1' option priority '2' Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> (cherry picked from commitb370753fc4)
This commit is contained in:
Pawel Dembicki
Hauke Mehrtens
parent
ad2fa6bc9c
commit
4ebba8a05d
@ -21,6 +21,7 @@ board=$(board_name)
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board_config_update
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lan_list=$(ls -1 -v -d /sys/class/net/lan* | xargs -n1 basename | xargs)
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lan_list_rev=$(ls -1 -v -d -r /sys/class/net/lan* | xargs -n1 basename | xargs)
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ucidef_set_bridge_device switch
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ucidef_set_interface_lan "$lan_list"
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@ -30,6 +31,7 @@ lan_mac_end=""
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label_mac=""
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case $board in
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hpe,1920-8g|\
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hpe,1920-8g-poe|\
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hpe,1920-16g|\
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hpe,1920-24g)
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label_mac=$(mtd_get_mac_binary factory 0x68)
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@ -65,6 +67,9 @@ done
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[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
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case $board in
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hpe,1920-8g-poe)
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ucidef_set_poe 180 "$lan_list_rev" "lan9 lan10"
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;;
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netgear,gs110tpp-v1)
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ucidef_set_poe 130 "$lan_list" "lan9 lan10"
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;;
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16
target/linux/realtek/base-files/etc/board.d/03_gpio_switches
Normal file
16
target/linux/realtek/base-files/etc/board.d/03_gpio_switches
Normal file
@ -0,0 +1,16 @@
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. /lib/functions/uci-defaults.sh
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board_config_update
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board=$(board_name)
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case "$board" in
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hpe,1920-8g-poe)
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ucidef_add_gpio_switch "fan_ctrl" "Fan control" "456" "0"
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;;
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esac
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board_config_flush
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exit 0
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12
target/linux/realtek/dts-5.15/rtl8380_hpe_1920-8g-poe.dts
Normal file
12
target/linux/realtek/dts-5.15/rtl8380_hpe_1920-8g-poe.dts
Normal file
@ -0,0 +1,12 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl8380_hpe_1920-8g.dtsi"
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/ {
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compatible = "hpe,1920-8g-poe", "realtek,rtl838x-soc";
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model = "HPE 1920-8G-PoE+ (JG922A)";
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};
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&uart1 {
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status = "okay";
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};
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@ -1,115 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl838x_hpe_1920.dtsi"
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#include "rtl8380_hpe_1920-8g.dtsi"
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/ {
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compatible = "hpe,1920-8g", "realtek,rtl838x-soc";
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model = "HPE 1920-8G (JG920A)";
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gpio1: rtl8231-gpio {
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compatible = "realtek,rtl8231-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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indirect-access-bus-id = <0>;
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};
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-0 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>;
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// tx-fault and tx-disable unconnected
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};
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
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// tx-fault and tx-disable unconnected
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(24)
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INTERNAL_PHY(26)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@24 {
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reg = <24>;
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label = "lan9";
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phy-handle = <&phy24>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan10";
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phy-handle = <&phy26>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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112
target/linux/realtek/dts-5.15/rtl8380_hpe_1920-8g.dtsi
Normal file
112
target/linux/realtek/dts-5.15/rtl8380_hpe_1920-8g.dtsi
Normal file
@ -0,0 +1,112 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl838x_hpe_1920.dtsi"
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/ {
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gpio1: rtl8231-gpio {
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compatible = "realtek,rtl8231-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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indirect-access-bus-id = <0>;
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};
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-0 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 25 GPIO_ACTIVE_LOW>;
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// tx-fault and tx-disable unconnected
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};
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
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// tx-fault and tx-disable unconnected
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(24)
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INTERNAL_PHY(26)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@24 {
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reg = <24>;
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label = "lan9";
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phy-handle = <&phy24>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan10";
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phy-handle = <&phy26>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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@ -99,6 +99,14 @@ define Device/hpe_1920-8g
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endef
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TARGET_DEVICES += hpe_1920-8g
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define Device/hpe_1920-8g-poe
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$(Device/hpe_1920)
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SOC := rtl8380
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DEVICE_MODEL := 1920-8G-PoE+ (JG922A)
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H3C_DEVICE_ID := 0x00010025
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endef
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TARGET_DEVICES += hpe_1920-8g-poe
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define Device/hpe_1920-16g
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$(Device/hpe_1920)
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SOC := rtl8382
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