diff --git a/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch b/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch new file mode 100644 index 00000000000..374093734fb --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-01-board-mediatek-mt7622-remove-board_late_init.patch @@ -0,0 +1,26 @@ +From 92090b92fab207250d5b8d5a4a36aa34f5a91f19 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:16:33 +0800 +Subject: [PATCH 01/15] board: mediatek: mt7622: remove board_late_init + +The function board_late_init defined for mt7622 is useless now. Just +remove it. + +Signed-off-by: Weijie Gao +--- + board/mediatek/mt7622/mt7622_rfb.c | 7 ------- + 1 file changed, 7 deletions(-) + +--- a/board/mediatek/mt7622/mt7622_rfb.c ++++ b/board/mediatek/mt7622/mt7622_rfb.c +@@ -15,10 +15,3 @@ int board_init(void) + { + return 0; + } +- +-int board_late_init(void) +-{ +- gd->env_valid = 1; //to load environment variable from persistent store +- env_relocate(); +- return 0; +-} diff --git a/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch b/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch new file mode 100644 index 00000000000..4e16fe78d4e --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-02-clk-mediatek-fix-uninitialized-fields-issue-in-INFRA.patch @@ -0,0 +1,48 @@ +From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:16:38 +0800 +Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in + INFRA_MUX struct + +This patch adds missing initialization of fields in INFRA_MUX struct +which caused uart broken after any other infra mux being enabled by +'clk_prepare_enable' + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/clk/mediatek/clk-mt7981.c | 1 + + drivers/clk/mediatek/clk-mt7986.c | 1 + + drivers/clk/mediatek/clk-mt7988.c | 1 + + 3 files changed, 3 insertions(+) + +--- a/drivers/clk/mediatek/clk-mt7981.c ++++ b/drivers/clk/mediatek/clk-mt7981.c +@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci + .id = _id, .mux_reg = (_reg) + 0x8, \ + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ ++ .gate_shift = -1, .upd_shift = -1, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } +--- a/drivers/clk/mediatek/clk-mt7986.c ++++ b/drivers/clk/mediatek/clk-mt7986.c +@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci + .id = _id, .mux_reg = (_reg) + 0x8, \ + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \ + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \ ++ .gate_shift = -1, .upd_shift = -1, \ + .parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \ + } +--- a/drivers/clk/mediatek/clk-mt7988.c ++++ b/drivers/clk/mediatek/clk-mt7988.c +@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_ + .id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \ + .mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, .parent = _parents, \ ++ .gate_shift = -1, .upd_shift = -1, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \ + } diff --git a/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch b/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch new file mode 100644 index 00000000000..b17986ead5d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-03-configs-mt7629-move-image-load-address-to-0x42000000.patch @@ -0,0 +1,25 @@ +From 7958b41b8c6a15c3c993affd2091f8c921b6a8a1 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:17:38 +0800 +Subject: [PATCH 03/15] configs: mt7629: move image load address to 0x42000000 + +Update the image load address to ensure it matches the mt7629 NOR +controller's DMA alignment requirements. + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + configs/mt7629_rfb_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/configs/mt7629_rfb_defconfig ++++ b/configs/mt7629_rfb_defconfig +@@ -18,7 +18,7 @@ CONFIG_SPL_STACK=0x106000 + CONFIG_SPL_TEXT_BASE=0x201000 + CONFIG_SPL_STACK_R=y + CONFIG_SYS_BOOTM_LEN=0x4000000 +-CONFIG_SYS_LOAD_ADDR=0x42007f1c ++CONFIG_SYS_LOAD_ADDR=0x42000000 + CONFIG_SPL_PAYLOAD="u-boot-lzma.img" + CONFIG_BUILD_TARGET="u-boot-mtk.bin" + CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" diff --git a/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch b/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch new file mode 100644 index 00000000000..e03c9b0305a --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-04-configs-mt7988-move-image-load-address-to-0x44000000.patch @@ -0,0 +1,24 @@ +From c7a3761ddfce2bd56ad319a254d5269cb26fa18f Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:17:44 +0800 +Subject: [PATCH 04/15] configs: mt7988: move image load address to 0x44000000 + +This patch sets mt7988 image load address to 0x44000000 to support loading +larger images. + +Signed-off-by: Weijie Gao +--- + configs/mt7988_rfb_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/configs/mt7988_rfb_defconfig ++++ b/configs/mt7988_rfb_defconfig +@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_DEFAULT_DEVICE_TREE="mt7988-rfb" + CONFIG_TARGET_MT7988=y +-CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SYS_LOAD_ADDR=0x44000000 + CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_DEBUG_UART=y diff --git a/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch b/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch new file mode 100644 index 00000000000..4b90136687c --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-05-spi-mtk_spim-add-support-to-use-DT-live-tree.patch @@ -0,0 +1,23 @@ +From a2c2ac46ca4c4ef5fe043e584cf867a20e93226d Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:17:51 +0800 +Subject: [PATCH 05/15] spi: mtk_spim: add support to use DT live tree + +Change devfdt_get_addr_ptr to dev_read_addr_ptr to support DT live tree. + +Signed-off-by: Weijie Gao +--- + drivers/spi/mtk_spim.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/mtk_spim.c ++++ b/drivers/spi/mtk_spim.c +@@ -648,7 +648,7 @@ static int mtk_spim_probe(struct udevice + struct mtk_spim_priv *priv = dev_get_priv(dev); + int ret; + +- priv->base = devfdt_get_addr_ptr(dev); ++ priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + diff --git a/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch b/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch new file mode 100644 index 00000000000..c30105bb5fa --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-06-spi-mtk_spim-check-slave-device-mode-in-spi-mem-s-su.patch @@ -0,0 +1,27 @@ +From 7725d4ba16577b74567f7cffb2faffa8bdc5ad61 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:17:55 +0800 +Subject: [PATCH 06/15] spi: mtk_spim: check slave device mode in spi-mem's + supports_op + +Call spi_mem_default_supports_op() in supports_op to honor the +slave's supported single/dual/quad mode settings. + +Signed-off-by: SkyLake.Huang +Signed-off-by: Weijie Gao +--- + drivers/spi/mtk_spim.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/spi/mtk_spim.c ++++ b/drivers/spi/mtk_spim.c +@@ -359,6 +359,9 @@ static bool mtk_spim_supports_op(struct + struct udevice *bus = dev_get_parent(slave->dev); + struct mtk_spim_priv *priv = dev_get_priv(bus); + ++ if (!spi_mem_default_supports_op(slave, op)) ++ return false; ++ + if (op->cmd.buswidth == 0 || op->cmd.buswidth > 4 || + op->addr.buswidth > 4 || op->dummy.buswidth > 4 || + op->data.buswidth > 4) diff --git a/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch b/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch new file mode 100644 index 00000000000..bfcbd644aa7 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-07-arm-dts-mediatek-add-quad-mode-capabilities-for-SPI-.patch @@ -0,0 +1,96 @@ +From c7a602028669f4409538c3ce0a63c4054d0f2b7a Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:01 +0800 +Subject: [PATCH 07/15] arm: dts: mediatek: add quad mode capabilities for SPI + flashes + +Explicitly add quad mode capabilities or the SPI controller may +start transfer in single mode. + +Signed-off-by: SkyLake.Huang +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7981-rfb.dts | 4 ++++ + arch/arm/dts/mt7986a-rfb.dts | 4 ++++ + arch/arm/dts/mt7986b-rfb.dts | 4 ++++ + arch/arm/dts/mt7988-rfb.dts | 4 ++++ + 4 files changed, 16 insertions(+) + +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -143,6 +143,8 @@ + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +@@ -164,6 +166,8 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +--- a/arch/arm/dts/mt7986a-rfb.dts ++++ b/arch/arm/dts/mt7986a-rfb.dts +@@ -190,12 +190,16 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +--- a/arch/arm/dts/mt7986b-rfb.dts ++++ b/arch/arm/dts/mt7986b-rfb.dts +@@ -177,12 +177,16 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + + spi_nand@1 { + compatible = "spi-nand"; + reg = <1>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -144,6 +144,8 @@ + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + +@@ -165,6 +167,8 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ spi-rx-bus-width = <4>; ++ spi-tx-bus-width = <4>; + }; + }; + diff --git a/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch b/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch new file mode 100644 index 00000000000..a11742a213e --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-08-pwm-mediatek-add-pwm3-support-for-mt7981.patch @@ -0,0 +1,98 @@ +From 7071ba2658ef6175183cc5dc85819293811490b3 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:06 +0800 +Subject: [PATCH 08/15] pwm: mediatek: add pwm3 support for mt7981 + +This patch adds pwm channel 2 (pwm3) support for mt7981 + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7981-emmc-rfb.dts | 8 ++++++++ + arch/arm/dts/mt7981-rfb.dts | 8 ++++++++ + arch/arm/dts/mt7981-sd-rfb.dts | 8 ++++++++ + arch/arm/dts/mt7981.dtsi | 10 ++++++++-- + drivers/pwm/pwm-mtk.c | 2 +- + 5 files changed, 33 insertions(+), 3 deletions(-) + +--- a/arch/arm/dts/mt7981-emmc-rfb.dts ++++ b/arch/arm/dts/mt7981-emmc-rfb.dts +@@ -95,6 +95,14 @@ + }; + }; + ++ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins_1: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0", "pwm1_1", "pwm2"; ++ }; ++ }; ++ + mmc0_pins_default: mmc0default { + mux { + function = "flash"; +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -123,6 +123,14 @@ + groups = "pwm0_1", "pwm1_0", "pwm2"; + }; + }; ++ ++ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins_1: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0", "pwm1_1", "pwm2"; ++ }; ++ }; + }; + + &spi0 { +--- a/arch/arm/dts/mt7981-sd-rfb.dts ++++ b/arch/arm/dts/mt7981-sd-rfb.dts +@@ -95,6 +95,14 @@ + }; + }; + ++ /* pin13 as pwm0, pin15 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins_1: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_0", "pwm1_1", "pwm2"; ++ }; ++ }; ++ + mmc0_pins_default: mmc0default { + mux { + function = "flash"; +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -137,8 +137,14 @@ + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; +- assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>; ++ assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>, ++ <&infracfg CLK_INFRA_PWM1_SEL>, ++ <&infracfg CLK_INFRA_PWM2_SEL>, ++ <&infracfg CLK_INFRA_PWM3_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, ++ <&topckgen CLK_TOP_PWM_SEL>, ++ <&topckgen CLK_TOP_PWM_SEL>, ++ <&topckgen CLK_TOP_PWM_SEL>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + status = "disabled"; + }; +--- a/drivers/pwm/pwm-mtk.c ++++ b/drivers/pwm/pwm-mtk.c +@@ -192,7 +192,7 @@ static const struct mtk_pwm_soc mt7629_d + }; + + static const struct mtk_pwm_soc mt7981_data = { +- .num_pwms = 2, ++ .num_pwms = 3, + .pwm45_fixup = false, + .reg_ver = PWM_REG_V2, + }; diff --git a/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch b/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch new file mode 100644 index 00000000000..cc23dda9756 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-09-pci-mediatek-add-support-for-multiple-ports-in-media.patch @@ -0,0 +1,61 @@ +From dfbadb86b3bc43c004671ab6eb46ee160a192e98 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:11 +0800 +Subject: [PATCH 09/15] pci: mediatek: add support for multiple ports in + mediatek pcie gen3 driver + +One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 +on this port represents the controller itself and bus 1 represents +the external PCIe device. + +If multiple PCIe controllers are probed in U-Boot, U-Boot will use +bus numbers greater than 2 as input parameters. Therefore, we should +convert the BDF bus number to either 0 or 1 by subtracting the +offset by controller->seq_. + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/pci/pcie_mediatek_gen3.c | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +--- a/drivers/pci/pcie_mediatek_gen3.c ++++ b/drivers/pci/pcie_mediatek_gen3.c +@@ -83,6 +83,28 @@ struct mtk_pcie { + struct phy phy; + }; + ++static pci_dev_t convert_bdf(const struct udevice *controller, pci_dev_t bdf) ++{ ++ int bdfs[3]; ++ ++ bdfs[0] = PCI_BUS(bdf); ++ bdfs[1] = PCI_DEV(bdf); ++ bdfs[2] = PCI_FUNC(bdf); ++ ++ /* ++ * One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0 on ++ * this port represents the controller itself and bus 1 represents the ++ * external PCIe device. If multiple PCIe controllers are probed in U-Boot, ++ * U-Boot will use bus numbers greater than 2 as input parameters. Therefore, ++ * we should convert the BDF bus number to either 0 or 1 by subtracting the ++ * offset by controller->seq_ ++ */ ++ ++ bdfs[0] = bdfs[0] - controller->seq_; ++ ++ return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); ++} ++ + static void mtk_pcie_config_tlp_header(const struct udevice *bus, + pci_dev_t devfn, + int where, int size) +@@ -91,6 +113,8 @@ static void mtk_pcie_config_tlp_header(c + int bytes; + u32 val; + ++ devfn = convert_bdf(bus, devfn); ++ + size = 1 << size; + bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); + diff --git a/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch b/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch new file mode 100644 index 00000000000..0b72a0d232f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-10-arm-dts-mediatek-add-pcie-support-for-mt7988.patch @@ -0,0 +1,219 @@ +From 4064eb22e221ce93fef7f1ec3b13ac670c6b20e2 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:17 +0800 +Subject: [PATCH 10/15] arm: dts: mediatek: add pcie support for mt7988 + +This patch adds PCIe support for mt7988 + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7988-rfb.dts | 18 ++++ + arch/arm/dts/mt7988.dtsi | 162 ++++++++++++++++++++++++++++++++++++ + 2 files changed, 180 insertions(+) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -63,6 +63,24 @@ + }; + }; + ++&pcie0 { ++ status = "okay"; ++}; ++ ++&pcie1 { ++ status = "okay"; ++}; ++ ++/* PCIE2 not working in u-boot */ ++&pcie2 { ++ status = "disabled"; ++}; ++ ++/* PCIE3 not working in u-boot */ ++&pcie3 { ++ status = "disabled"; ++}; ++ + &pinctrl { + i2c1_pins: i2c1-pins { + mux { +--- a/arch/arm/dts/mt7988.dtsi ++++ b/arch/arm/dts/mt7988.dtsi +@@ -188,6 +188,152 @@ + status = "okay"; + }; + ++ pcie2: pcie@11280000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11280000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <3>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ phys = <&xphyu3port0 PHY_TYPE_PCIE>; ++ phy-names = "pcie-phy"; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc2 0>, ++ <0 0 0 2 &pcie_intc2 1>, ++ <0 0 0 3 &pcie_intc2 2>, ++ <0 0 0 4 &pcie_intc2 3>; ++ ++ pcie_intc2: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie3: pcie@11290000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11290000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <2>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ use-dedicated-phy; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc3 0>, ++ <0 0 0 2 &pcie_intc3 1>, ++ <0 0 0 3 &pcie_intc3 2>, ++ <0 0 0 4 &pcie_intc3 3>; ++ pcie_intc3: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie0: pcie@11300000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11300000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <0>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ use-dedicated-phy; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc0 0>, ++ <0 0 0 2 &pcie_intc0 1>, ++ <0 0 0 3 &pcie_intc0 2>, ++ <0 0 0 4 &pcie_intc0 3>; ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie1: pcie@11310000 { ++ compatible = "mediatek,mt7988-pcie", ++ "mediatek,mt7986-pcie", ++ "mediatek,mt8192-pcie"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ reg = <0 0x11310000 0 0x2000>; ++ reg-names = "pcie-mac"; ++ linux,pci-domain = <1>; ++ interrupts = ; ++ bus-range = <0x00 0xff>; ++ ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>; ++ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, ++ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, ++ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, ++ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; ++ clock-names = "pl_250m", "tl_26m", "peri_26m", ++ "top_133m"; ++ use-dedicated-phy; ++ ++ status = "disabled"; ++ ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 0x7>; ++ interrupt-map = <0 0 0 1 &pcie_intc1 0>, ++ <0 0 0 2 &pcie_intc1 1>, ++ <0 0 0 3 &pcie_intc1 2>, ++ <0 0 0 4 &pcie_intc1 3>; ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ + usbtphy: usb-phy@11c50000 { + compatible = "mediatek,mt7988", + "mediatek,generic-tphy-v2"; +@@ -214,6 +360,22 @@ + status = "okay"; + }; + }; ++ ++ xphy: xphy@11e10000 { ++ compatible = "mediatek,mt7988", "mediatek,xsphy"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ status = "disabled"; ++ ++ xphyu3port0: usb-phy@11e13000 { ++ reg = <0 0x11e13400 0 0x500>; ++ clocks = <&dummy_clk>; ++ clock-names = "ref"; ++ #phy-cells = <1>; ++ status = "okay"; ++ }; ++ }; + + xfi_pextp0: syscon@11f20000 { + compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; diff --git a/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch b/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch new file mode 100644 index 00000000000..73caeca7ca0 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-11-arm-dts-medaitek-fix-internal-switch-link-speed-of-m.patch @@ -0,0 +1,36 @@ +From 4a85182570200bf5e87e2a9920e9d28e968bc6e0 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:22 +0800 +Subject: [PATCH 11/15] arm: dts: medaitek: fix internal switch link speed of + mt7988 + +The CPU port of mt7988 internal switch uses 10Gb link speed. + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7988-rfb.dts | 2 +- + arch/arm/dts/mt7988-sd-rfb.dts | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -57,7 +57,7 @@ + mediatek,switch = "mt7988"; + + fixed-link { +- speed = <1000>; ++ speed = <10000>; + full-duplex; + pause; + }; +--- a/arch/arm/dts/mt7988-sd-rfb.dts ++++ b/arch/arm/dts/mt7988-sd-rfb.dts +@@ -48,7 +48,7 @@ + mediatek,switch = "mt7988"; + + fixed-link { +- speed = <1000>; ++ speed = <10000>; + full-duplex; + pause; + }; diff --git a/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch b/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch new file mode 100644 index 00000000000..f1c9aaa76fd --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-12-arm-dts-mediatek-add-support-for-all-three-GMACs-for.patch @@ -0,0 +1,103 @@ +From 64cf3dd0ef520a81a27359d83d58b64939e2aa06 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:27 +0800 +Subject: [PATCH 12/15] arm: dts: mediatek: add support for all three GMACs for + mt7988 + +This patch add all three GMACs nodes for mt7988. Each GMAC can be +configured to connect to different ethernet switches/PHYs. + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7988-rfb.dts | 3 +-- + arch/arm/dts/mt7988-sd-rfb.dts | 3 +-- + arch/arm/dts/mt7988.dtsi | 42 ++++++++++++++++++++++++++++++++-- + 3 files changed, 42 insertions(+), 6 deletions(-) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -50,9 +50,8 @@ + status = "okay"; + }; + +-ð { ++ð0 { + status = "okay"; +- mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; + mediatek,switch = "mt7988"; + +--- a/arch/arm/dts/mt7988-sd-rfb.dts ++++ b/arch/arm/dts/mt7988-sd-rfb.dts +@@ -41,9 +41,8 @@ + status = "okay"; + }; + +-ð { ++ð0 { + status = "okay"; +- mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; + mediatek,switch = "mt7988"; + +--- a/arch/arm/dts/mt7988.dtsi ++++ b/arch/arm/dts/mt7988.dtsi +@@ -587,11 +587,11 @@ + #reset-cells = <1>; + }; + +- eth: ethernet@15100000 { ++ eth0: ethernet@15110100 { + compatible = "mediatek,mt7988-eth", "syscon"; + reg = <0 0x15100000 0 0x20000>; ++ mediatek,gmac-id = <0>; + mediatek,ethsys = <ðdma>; +- mediatek,sgmiisys = <&sgmiisys0>; + mediatek,usxgmiisys = <&usxgmiisys0>; + mediatek,xfi_pextp = <&xfi_pextp0>; + mediatek,xfi_pll = <&xfi_pll>; +@@ -602,6 +602,44 @@ + #address-cells = <1>; + #size-cells = <0>; + mediatek,mcm; ++ status = "disabled"; ++ }; ++ ++ eth1: ethernet@15110200 { ++ compatible = "mediatek,mt7988-eth", "syscon"; ++ reg = <0 0x15100000 0 0x20000>; ++ mediatek,gmac-id = <1>; ++ mediatek,ethsys = <ðdma>; ++ mediatek,sgmiisys = <&sgmiisys1>; ++ mediatek,usxgmiisys = <&usxgmiisys1>; ++ mediatek,xfi_pextp = <&xfi_pextp1>; ++ mediatek,xfi_pll = <&xfi_pll>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,toprgu = <&watchdog>; ++ resets = <ðdma ETHDMA_FE_RST>; ++ reset-names = "fe"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,mcm; ++ status = "disabled"; ++ }; ++ ++ eth2: ethernet@15110300 { ++ compatible = "mediatek,mt7988-eth", "syscon"; ++ reg = <0 0x15100000 0 0x20000>; ++ mediatek,gmac-id = <2>; ++ mediatek,ethsys = <ðdma>; ++ mediatek,sgmiisys = <&sgmiisys0>; ++ mediatek,usxgmiisys = <&usxgmiisys0>; ++ mediatek,xfi_pextp = <&xfi_pextp0>; ++ mediatek,xfi_pll = <&xfi_pll>; ++ mediatek,infracfg = <&topmisc>; ++ mediatek,toprgu = <&watchdog>; ++ resets = <ðdma ETHDMA_FE_RST>; ++ reset-names = "fe"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mediatek,mcm; + status = "disabled"; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch b/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch new file mode 100644 index 00000000000..ec948ef2079 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-13-arm-dts-medaitek-add-flash-interface-driving-setting.patch @@ -0,0 +1,81 @@ +From 1090c6df3767da2c56d5827ba65ce91af8745420 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:41 +0800 +Subject: [PATCH 13/15] arm: dts: medaitek: add flash interface driving + settings for mt7988 + +Add driving settings for both SPI and SD/eMMC interfaces to support ensure +flash devices is accessible for ram-booting. + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7988-rfb.dts | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +--- a/arch/arm/dts/mt7988-rfb.dts ++++ b/arch/arm/dts/mt7988-rfb.dts +@@ -101,6 +101,19 @@ + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; ++ ++ conf-pu { ++ pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; ++ + }; + + spi2_pins: spi2-pins { +@@ -108,6 +121,18 @@ + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; ++ ++ conf-pu { ++ pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = ; ++ bias-pull-up = ; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = ; ++ bias-pull-down = ; ++ }; + }; + + mmc0_pins_default: mmc0default { +@@ -121,18 +146,25 @@ + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; ++ drive-strength = ; ++ mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + + conf-clk { + pins = "EMMC_CK"; ++ drive-strength = ; ++ mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + + conf-dsl { + pins = "EMMC_DSL"; ++ mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + + conf-rst { + pins = "EMMC_RSTB"; ++ drive-strength = ; ++ mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch b/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch new file mode 100644 index 00000000000..a6b47d7cc8d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-14-arm-dts-mediatek-update-mt7981-mmc-node.patch @@ -0,0 +1,62 @@ +From 140303d0308738dfb04059333c9fc25b5159a776 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:55 +0800 +Subject: [PATCH 14/15] arm: dts: mediatek: update mt7981 mmc node + +1. Fix mmc clock order of mt7981 to match the clock name +2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0 +3. Increase the CLK pin driving strength to 8mA + +Signed-off-by: Weijie Gao +--- + arch/arm/dts/mt7981-sd-rfb.dts | 6 ++++-- + arch/arm/dts/mt7981.dtsi | 12 ++++++------ + 2 files changed, 10 insertions(+), 8 deletions(-) + +--- a/arch/arm/dts/mt7981-sd-rfb.dts ++++ b/arch/arm/dts/mt7981-sd-rfb.dts +@@ -118,7 +118,7 @@ + }; + conf-clk { + pins = "SPI1_CS"; +- drive-strength = ; ++ drive-strength = ; + bias-pull-down = ; + }; + conf-rst { +@@ -140,10 +140,12 @@ + }; + + &mmc0 { ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>, ++ <&topckgen CLK_TOP_CB_NET2_D2>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; + bus-width = <4>; +- max-frequency = <52000000>; ++ max-frequency = <50000000>; + cap-sd-highspeed; + r_smpl = <0>; + vmmc-supply = <®_3p3v>; +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -306,13 +306,13 @@ + reg = <0x11230000 0x1000>, + <0x11C20000 0x1000>; + interrupts = ; +- clocks = <&topckgen CLK_TOP_EMMC_400M>, +- <&topckgen CLK_TOP_EMMC_208M>, ++ clocks = <&topckgen CLK_TOP_EMMC_208M>, ++ <&topckgen CLK_TOP_EMMC_400M>, + <&infracfg CLK_INFRA_MSDC_CK>; +- assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>, +- <&topckgen CLK_TOP_EMMC_208M_SEL>; +- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>, +- <&topckgen CLK_TOP_CB_M_D2>; ++ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, ++ <&topckgen CLK_TOP_EMMC_400M_SEL>; ++ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, ++ <&topckgen CLK_TOP_CB_NET2_D2>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; diff --git a/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch b/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch new file mode 100644 index 00000000000..81fcac7819e --- /dev/null +++ b/package/boot/uboot-mediatek/patches/070-15-MAINTAINERS-update-file-list-for-MediaTek-ARM-platfo.patch @@ -0,0 +1,36 @@ +From 8707ea0360046522d0784135b6c9a7c564f9515c Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 17 Jan 2025 17:18:59 +0800 +Subject: [PATCH 15/15] MAINTAINERS: update file list for MediaTek ARM platform + +Add driver files for MediaTek ARM platform + +Signed-off-by: Weijie Gao +--- + MAINTAINERS | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -412,9 +412,13 @@ F: drivers/mmc/mtk-sd.c + F: drivers/phy/phy-mtk-* + F: drivers/pinctrl/mediatek/ + F: drivers/power/domain/mtk-power-domain.c ++F: drivers/pci/pcie_mediatek_gen3.c ++F: drivers/pci/pcie_mediatek.c ++F: drivers/pwm/pwm-mtk.c + F: drivers/ram/mediatek/ + F: drivers/spi/mtk_snfi_spi.c + F: drivers/spi/mtk_spim.c ++F: drivers/spi/mtk_snor.c + F: drivers/timer/mtk_timer.c + F: drivers/usb/host/xhci-mtk.c + F: drivers/usb/mtu3/ +@@ -422,6 +426,7 @@ F: drivers/watchdog/mtk_wdt.c + F: drivers/net/mtk_eth.c + F: drivers/net/mtk_eth.h + F: drivers/reset/reset-mediatek.c ++F: drivers/serial/serial_mtk.c + F: include/dt-bindings/clock/mediatek,* + F: include/dt-bindings/power/mediatek,* + F: tools/mtk_image.c diff --git a/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch b/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch new file mode 100644 index 00000000000..e6d0ec35fa7 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/071-01-pinctrl-mediatek-update-mt7981-pinctrl-driver-based-.patch @@ -0,0 +1,138 @@ +From 24e660265f11dad63687c5529cf732538946a197 Mon Sep 17 00:00:00 2001 +From: Weijie Gao +Date: Fri, 24 Jan 2025 11:39:02 +0800 +Subject: [PATCH] pinctrl: mediatek: update mt7981 pinctrl driver based on + upstream kernel + +Update mt7981 pinctrl driver based on upstream kernel + +Signed-off-by: Sam Shih +Signed-off-by: Weijie Gao +--- + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 51 ++++++++++++++++++++--- + 1 file changed, 45 insertions(+), 6 deletions(-) + +--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c ++++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c +@@ -569,6 +569,11 @@ static const struct mtk_pin_desc mt7981_ + MT7981_TYPE1_PIN(56, "WF_HB10"), + }; + ++/* List all groups consisting of these pins dedicated to the enablement of ++ * certain hardware block and the corresponding mode for all of the pins. ++ * The hardware probably has multiple combinations of these pinouts. ++ */ ++ + /* WA_AICE */ + static const int mt7981_wa_aice1_pins[] = { 0, 1, }; + static const int mt7981_wa_aice1_funcs[] = { 2, 2, }; +@@ -632,6 +637,9 @@ static const int mt7981_wo0_jtag_1_funcs + static const int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; + static const int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; + ++static const int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; ++static const int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; ++ + /* GBE_LED0 */ + static const int mt7981_gbe_led0_pins[] = { 8, }; + static const int mt7981_gbe_led0_funcs[] = { 3, }; +@@ -718,6 +726,17 @@ static const int mt7981_drv_vbus_pins[] + static const int mt7981_drv_vbus_funcs[] = { 1, }; + + /* EMMC */ ++static const int mt7981_emmc_reset_pins[] = { 15, }; ++static const int mt7981_emmc_reset_funcs[] = { 2, }; ++ ++static const int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; ++static const int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; ++ ++static const int mt7981_emmc_8_pins[] = { ++ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; ++static const int mt7981_emmc_8_funcs[] = { ++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; ++ + static const int mt7981_emmc_45_pins[] = { + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; + static const int mt7981_emmc_45_funcs[] = { +@@ -754,6 +773,12 @@ static const int mt7981_uart1_0_funcs[] + static const int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; + static const int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; + ++static const int mt7981_uart1_2_pins[] = { 9, 10, }; ++static const int mt7981_uart1_2_funcs[] = { 2, 2, }; ++ ++static const int mt7981_uart1_3_pins[] = { 26, 27, }; ++static const int mt7981_uart1_3_funcs[] = { 2, 2, }; ++ + /* UART2 */ + static const int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; + static const int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; +@@ -832,6 +857,8 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), + /* @GPIO(4,7) WM_JTAG(3) */ + PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), ++ /* @GPIO(4,5) WM_JTAG(4) */ ++ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), + /* @GPIO(8) GBE_LED0(3) */ + PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), + /* @GPIO(4,6) PTA_EXT(4) */ +@@ -844,7 +871,7 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), + /* @GPIO(6,7) I2C(5) */ + PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), +- /* @GPIO(8): DFD_NTRST(6) */ ++ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ + PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), + /* @GPIO(9,10): WM_AICE(2) */ + PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), +@@ -870,6 +897,12 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("udi", mt7981_udi), + /* @GPIO(14) DRV_VBUS(1) */ + PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), ++ /* @GPIO(15): EMMC_RSTB(2) */ ++ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), ++ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ ++ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), ++ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ ++ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), + /* @GPIO(15,25): EMMC(2) */ + PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), + /* @GPIO(16,21): SNFI(3) */ +@@ -888,8 +921,12 @@ static const struct mtk_group_desc mt798 + PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), + /* @GPIO(26,29): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), ++ /* @GPIO(9,10): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), ++ /* @GPIO(26,27): UART1(2) */ ++ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), + /* @GPIO(22,25): UART2(3) */ +- PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_1), ++ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), + /* @GPIO(22,24) PTA_EXT(4) */ + PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), + /* @GPIO(20,21): WM_UART(4) */ +@@ -964,9 +1001,10 @@ static const struct mtk_io_type_desc mt7 + */ + static const char *const mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", + "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; +-static const char *const mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", +- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", +- "uart1_0", "uart1_1", "uart2_0", "wm_aurt_1", "wm_aurt_2", "uart0", }; ++static const char *const mt7981_uart_groups[] = { "net_wo0_uart_txd_0", ++ "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", "uart0", "uart1_0", ++ "uart1_1", "uart1_2", "uart1_3", "uart2_0", "uart2_0_tx_rx", "uart2_1", ++ "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; + static const char *const mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; + static const char *const mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; + static const char *const mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", +@@ -986,7 +1024,8 @@ static const char *const mt7981_i2c_grou + static const char *const mt7981_pcm_groups[] = { "pcm", }; + static const char *const mt7981_udi_groups[] = { "udi", }; + static const char *const mt7981_usb_groups[] = { "drv_vbus", }; +-static const char *const mt7981_flash_groups[] = { "emmc_45", "snfi", }; ++static const char *const mt7981_flash_groups[] = { "emmc_reset", "emmc_4", ++ "emmc_8", "emmc_45", "snfi", }; + static const char *const mt7981_ethernet_groups[] = { "smi_mdc_mdio", + "gbe_ext_mdc_mdio", "wf0_mode1", "wf0_mode3", "mt7531_int", }; + static const char *const mt7981_ant_groups[] = { "ant_sel", }; diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch index aea82d898e0..cdb83005d98 100644 --- a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch +++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch @@ -12,7 +12,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support --- a/board/mediatek/mt7622/mt7622_rfb.c +++ b/board/mediatek/mt7622/mt7622_rfb.c -@@ -9,6 +9,11 @@ +@@ -9,9 +9,47 @@ #include #include @@ -24,8 +24,7 @@ Subject: [PATCH] board: mediatek: wire-up NMBM support DECLARE_GLOBAL_DATA_PTR; int board_init(void) -@@ -22,3 +27,36 @@ int board_late_init(void) - env_relocate(); + { return 0; } + diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch index c6abfcaa9b0..b9357ea6f90 100644 --- a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch +++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch @@ -259,10 +259,10 @@ CONFIG_HEXDUMP=y --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts -@@ -144,6 +144,23 @@ - compatible = "spi-nand"; - reg = <0>; +@@ -195,6 +195,23 @@ spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; diff --git a/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch b/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch index a58c81b6568..eb68af9ee88 100644 --- a/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch +++ b/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch @@ -1,9 +1,9 @@ --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts -@@ -143,6 +143,37 @@ - compatible = "spi-nand"; - reg = <0>; +@@ -153,6 +153,37 @@ spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; @@ -38,10 +38,10 @@ }; }; -@@ -164,6 +195,37 @@ - compatible = "jedec,spi-nor"; - reg = <0>; +@@ -176,6 +207,37 @@ spi-max-frequency = <52000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; diff --git a/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch b/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch index b6dde70d6d2..6ed50907e32 100644 --- a/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch +++ b/package/boot/uboot-mediatek/patches/290-mt7981-add-USB-nodes.patch @@ -18,7 +18,7 @@ Signed-off-by: John Crispin #include #include #include -@@ -340,4 +341,50 @@ +@@ -346,4 +347,50 @@ status = "disabled"; }; diff --git a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index 57a119bd398..66dd43da4bc 100644 --- a/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -17,11 +17,12 @@ #include #include -@@ -23,7 +30,22 @@ int board_init(void) +@@ -21,6 +28,28 @@ int board_init(void) + return 0; + } - int board_late_init(void) - { -- gd->env_valid = 1; //to load environment variable from persistent store ++int board_late_init(void) ++{ + struct udevice *dev; + + if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { @@ -38,9 +39,13 @@ + } + } + - env_relocate(); - return 0; - } ++ env_relocate(); ++ return 0; ++ } ++ + int board_nmbm_init(void) + { + #ifdef CONFIG_ENABLE_NAND_NMBM --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -155,4 +155,11 @@ config MTK_BROM_HEADER_INFO diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch index 93fffc1d439..377b90c8e43 100644 --- a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch +++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch @@ -697,7 +697,7 @@ + status = "okay"; +}; + -+ð { ++ð0 { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "usxgmii"; diff --git a/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch b/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch index 5c11d81108f..e2ebf8994e3 100644 --- a/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch +++ b/package/boot/uboot-mediatek/patches/456-add-arcadyan-mozart.patch @@ -247,7 +247,7 @@ + status = "okay"; +}; + -+ð { ++ð0 { + status = "okay"; + mediatek,gmac-id = <0>; + phy-mode = "usxgmii";