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kernel: add WED rx support for mediatek
This is required for rx flow offloading on mt76 with MT7986 and MT7915 Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
parent
e410833bdd
commit
4e1a6ee903
@ -0,0 +1,591 @@
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From: Sujuan Chen <sujuan.chen@mediatek.com>
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Date: Sat, 5 Nov 2022 23:36:18 +0100
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Subject: [PATCH] net: ethernet: mtk_wed: introduce wed mcu support
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Introduce WED mcu support used to configure WED WO chip.
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This is a preliminary patch in order to add RX Wireless
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Ethernet Dispatch available on MT7986 SoC.
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_mcu.c
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create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.h
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--- a/drivers/net/ethernet/mediatek/Makefile
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+++ b/drivers/net/ethernet/mediatek/Makefile
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@@ -5,7 +5,7 @@
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
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mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
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-mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
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+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
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ifdef CONFIG_DEBUG_FS
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mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
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endif
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
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@@ -0,0 +1,359 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+/* Copyright (C) 2022 MediaTek Inc.
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+ *
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+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
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+ * Sujuan Chen <sujuan.chen@mediatek.com>
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+ */
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+
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+#include <linux/firmware.h>
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+#include <linux/of_address.h>
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+#include <linux/of_reserved_mem.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/soc/mediatek/mtk_wed.h>
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+
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+#include "mtk_wed_regs.h"
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+#include "mtk_wed_wo.h"
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+#include "mtk_wed.h"
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+
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+static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
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+{
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+ return readl(wo->boot.addr + reg);
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+}
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+
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+static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
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+{
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+ writel(val, wo->boot.addr + reg);
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+}
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+
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+static struct sk_buff *
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+mtk_wed_mcu_msg_alloc(const void *data, int data_len)
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+{
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+ int length = sizeof(struct mtk_wed_mcu_hdr) + data_len;
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+ struct sk_buff *skb;
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+
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+ skb = alloc_skb(length, GFP_KERNEL);
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+ if (!skb)
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+ return NULL;
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+
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+ memset(skb->head, 0, length);
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+ skb_reserve(skb, sizeof(struct mtk_wed_mcu_hdr));
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+ if (data && data_len)
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+ skb_put_data(skb, data, data_len);
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+
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+ return skb;
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+}
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+
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+static struct sk_buff *
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+mtk_wed_mcu_get_response(struct mtk_wed_wo *wo, unsigned long expires)
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+{
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+ if (!time_is_after_jiffies(expires))
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+ return NULL;
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+
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+ wait_event_timeout(wo->mcu.wait, !skb_queue_empty(&wo->mcu.res_q),
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+ expires - jiffies);
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+ return skb_dequeue(&wo->mcu.res_q);
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+}
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+
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+void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb)
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+{
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+ skb_queue_tail(&wo->mcu.res_q, skb);
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+ wake_up(&wo->mcu.wait);
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+}
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+
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+void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
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+ struct sk_buff *skb)
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+{
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+ struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
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+
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+ switch (hdr->cmd) {
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+ case MTK_WED_WO_EVT_LOG_DUMP: {
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+ const char *msg = (const char *)(skb->data + sizeof(*hdr));
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+
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+ dev_notice(wo->hw->dev, "%s\n", msg);
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+ break;
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+ }
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+ case MTK_WED_WO_EVT_PROFILING: {
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+ struct mtk_wed_wo_log_info *info;
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+ u32 count = (skb->len - sizeof(*hdr)) / sizeof(*info);
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+ int i;
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+
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+ info = (struct mtk_wed_wo_log_info *)(skb->data + sizeof(*hdr));
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+ for (i = 0 ; i < count ; i++)
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+ dev_notice(wo->hw->dev,
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+ "SN:%u latency: total=%u, rro:%u, mod:%u\n",
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+ le32_to_cpu(info[i].sn),
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+ le32_to_cpu(info[i].total),
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+ le32_to_cpu(info[i].rro),
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+ le32_to_cpu(info[i].mod));
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+ break;
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+ }
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+ case MTK_WED_WO_EVT_RXCNT_INFO:
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ dev_kfree_skb(skb);
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+}
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+
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+static int
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+mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb,
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+ int id, int cmd, u16 *wait_seq, bool wait_resp)
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+{
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+ struct mtk_wed_mcu_hdr *hdr;
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+
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+ /* TODO: make it dynamic based on cmd */
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+ wo->mcu.timeout = 20 * HZ;
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+
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+ hdr = (struct mtk_wed_mcu_hdr *)skb_push(skb, sizeof(*hdr));
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+ hdr->cmd = cmd;
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+ hdr->length = cpu_to_le16(skb->len);
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+
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+ if (wait_resp && wait_seq) {
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+ u16 seq = ++wo->mcu.seq;
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+
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+ if (!seq)
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+ seq = ++wo->mcu.seq;
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+ *wait_seq = seq;
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+
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+ hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_NEED_RSP);
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+ hdr->seq = cpu_to_le16(seq);
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+ }
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+ if (id == MTK_WED_MODULE_ID_WO)
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+ hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO);
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+
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+ dev_kfree_skb(skb);
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+ return 0;
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+}
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+
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+static int
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+mtk_wed_mcu_parse_response(struct mtk_wed_wo *wo, struct sk_buff *skb,
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+ int cmd, int seq)
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+{
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+ struct mtk_wed_mcu_hdr *hdr;
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+
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+ if (!skb) {
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+ dev_err(wo->hw->dev, "Message %08x (seq %d) timeout\n",
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+ cmd, seq);
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+ return -ETIMEDOUT;
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+ }
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+
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+ hdr = (struct mtk_wed_mcu_hdr *)skb->data;
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+ if (le16_to_cpu(hdr->seq) != seq)
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+ return -EAGAIN;
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+
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+ skb_pull(skb, sizeof(*hdr));
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+ switch (cmd) {
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+ case MTK_WED_WO_CMD_RXCNT_INFO:
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+ default:
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+ break;
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+ }
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+
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+ return 0;
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+}
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+
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+int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
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+ const void *data, int len, bool wait_resp)
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+{
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+ unsigned long expires;
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+ struct sk_buff *skb;
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+ u16 seq;
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+ int ret;
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+
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+ skb = mtk_wed_mcu_msg_alloc(data, len);
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+ if (!skb)
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+ return -ENOMEM;
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+
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+ mutex_lock(&wo->mcu.mutex);
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+
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+ ret = mtk_wed_mcu_skb_send_msg(wo, skb, id, cmd, &seq, wait_resp);
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+ if (ret || !wait_resp)
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+ goto unlock;
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+
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+ expires = jiffies + wo->mcu.timeout;
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+ do {
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+ skb = mtk_wed_mcu_get_response(wo, expires);
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+ ret = mtk_wed_mcu_parse_response(wo, skb, cmd, seq);
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+ dev_kfree_skb(skb);
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+ } while (ret == -EAGAIN);
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+
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+unlock:
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+ mutex_unlock(&wo->mcu.mutex);
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+
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+ return ret;
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+}
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+
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+static int
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+mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
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+ struct mtk_wed_wo_memory_region *region)
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+{
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+ struct reserved_mem *rmem;
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+ struct device_node *np;
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+ int index;
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+
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+ index = of_property_match_string(wo->hw->node, "memory-region-names",
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+ region->name);
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+ if (index < 0)
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+ return index;
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+
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+ np = of_parse_phandle(wo->hw->node, "memory-region", index);
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+ if (!np)
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+ return -ENODEV;
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+
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+ rmem = of_reserved_mem_lookup(np);
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+ of_node_put(np);
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+
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+ if (!rmem)
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+ return -ENODEV;
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+
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+ region->phy_addr = rmem->base;
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+ region->size = rmem->size;
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+ region->addr = devm_ioremap(wo->hw->dev, region->phy_addr, region->size);
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+
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+ return !region->addr ? -EINVAL : 0;
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+}
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+
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+static int
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+mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
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+ struct mtk_wed_wo_memory_region *region)
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+{
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+ const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
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+ const struct mtk_wed_fw_trailer *trailer;
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+ const struct mtk_wed_fw_region *fw_region;
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+
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+ trailer_ptr = fw->data + fw->size - sizeof(*trailer);
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+ trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
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+ region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
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+ first_region_ptr = region_ptr;
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+
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+ while (region_ptr < trailer_ptr) {
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+ u32 length;
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+
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+ fw_region = (const struct mtk_wed_fw_region *)region_ptr;
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+ length = le32_to_cpu(fw_region->len);
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+
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+ if (region->phy_addr != le32_to_cpu(fw_region->addr))
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+ goto next;
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+
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+ if (region->size < length)
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+ goto next;
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+
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+ if (first_region_ptr < ptr + length)
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+ goto next;
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+
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+ if (region->shared && region->consumed)
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+ return 0;
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+
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+ if (!region->shared || !region->consumed) {
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+ memcpy_toio(region->addr, ptr, length);
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+ region->consumed = true;
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+ return 0;
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+ }
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+next:
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+ region_ptr += sizeof(*fw_region);
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+ ptr += length;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+static int
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+mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
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+{
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+ static struct mtk_wed_wo_memory_region mem_region[] = {
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+ [MTK_WED_WO_REGION_EMI] = {
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+ .name = "wo-emi",
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+ },
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+ [MTK_WED_WO_REGION_ILM] = {
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+ .name = "wo-ilm",
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+ },
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+ [MTK_WED_WO_REGION_DATA] = {
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+ .name = "wo-data",
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+ .shared = true,
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+ },
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+ };
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+ const struct mtk_wed_fw_trailer *trailer;
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+ const struct firmware *fw;
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+ const char *fw_name;
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+ u32 val, boot_cr;
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+ int ret, i;
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+
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+ /* load firmware region metadata */
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+ for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
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+ ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
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+ if (ret)
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+ return ret;
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+ }
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+
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+ wo->boot.name = "wo-boot";
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+ ret = mtk_wed_get_memory_region(wo, &wo->boot);
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+ if (ret)
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+ return ret;
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+
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+ /* set dummy cr */
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+ wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
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+ wo->hw->index + 1);
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+
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+ /* load firmware */
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+ fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
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+ ret = request_firmware(&fw, fw_name, wo->hw->dev);
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+ if (ret)
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+ return ret;
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+
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+ trailer = (void *)(fw->data + fw->size -
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+ sizeof(struct mtk_wed_fw_trailer));
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+ dev_info(wo->hw->dev,
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+ "MTK WED WO Firmware Version: %.10s, Build Time: %.15s\n",
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+ trailer->fw_ver, trailer->build_date);
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+ dev_info(wo->hw->dev, "MTK WED WO Chip ID %02x Region %d\n",
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+ trailer->chip_id, trailer->num_region);
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+
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+ for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
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+ ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
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+ if (ret)
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+ goto out;
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+ }
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+
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+ /* set the start address */
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+ boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
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+ : MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
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+ wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
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+ /* wo firmware reset */
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+ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
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+
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+ val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
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+ val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
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+ : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
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+ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
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+out:
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+ release_firmware(fw);
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+
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+ return ret;
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+}
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+
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+static u32
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+mtk_wed_mcu_read_fw_dl(struct mtk_wed_wo *wo)
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+{
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+ return wed_r32(wo->hw->wed_dev,
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+ MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL);
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+}
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+
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+int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
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+{
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+ u32 val;
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+ int ret;
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+
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+ skb_queue_head_init(&wo->mcu.res_q);
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+ init_waitqueue_head(&wo->mcu.wait);
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+ mutex_init(&wo->mcu.mutex);
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+
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+ ret = mtk_wed_mcu_load_firmware(wo);
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+ if (ret)
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+ return ret;
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+
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+ return readx_poll_timeout(mtk_wed_mcu_read_fw_dl, wo, val, !val,
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+ 100, MTK_FW_DL_TIMEOUT);
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+}
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+
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+MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
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+MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);
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--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
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+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
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@@ -152,6 +152,7 @@ struct mtk_wdma_desc {
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#define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)
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+#define MTK_WED_SCR0 0x3c0
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#define MTK_WED_WPDMA_INT_TRIGGER 0x504
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#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
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#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
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@@ -0,0 +1,150 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/* Copyright (C) 2022 Lorenzo Bianconi <lorenzo@kernel.org> */
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+
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+#ifndef __MTK_WED_WO_H
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+#define __MTK_WED_WO_H
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+
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+#include <linux/skbuff.h>
|
||||
+#include <linux/netdevice.h>
|
||||
+
|
||||
+struct mtk_wed_hw;
|
||||
+
|
||||
+struct mtk_wed_mcu_hdr {
|
||||
+ /* DW0 */
|
||||
+ u8 version;
|
||||
+ u8 cmd;
|
||||
+ __le16 length;
|
||||
+
|
||||
+ /* DW1 */
|
||||
+ __le16 seq;
|
||||
+ __le16 flag;
|
||||
+
|
||||
+ /* DW2 */
|
||||
+ __le32 status;
|
||||
+
|
||||
+ /* DW3 */
|
||||
+ u8 rsv[20];
|
||||
+};
|
||||
+
|
||||
+struct mtk_wed_wo_log_info {
|
||||
+ __le32 sn;
|
||||
+ __le32 total;
|
||||
+ __le32 rro;
|
||||
+ __le32 mod;
|
||||
+};
|
||||
+
|
||||
+enum mtk_wed_wo_event {
|
||||
+ MTK_WED_WO_EVT_LOG_DUMP = 0x1,
|
||||
+ MTK_WED_WO_EVT_PROFILING = 0x2,
|
||||
+ MTK_WED_WO_EVT_RXCNT_INFO = 0x3,
|
||||
+};
|
||||
+
|
||||
+#define MTK_WED_MODULE_ID_WO 1
|
||||
+#define MTK_FW_DL_TIMEOUT 4000000 /* us */
|
||||
+#define MTK_WOCPU_TIMEOUT 2000000 /* us */
|
||||
+
|
||||
+enum {
|
||||
+ MTK_WED_WARP_CMD_FLAG_RSP = BIT(0),
|
||||
+ MTK_WED_WARP_CMD_FLAG_NEED_RSP = BIT(1),
|
||||
+ MTK_WED_WARP_CMD_FLAG_FROM_TO_WO = BIT(2),
|
||||
+};
|
||||
+
|
||||
+enum {
|
||||
+ MTK_WED_WO_REGION_EMI,
|
||||
+ MTK_WED_WO_REGION_ILM,
|
||||
+ MTK_WED_WO_REGION_DATA,
|
||||
+ MTK_WED_WO_REGION_BOOT,
|
||||
+ __MTK_WED_WO_REGION_MAX,
|
||||
+};
|
||||
+
|
||||
+enum mtk_wed_dummy_cr_idx {
|
||||
+ MTK_WED_DUMMY_CR_FWDL,
|
||||
+ MTK_WED_DUMMY_CR_WO_STATUS,
|
||||
+};
|
||||
+
|
||||
+#define MT7986_FIRMWARE_WO0 "mediatek/mt7986_wo_0.bin"
|
||||
+#define MT7986_FIRMWARE_WO1 "mediatek/mt7986_wo_1.bin"
|
||||
+
|
||||
+#define MTK_WO_MCU_CFG_LS_BASE 0
|
||||
+#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
|
||||
+#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x004)
|
||||
+#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x00c)
|
||||
+#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x010)
|
||||
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x014)
|
||||
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_SET_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x018)
|
||||
+#define MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x01c)
|
||||
+#define MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x050)
|
||||
+#define MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x060)
|
||||
+#define MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x064)
|
||||
+
|
||||
+#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK BIT(5)
|
||||
+#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK BIT(0)
|
||||
+
|
||||
+struct mtk_wed_wo_memory_region {
|
||||
+ const char *name;
|
||||
+ void __iomem *addr;
|
||||
+ phys_addr_t phy_addr;
|
||||
+ u32 size;
|
||||
+ bool shared:1;
|
||||
+ bool consumed:1;
|
||||
+};
|
||||
+
|
||||
+struct mtk_wed_fw_region {
|
||||
+ __le32 decomp_crc;
|
||||
+ __le32 decomp_len;
|
||||
+ __le32 decomp_blk_sz;
|
||||
+ u8 rsv0[4];
|
||||
+ __le32 addr;
|
||||
+ __le32 len;
|
||||
+ u8 feature_set;
|
||||
+ u8 rsv1[15];
|
||||
+} __packed;
|
||||
+
|
||||
+struct mtk_wed_fw_trailer {
|
||||
+ u8 chip_id;
|
||||
+ u8 eco_code;
|
||||
+ u8 num_region;
|
||||
+ u8 format_ver;
|
||||
+ u8 format_flag;
|
||||
+ u8 rsv[2];
|
||||
+ char fw_ver[10];
|
||||
+ char build_date[15];
|
||||
+ u32 crc;
|
||||
+};
|
||||
+
|
||||
+struct mtk_wed_wo {
|
||||
+ struct mtk_wed_hw *hw;
|
||||
+ struct mtk_wed_wo_memory_region boot;
|
||||
+
|
||||
+ struct {
|
||||
+ struct mutex mutex;
|
||||
+ int timeout;
|
||||
+ u16 seq;
|
||||
+
|
||||
+ struct sk_buff_head res_q;
|
||||
+ wait_queue_head_t wait;
|
||||
+ } mcu;
|
||||
+};
|
||||
+
|
||||
+static inline int
|
||||
+mtk_wed_mcu_check_msg(struct mtk_wed_wo *wo, struct sk_buff *skb)
|
||||
+{
|
||||
+ struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data;
|
||||
+
|
||||
+ if (hdr->version)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ if (skb->len < sizeof(*hdr) || skb->len != le16_to_cpu(hdr->length))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+void mtk_wed_mcu_rx_event(struct mtk_wed_wo *wo, struct sk_buff *skb);
|
||||
+void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo,
|
||||
+ struct sk_buff *skb);
|
||||
+int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
|
||||
+ const void *data, int len, bool wait_resp);
|
||||
+int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
|
||||
+
|
||||
+#endif /* __MTK_WED_WO_H */
|
||||
--- a/include/linux/soc/mediatek/mtk_wed.h
|
||||
+++ b/include/linux/soc/mediatek/mtk_wed.h
|
||||
@@ -11,6 +11,35 @@
|
||||
struct mtk_wed_hw;
|
||||
struct mtk_wdma_desc;
|
||||
|
||||
+enum mtk_wed_wo_cmd {
|
||||
+ MTK_WED_WO_CMD_WED_CFG,
|
||||
+ MTK_WED_WO_CMD_WED_RX_STAT,
|
||||
+ MTK_WED_WO_CMD_RRO_SER,
|
||||
+ MTK_WED_WO_CMD_DBG_INFO,
|
||||
+ MTK_WED_WO_CMD_DEV_INFO,
|
||||
+ MTK_WED_WO_CMD_BSS_INFO,
|
||||
+ MTK_WED_WO_CMD_STA_REC,
|
||||
+ MTK_WED_WO_CMD_DEV_INFO_DUMP,
|
||||
+ MTK_WED_WO_CMD_BSS_INFO_DUMP,
|
||||
+ MTK_WED_WO_CMD_STA_REC_DUMP,
|
||||
+ MTK_WED_WO_CMD_BA_INFO_DUMP,
|
||||
+ MTK_WED_WO_CMD_FBCMD_Q_DUMP,
|
||||
+ MTK_WED_WO_CMD_FW_LOG_CTRL,
|
||||
+ MTK_WED_WO_CMD_LOG_FLUSH,
|
||||
+ MTK_WED_WO_CMD_CHANGE_STATE,
|
||||
+ MTK_WED_WO_CMD_CPU_STATS_ENABLE,
|
||||
+ MTK_WED_WO_CMD_CPU_STATS_DUMP,
|
||||
+ MTK_WED_WO_CMD_EXCEPTION_INIT,
|
||||
+ MTK_WED_WO_CMD_PROF_CTRL,
|
||||
+ MTK_WED_WO_CMD_STA_BA_DUMP,
|
||||
+ MTK_WED_WO_CMD_BA_CTRL_DUMP,
|
||||
+ MTK_WED_WO_CMD_RXCNT_CTRL,
|
||||
+ MTK_WED_WO_CMD_RXCNT_INFO,
|
||||
+ MTK_WED_WO_CMD_SET_CAP,
|
||||
+ MTK_WED_WO_CMD_CCIF_RING_DUMP,
|
||||
+ MTK_WED_WO_CMD_WED_END
|
||||
+};
|
||||
+
|
||||
enum mtk_wed_bus_tye {
|
||||
MTK_WED_BUS_PCIE,
|
||||
MTK_WED_BUS_AXI,
|
@ -0,0 +1,737 @@
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sat, 5 Nov 2022 23:36:19 +0100
|
||||
Subject: [PATCH] net: ethernet: mtk_wed: introduce wed wo support
|
||||
|
||||
Introduce WO chip support to mtk wed driver. MTK WED WO is used to
|
||||
implement RX Wireless Ethernet Dispatch and offload traffic received by
|
||||
wlan nic to the wired interface.
|
||||
|
||||
Tested-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
|
||||
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.c
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/Makefile
|
||||
+++ b/drivers/net/ethernet/mediatek/Makefile
|
||||
@@ -5,7 +5,7 @@
|
||||
|
||||
obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
|
||||
mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
|
||||
-mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o
|
||||
+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
|
||||
ifdef CONFIG_DEBUG_FS
|
||||
mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
|
||||
endif
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
|
||||
@@ -16,6 +16,7 @@
|
||||
#include "mtk_wed_regs.h"
|
||||
#include "mtk_wed.h"
|
||||
#include "mtk_ppe.h"
|
||||
+#include "mtk_wed_wo.h"
|
||||
|
||||
#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
|
||||
|
||||
@@ -355,6 +356,8 @@ mtk_wed_detach(struct mtk_wed_device *de
|
||||
|
||||
mtk_wed_free_buffer(dev);
|
||||
mtk_wed_free_tx_rings(dev);
|
||||
+ if (hw->version != 1)
|
||||
+ mtk_wed_wo_deinit(hw);
|
||||
|
||||
if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
|
||||
struct device_node *wlan_node;
|
||||
@@ -885,9 +888,11 @@ mtk_wed_attach(struct mtk_wed_device *de
|
||||
}
|
||||
|
||||
mtk_wed_hw_init_early(dev);
|
||||
- if (hw->hifsys)
|
||||
+ if (hw->version == 1)
|
||||
regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
|
||||
BIT(hw->index), 0);
|
||||
+ else
|
||||
+ ret = mtk_wed_wo_init(hw);
|
||||
|
||||
out:
|
||||
mutex_unlock(&hw_lock);
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed.h
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
|
||||
@@ -10,6 +10,7 @@
|
||||
#include <linux/netdevice.h>
|
||||
|
||||
struct mtk_eth;
|
||||
+struct mtk_wed_wo;
|
||||
|
||||
struct mtk_wed_hw {
|
||||
struct device_node *node;
|
||||
@@ -22,6 +23,7 @@ struct mtk_wed_hw {
|
||||
struct regmap *mirror;
|
||||
struct dentry *debugfs_dir;
|
||||
struct mtk_wed_device *wed_dev;
|
||||
+ struct mtk_wed_wo *wed_wo;
|
||||
u32 debugfs_reg;
|
||||
u32 num_flows;
|
||||
u8 version;
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
@@ -122,8 +122,7 @@ mtk_wed_mcu_skb_send_msg(struct mtk_wed_
|
||||
if (id == MTK_WED_MODULE_ID_WO)
|
||||
hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO);
|
||||
|
||||
- dev_kfree_skb(skb);
|
||||
- return 0;
|
||||
+ return mtk_wed_wo_queue_tx_skb(wo, &wo->q_tx, skb);
|
||||
}
|
||||
|
||||
static int
|
||||
--- /dev/null
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c
|
||||
@@ -0,0 +1,508 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+/* Copyright (C) 2022 MediaTek Inc.
|
||||
+ *
|
||||
+ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
+ * Sujuan Chen <sujuan.chen@mediatek.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/bitfield.h>
|
||||
+
|
||||
+#include "mtk_wed.h"
|
||||
+#include "mtk_wed_regs.h"
|
||||
+#include "mtk_wed_wo.h"
|
||||
+
|
||||
+static u32
|
||||
+mtk_wed_mmio_r32(struct mtk_wed_wo *wo, u32 reg)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (regmap_read(wo->mmio.regs, reg, &val))
|
||||
+ val = ~0;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_mmio_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
|
||||
+{
|
||||
+ regmap_write(wo->mmio.regs, reg, val);
|
||||
+}
|
||||
+
|
||||
+static u32
|
||||
+mtk_wed_wo_get_isr(struct mtk_wed_wo *wo)
|
||||
+{
|
||||
+ u32 val = mtk_wed_mmio_r32(wo, MTK_WED_WO_CCIF_RCHNUM);
|
||||
+
|
||||
+ return val & MTK_WED_WO_CCIF_RCHNUM_MASK;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_set_isr(struct mtk_wed_wo *wo, u32 mask)
|
||||
+{
|
||||
+ mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_IRQ0_MASK, mask);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_set_ack(struct mtk_wed_wo *wo, u32 mask)
|
||||
+{
|
||||
+ mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_ACK, mask);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_set_isr_mask(struct mtk_wed_wo *wo, u32 mask, u32 val, bool set)
|
||||
+{
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ spin_lock_irqsave(&wo->mmio.lock, flags);
|
||||
+ wo->mmio.irq_mask &= ~mask;
|
||||
+ wo->mmio.irq_mask |= val;
|
||||
+ if (set)
|
||||
+ mtk_wed_wo_set_isr(wo, wo->mmio.irq_mask);
|
||||
+ spin_unlock_irqrestore(&wo->mmio.lock, flags);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_irq_enable(struct mtk_wed_wo *wo, u32 mask)
|
||||
+{
|
||||
+ mtk_wed_wo_set_isr_mask(wo, 0, mask, false);
|
||||
+ tasklet_schedule(&wo->mmio.irq_tasklet);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_irq_disable(struct mtk_wed_wo *wo, u32 mask)
|
||||
+{
|
||||
+ mtk_wed_wo_set_isr_mask(wo, mask, 0, true);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_kickout(struct mtk_wed_wo *wo)
|
||||
+{
|
||||
+ mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_BUSY, 1 << MTK_WED_WO_TXCH_NUM);
|
||||
+ mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_TCHNUM, MTK_WED_WO_TXCH_NUM);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_queue_kick(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q,
|
||||
+ u32 val)
|
||||
+{
|
||||
+ wmb();
|
||||
+ mtk_wed_mmio_w32(wo, q->regs.cpu_idx, val);
|
||||
+}
|
||||
+
|
||||
+static void *
|
||||
+mtk_wed_wo_dequeue(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, u32 *len,
|
||||
+ bool flush)
|
||||
+{
|
||||
+ int buf_len = SKB_WITH_OVERHEAD(q->buf_size);
|
||||
+ int index = (q->tail + 1) % q->n_desc;
|
||||
+ struct mtk_wed_wo_queue_entry *entry;
|
||||
+ struct mtk_wed_wo_queue_desc *desc;
|
||||
+ void *buf;
|
||||
+
|
||||
+ if (!q->queued)
|
||||
+ return NULL;
|
||||
+
|
||||
+ if (flush)
|
||||
+ q->desc[index].ctrl |= cpu_to_le32(MTK_WED_WO_CTL_DMA_DONE);
|
||||
+ else if (!(q->desc[index].ctrl & cpu_to_le32(MTK_WED_WO_CTL_DMA_DONE)))
|
||||
+ return NULL;
|
||||
+
|
||||
+ q->tail = index;
|
||||
+ q->queued--;
|
||||
+
|
||||
+ desc = &q->desc[index];
|
||||
+ entry = &q->entry[index];
|
||||
+ buf = entry->buf;
|
||||
+ if (len)
|
||||
+ *len = FIELD_GET(MTK_WED_WO_CTL_SD_LEN0,
|
||||
+ le32_to_cpu(READ_ONCE(desc->ctrl)));
|
||||
+ if (buf)
|
||||
+ dma_unmap_single(wo->hw->dev, entry->addr, buf_len,
|
||||
+ DMA_FROM_DEVICE);
|
||||
+ entry->buf = NULL;
|
||||
+
|
||||
+ return buf;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+mtk_wed_wo_queue_refill(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q,
|
||||
+ gfp_t gfp, bool rx)
|
||||
+{
|
||||
+ enum dma_data_direction dir = rx ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
|
||||
+ int n_buf = 0;
|
||||
+
|
||||
+ spin_lock_bh(&q->lock);
|
||||
+ while (q->queued < q->n_desc) {
|
||||
+ void *buf = page_frag_alloc(&q->cache, q->buf_size, gfp);
|
||||
+ struct mtk_wed_wo_queue_entry *entry;
|
||||
+ dma_addr_t addr;
|
||||
+
|
||||
+ if (!buf)
|
||||
+ break;
|
||||
+
|
||||
+ addr = dma_map_single(wo->hw->dev, buf, q->buf_size, dir);
|
||||
+ if (unlikely(dma_mapping_error(wo->hw->dev, addr))) {
|
||||
+ skb_free_frag(buf);
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ q->head = (q->head + 1) % q->n_desc;
|
||||
+ entry = &q->entry[q->head];
|
||||
+ entry->addr = addr;
|
||||
+ entry->len = q->buf_size;
|
||||
+ q->entry[q->head].buf = buf;
|
||||
+
|
||||
+ if (rx) {
|
||||
+ struct mtk_wed_wo_queue_desc *desc = &q->desc[q->head];
|
||||
+ u32 ctrl = MTK_WED_WO_CTL_LAST_SEC0 |
|
||||
+ FIELD_PREP(MTK_WED_WO_CTL_SD_LEN0,
|
||||
+ entry->len);
|
||||
+
|
||||
+ WRITE_ONCE(desc->buf0, cpu_to_le32(addr));
|
||||
+ WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
|
||||
+ }
|
||||
+ q->queued++;
|
||||
+ n_buf++;
|
||||
+ }
|
||||
+ spin_unlock_bh(&q->lock);
|
||||
+
|
||||
+ return n_buf;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_rx_complete(struct mtk_wed_wo *wo)
|
||||
+{
|
||||
+ mtk_wed_wo_set_ack(wo, MTK_WED_WO_RXCH_INT_MASK);
|
||||
+ mtk_wed_wo_irq_enable(wo, MTK_WED_WO_RXCH_INT_MASK);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_rx_run_queue(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q)
|
||||
+{
|
||||
+ for (;;) {
|
||||
+ struct mtk_wed_mcu_hdr *hdr;
|
||||
+ struct sk_buff *skb;
|
||||
+ void *data;
|
||||
+ u32 len;
|
||||
+
|
||||
+ data = mtk_wed_wo_dequeue(wo, q, &len, false);
|
||||
+ if (!data)
|
||||
+ break;
|
||||
+
|
||||
+ skb = build_skb(data, q->buf_size);
|
||||
+ if (!skb) {
|
||||
+ skb_free_frag(data);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ __skb_put(skb, len);
|
||||
+ if (mtk_wed_mcu_check_msg(wo, skb)) {
|
||||
+ dev_kfree_skb(skb);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ hdr = (struct mtk_wed_mcu_hdr *)skb->data;
|
||||
+ if (hdr->flag & cpu_to_le16(MTK_WED_WARP_CMD_FLAG_RSP))
|
||||
+ mtk_wed_mcu_rx_event(wo, skb);
|
||||
+ else
|
||||
+ mtk_wed_mcu_rx_unsolicited_event(wo, skb);
|
||||
+ }
|
||||
+
|
||||
+ if (mtk_wed_wo_queue_refill(wo, q, GFP_ATOMIC, true)) {
|
||||
+ u32 index = (q->head - 1) % q->n_desc;
|
||||
+
|
||||
+ mtk_wed_wo_queue_kick(wo, q, index);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t
|
||||
+mtk_wed_wo_irq_handler(int irq, void *data)
|
||||
+{
|
||||
+ struct mtk_wed_wo *wo = data;
|
||||
+
|
||||
+ mtk_wed_wo_set_isr(wo, 0);
|
||||
+ tasklet_schedule(&wo->mmio.irq_tasklet);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static void mtk_wed_wo_irq_tasklet(struct tasklet_struct *t)
|
||||
+{
|
||||
+ struct mtk_wed_wo *wo = from_tasklet(wo, t, mmio.irq_tasklet);
|
||||
+ u32 intr, mask;
|
||||
+
|
||||
+ /* disable interrupts */
|
||||
+ mtk_wed_wo_set_isr(wo, 0);
|
||||
+
|
||||
+ intr = mtk_wed_wo_get_isr(wo);
|
||||
+ intr &= wo->mmio.irq_mask;
|
||||
+ mask = intr & (MTK_WED_WO_RXCH_INT_MASK | MTK_WED_WO_EXCEPTION_INT_MASK);
|
||||
+ mtk_wed_wo_irq_disable(wo, mask);
|
||||
+
|
||||
+ if (intr & MTK_WED_WO_RXCH_INT_MASK) {
|
||||
+ mtk_wed_wo_rx_run_queue(wo, &wo->q_rx);
|
||||
+ mtk_wed_wo_rx_complete(wo);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/* mtk wed wo hw queues */
|
||||
+
|
||||
+static int
|
||||
+mtk_wed_wo_queue_alloc(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q,
|
||||
+ int n_desc, int buf_size, int index,
|
||||
+ struct mtk_wed_wo_queue_regs *regs)
|
||||
+{
|
||||
+ spin_lock_init(&q->lock);
|
||||
+ q->regs = *regs;
|
||||
+ q->n_desc = n_desc;
|
||||
+ q->buf_size = buf_size;
|
||||
+
|
||||
+ q->desc = dmam_alloc_coherent(wo->hw->dev, n_desc * sizeof(*q->desc),
|
||||
+ &q->desc_dma, GFP_KERNEL);
|
||||
+ if (!q->desc)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ q->entry = devm_kzalloc(wo->hw->dev, n_desc * sizeof(*q->entry),
|
||||
+ GFP_KERNEL);
|
||||
+ if (!q->entry)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_queue_free(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q)
|
||||
+{
|
||||
+ mtk_wed_mmio_w32(wo, q->regs.cpu_idx, 0);
|
||||
+ dma_free_coherent(wo->hw->dev, q->n_desc * sizeof(*q->desc), q->desc,
|
||||
+ q->desc_dma);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_queue_tx_clean(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q)
|
||||
+{
|
||||
+ struct page *page;
|
||||
+ int i;
|
||||
+
|
||||
+ spin_lock_bh(&q->lock);
|
||||
+ for (i = 0; i < q->n_desc; i++) {
|
||||
+ struct mtk_wed_wo_queue_entry *entry = &q->entry[i];
|
||||
+
|
||||
+ dma_unmap_single(wo->hw->dev, entry->addr, entry->len,
|
||||
+ DMA_TO_DEVICE);
|
||||
+ skb_free_frag(entry->buf);
|
||||
+ entry->buf = NULL;
|
||||
+ }
|
||||
+ spin_unlock_bh(&q->lock);
|
||||
+
|
||||
+ if (!q->cache.va)
|
||||
+ return;
|
||||
+
|
||||
+ page = virt_to_page(q->cache.va);
|
||||
+ __page_frag_cache_drain(page, q->cache.pagecnt_bias);
|
||||
+ memset(&q->cache, 0, sizeof(q->cache));
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_queue_rx_clean(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q)
|
||||
+{
|
||||
+ struct page *page;
|
||||
+
|
||||
+ spin_lock_bh(&q->lock);
|
||||
+ for (;;) {
|
||||
+ void *buf = mtk_wed_wo_dequeue(wo, q, NULL, true);
|
||||
+
|
||||
+ if (!buf)
|
||||
+ break;
|
||||
+
|
||||
+ skb_free_frag(buf);
|
||||
+ }
|
||||
+ spin_unlock_bh(&q->lock);
|
||||
+
|
||||
+ if (!q->cache.va)
|
||||
+ return;
|
||||
+
|
||||
+ page = virt_to_page(q->cache.va);
|
||||
+ __page_frag_cache_drain(page, q->cache.pagecnt_bias);
|
||||
+ memset(&q->cache, 0, sizeof(q->cache));
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_queue_reset(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q)
|
||||
+{
|
||||
+ mtk_wed_mmio_w32(wo, q->regs.cpu_idx, 0);
|
||||
+ mtk_wed_mmio_w32(wo, q->regs.desc_base, q->desc_dma);
|
||||
+ mtk_wed_mmio_w32(wo, q->regs.ring_size, q->n_desc);
|
||||
+}
|
||||
+
|
||||
+int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q,
|
||||
+ struct sk_buff *skb)
|
||||
+{
|
||||
+ struct mtk_wed_wo_queue_entry *entry;
|
||||
+ struct mtk_wed_wo_queue_desc *desc;
|
||||
+ int ret = 0, index;
|
||||
+ u32 ctrl;
|
||||
+
|
||||
+ spin_lock_bh(&q->lock);
|
||||
+
|
||||
+ q->tail = mtk_wed_mmio_r32(wo, q->regs.dma_idx);
|
||||
+ index = (q->head + 1) % q->n_desc;
|
||||
+ if (q->tail == index) {
|
||||
+ ret = -ENOMEM;
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ entry = &q->entry[index];
|
||||
+ if (skb->len > entry->len) {
|
||||
+ ret = -ENOMEM;
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ desc = &q->desc[index];
|
||||
+ q->head = index;
|
||||
+
|
||||
+ dma_sync_single_for_cpu(wo->hw->dev, entry->addr, skb->len,
|
||||
+ DMA_TO_DEVICE);
|
||||
+ memcpy(entry->buf, skb->data, skb->len);
|
||||
+ dma_sync_single_for_device(wo->hw->dev, entry->addr, skb->len,
|
||||
+ DMA_TO_DEVICE);
|
||||
+
|
||||
+ ctrl = FIELD_PREP(MTK_WED_WO_CTL_SD_LEN0, skb->len) |
|
||||
+ MTK_WED_WO_CTL_LAST_SEC0 | MTK_WED_WO_CTL_DMA_DONE;
|
||||
+ WRITE_ONCE(desc->buf0, cpu_to_le32(entry->addr));
|
||||
+ WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl));
|
||||
+
|
||||
+ mtk_wed_wo_queue_kick(wo, q, q->head);
|
||||
+ mtk_wed_wo_kickout(wo);
|
||||
+out:
|
||||
+ spin_unlock_bh(&q->lock);
|
||||
+
|
||||
+ dev_kfree_skb(skb);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+mtk_wed_wo_exception_init(struct mtk_wed_wo *wo)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+mtk_wed_wo_hardware_init(struct mtk_wed_wo *wo)
|
||||
+{
|
||||
+ struct mtk_wed_wo_queue_regs regs;
|
||||
+ struct device_node *np;
|
||||
+ int ret;
|
||||
+
|
||||
+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ccif", 0);
|
||||
+ if (!np)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ wo->mmio.regs = syscon_regmap_lookup_by_phandle(np, NULL);
|
||||
+ if (IS_ERR_OR_NULL(wo->mmio.regs))
|
||||
+ return PTR_ERR(wo->mmio.regs);
|
||||
+
|
||||
+ wo->mmio.irq = irq_of_parse_and_map(np, 0);
|
||||
+ wo->mmio.irq_mask = MTK_WED_WO_ALL_INT_MASK;
|
||||
+ spin_lock_init(&wo->mmio.lock);
|
||||
+ tasklet_setup(&wo->mmio.irq_tasklet, mtk_wed_wo_irq_tasklet);
|
||||
+
|
||||
+ ret = devm_request_irq(wo->hw->dev, wo->mmio.irq,
|
||||
+ mtk_wed_wo_irq_handler, IRQF_TRIGGER_HIGH,
|
||||
+ KBUILD_MODNAME, wo);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+
|
||||
+ regs.desc_base = MTK_WED_WO_CCIF_DUMMY1;
|
||||
+ regs.ring_size = MTK_WED_WO_CCIF_DUMMY2;
|
||||
+ regs.dma_idx = MTK_WED_WO_CCIF_SHADOW4;
|
||||
+ regs.cpu_idx = MTK_WED_WO_CCIF_DUMMY3;
|
||||
+
|
||||
+ ret = mtk_wed_wo_queue_alloc(wo, &wo->q_tx, MTK_WED_WO_RING_SIZE,
|
||||
+ MTK_WED_WO_CMD_LEN, MTK_WED_WO_TXCH_NUM,
|
||||
+ ®s);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+
|
||||
+ mtk_wed_wo_queue_refill(wo, &wo->q_tx, GFP_KERNEL, false);
|
||||
+ mtk_wed_wo_queue_reset(wo, &wo->q_tx);
|
||||
+
|
||||
+ regs.desc_base = MTK_WED_WO_CCIF_DUMMY5;
|
||||
+ regs.ring_size = MTK_WED_WO_CCIF_DUMMY6;
|
||||
+ regs.dma_idx = MTK_WED_WO_CCIF_SHADOW8;
|
||||
+ regs.cpu_idx = MTK_WED_WO_CCIF_DUMMY7;
|
||||
+
|
||||
+ ret = mtk_wed_wo_queue_alloc(wo, &wo->q_rx, MTK_WED_WO_RING_SIZE,
|
||||
+ MTK_WED_WO_CMD_LEN, MTK_WED_WO_RXCH_NUM,
|
||||
+ ®s);
|
||||
+ if (ret)
|
||||
+ goto error;
|
||||
+
|
||||
+ mtk_wed_wo_queue_refill(wo, &wo->q_rx, GFP_KERNEL, true);
|
||||
+ mtk_wed_wo_queue_reset(wo, &wo->q_rx);
|
||||
+
|
||||
+ /* rx queue irqmask */
|
||||
+ mtk_wed_wo_set_isr(wo, wo->mmio.irq_mask);
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+error:
|
||||
+ devm_free_irq(wo->hw->dev, wo->mmio.irq, wo);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+mtk_wed_wo_hw_deinit(struct mtk_wed_wo *wo)
|
||||
+{
|
||||
+ /* disable interrupts */
|
||||
+ mtk_wed_wo_set_isr(wo, 0);
|
||||
+
|
||||
+ tasklet_disable(&wo->mmio.irq_tasklet);
|
||||
+
|
||||
+ disable_irq(wo->mmio.irq);
|
||||
+ devm_free_irq(wo->hw->dev, wo->mmio.irq, wo);
|
||||
+
|
||||
+ mtk_wed_wo_queue_tx_clean(wo, &wo->q_tx);
|
||||
+ mtk_wed_wo_queue_rx_clean(wo, &wo->q_rx);
|
||||
+ mtk_wed_wo_queue_free(wo, &wo->q_tx);
|
||||
+ mtk_wed_wo_queue_free(wo, &wo->q_rx);
|
||||
+}
|
||||
+
|
||||
+int mtk_wed_wo_init(struct mtk_wed_hw *hw)
|
||||
+{
|
||||
+ struct mtk_wed_wo *wo;
|
||||
+ int ret;
|
||||
+
|
||||
+ wo = devm_kzalloc(hw->dev, sizeof(*wo), GFP_KERNEL);
|
||||
+ if (!wo)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ hw->wed_wo = wo;
|
||||
+ wo->hw = hw;
|
||||
+
|
||||
+ ret = mtk_wed_wo_hardware_init(wo);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = mtk_wed_mcu_init(wo);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ return mtk_wed_wo_exception_init(wo);
|
||||
+}
|
||||
+
|
||||
+void mtk_wed_wo_deinit(struct mtk_wed_hw *hw)
|
||||
+{
|
||||
+ struct mtk_wed_wo *wo = hw->wed_wo;
|
||||
+
|
||||
+ mtk_wed_wo_hw_deinit(wo);
|
||||
+}
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
|
||||
@@ -80,6 +80,54 @@ enum mtk_wed_dummy_cr_idx {
|
||||
#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK BIT(5)
|
||||
#define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK BIT(0)
|
||||
|
||||
+#define MTK_WED_WO_RING_SIZE 256
|
||||
+#define MTK_WED_WO_CMD_LEN 1504
|
||||
+
|
||||
+#define MTK_WED_WO_TXCH_NUM 0
|
||||
+#define MTK_WED_WO_RXCH_NUM 1
|
||||
+#define MTK_WED_WO_RXCH_WO_EXCEPTION 7
|
||||
+
|
||||
+#define MTK_WED_WO_TXCH_INT_MASK BIT(0)
|
||||
+#define MTK_WED_WO_RXCH_INT_MASK BIT(1)
|
||||
+#define MTK_WED_WO_EXCEPTION_INT_MASK BIT(7)
|
||||
+#define MTK_WED_WO_ALL_INT_MASK (MTK_WED_WO_RXCH_INT_MASK | \
|
||||
+ MTK_WED_WO_EXCEPTION_INT_MASK)
|
||||
+
|
||||
+#define MTK_WED_WO_CCIF_BUSY 0x004
|
||||
+#define MTK_WED_WO_CCIF_START 0x008
|
||||
+#define MTK_WED_WO_CCIF_TCHNUM 0x00c
|
||||
+#define MTK_WED_WO_CCIF_RCHNUM 0x010
|
||||
+#define MTK_WED_WO_CCIF_RCHNUM_MASK GENMASK(7, 0)
|
||||
+
|
||||
+#define MTK_WED_WO_CCIF_ACK 0x014
|
||||
+#define MTK_WED_WO_CCIF_IRQ0_MASK 0x018
|
||||
+#define MTK_WED_WO_CCIF_IRQ1_MASK 0x01c
|
||||
+#define MTK_WED_WO_CCIF_DUMMY1 0x020
|
||||
+#define MTK_WED_WO_CCIF_DUMMY2 0x024
|
||||
+#define MTK_WED_WO_CCIF_DUMMY3 0x028
|
||||
+#define MTK_WED_WO_CCIF_DUMMY4 0x02c
|
||||
+#define MTK_WED_WO_CCIF_SHADOW1 0x030
|
||||
+#define MTK_WED_WO_CCIF_SHADOW2 0x034
|
||||
+#define MTK_WED_WO_CCIF_SHADOW3 0x038
|
||||
+#define MTK_WED_WO_CCIF_SHADOW4 0x03c
|
||||
+#define MTK_WED_WO_CCIF_DUMMY5 0x050
|
||||
+#define MTK_WED_WO_CCIF_DUMMY6 0x054
|
||||
+#define MTK_WED_WO_CCIF_DUMMY7 0x058
|
||||
+#define MTK_WED_WO_CCIF_DUMMY8 0x05c
|
||||
+#define MTK_WED_WO_CCIF_SHADOW5 0x060
|
||||
+#define MTK_WED_WO_CCIF_SHADOW6 0x064
|
||||
+#define MTK_WED_WO_CCIF_SHADOW7 0x068
|
||||
+#define MTK_WED_WO_CCIF_SHADOW8 0x06c
|
||||
+
|
||||
+#define MTK_WED_WO_CTL_SD_LEN1 GENMASK(13, 0)
|
||||
+#define MTK_WED_WO_CTL_LAST_SEC1 BIT(14)
|
||||
+#define MTK_WED_WO_CTL_BURST BIT(15)
|
||||
+#define MTK_WED_WO_CTL_SD_LEN0_SHIFT 16
|
||||
+#define MTK_WED_WO_CTL_SD_LEN0 GENMASK(29, 16)
|
||||
+#define MTK_WED_WO_CTL_LAST_SEC0 BIT(30)
|
||||
+#define MTK_WED_WO_CTL_DMA_DONE BIT(31)
|
||||
+#define MTK_WED_WO_INFO_WINFO GENMASK(15, 0)
|
||||
+
|
||||
struct mtk_wed_wo_memory_region {
|
||||
const char *name;
|
||||
void __iomem *addr;
|
||||
@@ -112,10 +160,53 @@ struct mtk_wed_fw_trailer {
|
||||
u32 crc;
|
||||
};
|
||||
|
||||
+struct mtk_wed_wo_queue_regs {
|
||||
+ u32 desc_base;
|
||||
+ u32 ring_size;
|
||||
+ u32 cpu_idx;
|
||||
+ u32 dma_idx;
|
||||
+};
|
||||
+
|
||||
+struct mtk_wed_wo_queue_desc {
|
||||
+ __le32 buf0;
|
||||
+ __le32 ctrl;
|
||||
+ __le32 buf1;
|
||||
+ __le32 info;
|
||||
+ __le32 reserved[4];
|
||||
+} __packed __aligned(32);
|
||||
+
|
||||
+struct mtk_wed_wo_queue_entry {
|
||||
+ dma_addr_t addr;
|
||||
+ void *buf;
|
||||
+ u32 len;
|
||||
+};
|
||||
+
|
||||
+struct mtk_wed_wo_queue {
|
||||
+ struct mtk_wed_wo_queue_regs regs;
|
||||
+
|
||||
+ struct page_frag_cache cache;
|
||||
+ spinlock_t lock;
|
||||
+
|
||||
+ struct mtk_wed_wo_queue_desc *desc;
|
||||
+ dma_addr_t desc_dma;
|
||||
+
|
||||
+ struct mtk_wed_wo_queue_entry *entry;
|
||||
+
|
||||
+ u16 head;
|
||||
+ u16 tail;
|
||||
+ int n_desc;
|
||||
+ int queued;
|
||||
+ int buf_size;
|
||||
+
|
||||
+};
|
||||
+
|
||||
struct mtk_wed_wo {
|
||||
struct mtk_wed_hw *hw;
|
||||
struct mtk_wed_wo_memory_region boot;
|
||||
|
||||
+ struct mtk_wed_wo_queue q_tx;
|
||||
+ struct mtk_wed_wo_queue q_rx;
|
||||
+
|
||||
struct {
|
||||
struct mutex mutex;
|
||||
int timeout;
|
||||
@@ -124,6 +215,15 @@ struct mtk_wed_wo {
|
||||
struct sk_buff_head res_q;
|
||||
wait_queue_head_t wait;
|
||||
} mcu;
|
||||
+
|
||||
+ struct {
|
||||
+ struct regmap *regs;
|
||||
+
|
||||
+ spinlock_t lock;
|
||||
+ struct tasklet_struct irq_tasklet;
|
||||
+ int irq;
|
||||
+ u32 irq_mask;
|
||||
+ } mmio;
|
||||
};
|
||||
|
||||
static inline int
|
||||
@@ -146,5 +246,9 @@ void mtk_wed_mcu_rx_unsolicited_event(st
|
||||
int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd,
|
||||
const void *data, int len, bool wait_resp);
|
||||
int mtk_wed_mcu_init(struct mtk_wed_wo *wo);
|
||||
+int mtk_wed_wo_init(struct mtk_wed_hw *hw);
|
||||
+void mtk_wed_wo_deinit(struct mtk_wed_hw *hw);
|
||||
+int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *dev, struct mtk_wed_wo_queue *q,
|
||||
+ struct sk_buff *skb);
|
||||
|
||||
#endif /* __MTK_WED_WO_H */
|
@ -0,0 +1,79 @@
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sat, 5 Nov 2022 23:36:20 +0100
|
||||
Subject: [PATCH] net: ethernet: mtk_wed: rename tx_wdma array in rx_wdma
|
||||
|
||||
Rename tx_wdma queue array in rx_wdma since this is rx side of wdma soc.
|
||||
Moreover rename mtk_wed_wdma_ring_setup routine in
|
||||
mtk_wed_wdma_rx_ring_setup()
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
|
||||
@@ -253,8 +253,8 @@ mtk_wed_free_tx_rings(struct mtk_wed_dev
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
|
||||
mtk_wed_free_ring(dev, &dev->tx_ring[i]);
|
||||
- for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
|
||||
- mtk_wed_free_ring(dev, &dev->tx_wdma[i]);
|
||||
+ for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
|
||||
+ mtk_wed_free_ring(dev, &dev->rx_wdma[i]);
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -695,10 +695,10 @@ mtk_wed_ring_alloc(struct mtk_wed_device
|
||||
}
|
||||
|
||||
static int
|
||||
-mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)
|
||||
+mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
|
||||
{
|
||||
u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
|
||||
- struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
|
||||
+ struct mtk_wed_ring *wdma = &dev->rx_wdma[idx];
|
||||
|
||||
if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size))
|
||||
return -ENOMEM;
|
||||
@@ -812,9 +812,9 @@ mtk_wed_start(struct mtk_wed_device *dev
|
||||
{
|
||||
int i;
|
||||
|
||||
- for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
|
||||
- if (!dev->tx_wdma[i].desc)
|
||||
- mtk_wed_wdma_ring_setup(dev, i, 16);
|
||||
+ for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
|
||||
+ if (!dev->rx_wdma[i].desc)
|
||||
+ mtk_wed_wdma_rx_ring_setup(dev, i, 16);
|
||||
|
||||
mtk_wed_hw_init(dev);
|
||||
mtk_wed_configure_irq(dev, irq_mask);
|
||||
@@ -923,7 +923,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
|
||||
sizeof(*ring->desc)))
|
||||
return -ENOMEM;
|
||||
|
||||
- if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
|
||||
+ if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
|
||||
return -ENOMEM;
|
||||
|
||||
ring->reg_base = MTK_WED_RING_TX(idx);
|
||||
--- a/include/linux/soc/mediatek/mtk_wed.h
|
||||
+++ b/include/linux/soc/mediatek/mtk_wed.h
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <linux/pci.h>
|
||||
|
||||
#define MTK_WED_TX_QUEUES 2
|
||||
+#define MTK_WED_RX_QUEUES 2
|
||||
|
||||
struct mtk_wed_hw;
|
||||
struct mtk_wdma_desc;
|
||||
@@ -66,7 +67,7 @@ struct mtk_wed_device {
|
||||
|
||||
struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];
|
||||
struct mtk_wed_ring txfree_ring;
|
||||
- struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];
|
||||
+ struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
|
||||
|
||||
struct {
|
||||
int size;
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,149 @@
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sat, 5 Nov 2022 23:36:22 +0100
|
||||
Subject: [PATCH] net: ethernet: mtk_wed: add rx mib counters
|
||||
|
||||
Introduce WED RX MIB counters support available on MT7986a SoC.
|
||||
|
||||
Tested-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
|
||||
Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
|
||||
@@ -2,6 +2,7 @@
|
||||
/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
|
||||
|
||||
#include <linux/seq_file.h>
|
||||
+#include <linux/soc/mediatek/mtk_wed.h>
|
||||
#include "mtk_wed.h"
|
||||
#include "mtk_wed_regs.h"
|
||||
|
||||
@@ -18,6 +19,8 @@ enum {
|
||||
DUMP_TYPE_WDMA,
|
||||
DUMP_TYPE_WPDMA_TX,
|
||||
DUMP_TYPE_WPDMA_TXFREE,
|
||||
+ DUMP_TYPE_WPDMA_RX,
|
||||
+ DUMP_TYPE_WED_RRO,
|
||||
};
|
||||
|
||||
#define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
|
||||
@@ -36,6 +39,9 @@ enum {
|
||||
|
||||
#define DUMP_WPDMA_TX_RING(_n) DUMP_RING("WPDMA_TX" #_n, 0, DUMP_TYPE_WPDMA_TX, _n)
|
||||
#define DUMP_WPDMA_TXFREE_RING DUMP_RING("WPDMA_RX1", 0, DUMP_TYPE_WPDMA_TXFREE)
|
||||
+#define DUMP_WPDMA_RX_RING(_n) DUMP_RING("WPDMA_RX" #_n, 0, DUMP_TYPE_WPDMA_RX, _n)
|
||||
+#define DUMP_WED_RRO_RING(_base)DUMP_RING("WED_RRO_MIOD", MTK_##_base, DUMP_TYPE_WED_RRO)
|
||||
+#define DUMP_WED_RRO_FDBK(_base)DUMP_RING("WED_RRO_FDBK", MTK_##_base, DUMP_TYPE_WED_RRO)
|
||||
|
||||
static void
|
||||
print_reg_val(struct seq_file *s, const char *name, u32 val)
|
||||
@@ -57,6 +63,7 @@ dump_wed_regs(struct seq_file *s, struct
|
||||
cur > regs ? "\n" : "",
|
||||
cur->name);
|
||||
continue;
|
||||
+ case DUMP_TYPE_WED_RRO:
|
||||
case DUMP_TYPE_WED:
|
||||
val = wed_r32(dev, cur->offset);
|
||||
break;
|
||||
@@ -69,6 +76,9 @@ dump_wed_regs(struct seq_file *s, struct
|
||||
case DUMP_TYPE_WPDMA_TXFREE:
|
||||
val = wpdma_txfree_r32(dev, cur->offset);
|
||||
break;
|
||||
+ case DUMP_TYPE_WPDMA_RX:
|
||||
+ val = wpdma_rx_r32(dev, cur->base, cur->offset);
|
||||
+ break;
|
||||
}
|
||||
print_reg_val(s, cur->name, val);
|
||||
}
|
||||
@@ -132,6 +142,80 @@ wed_txinfo_show(struct seq_file *s, void
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(wed_txinfo);
|
||||
|
||||
+static int
|
||||
+wed_rxinfo_show(struct seq_file *s, void *data)
|
||||
+{
|
||||
+ static const struct reg_dump regs[] = {
|
||||
+ DUMP_STR("WPDMA RX"),
|
||||
+ DUMP_WPDMA_RX_RING(0),
|
||||
+ DUMP_WPDMA_RX_RING(1),
|
||||
+
|
||||
+ DUMP_STR("WPDMA RX"),
|
||||
+ DUMP_WED(WED_WPDMA_RX_D_MIB(0)),
|
||||
+ DUMP_WED_RING(WED_WPDMA_RING_RX_DATA(0)),
|
||||
+ DUMP_WED(WED_WPDMA_RX_D_PROCESSED_MIB(0)),
|
||||
+ DUMP_WED(WED_WPDMA_RX_D_MIB(1)),
|
||||
+ DUMP_WED_RING(WED_WPDMA_RING_RX_DATA(1)),
|
||||
+ DUMP_WED(WED_WPDMA_RX_D_PROCESSED_MIB(1)),
|
||||
+ DUMP_WED(WED_WPDMA_RX_D_COHERENT_MIB),
|
||||
+
|
||||
+ DUMP_STR("WED RX"),
|
||||
+ DUMP_WED_RING(WED_RING_RX_DATA(0)),
|
||||
+ DUMP_WED_RING(WED_RING_RX_DATA(1)),
|
||||
+
|
||||
+ DUMP_STR("WED RRO"),
|
||||
+ DUMP_WED_RRO_RING(WED_RROQM_MIOD_CTRL0),
|
||||
+ DUMP_WED(WED_RROQM_MID_MIB),
|
||||
+ DUMP_WED(WED_RROQM_MOD_MIB),
|
||||
+ DUMP_WED(WED_RROQM_MOD_COHERENT_MIB),
|
||||
+ DUMP_WED_RRO_FDBK(WED_RROQM_FDBK_CTRL0),
|
||||
+ DUMP_WED(WED_RROQM_FDBK_IND_MIB),
|
||||
+ DUMP_WED(WED_RROQM_FDBK_ENQ_MIB),
|
||||
+ DUMP_WED(WED_RROQM_FDBK_ANC_MIB),
|
||||
+ DUMP_WED(WED_RROQM_FDBK_ANC2H_MIB),
|
||||
+
|
||||
+ DUMP_STR("WED Route QM"),
|
||||
+ DUMP_WED(WED_RTQM_R2H_MIB(0)),
|
||||
+ DUMP_WED(WED_RTQM_R2Q_MIB(0)),
|
||||
+ DUMP_WED(WED_RTQM_Q2H_MIB(0)),
|
||||
+ DUMP_WED(WED_RTQM_R2H_MIB(1)),
|
||||
+ DUMP_WED(WED_RTQM_R2Q_MIB(1)),
|
||||
+ DUMP_WED(WED_RTQM_Q2H_MIB(1)),
|
||||
+ DUMP_WED(WED_RTQM_Q2N_MIB),
|
||||
+ DUMP_WED(WED_RTQM_Q2B_MIB),
|
||||
+ DUMP_WED(WED_RTQM_PFDBK_MIB),
|
||||
+
|
||||
+ DUMP_STR("WED WDMA TX"),
|
||||
+ DUMP_WED(WED_WDMA_TX_MIB),
|
||||
+ DUMP_WED_RING(WED_WDMA_RING_TX),
|
||||
+
|
||||
+ DUMP_STR("WDMA TX"),
|
||||
+ DUMP_WDMA(WDMA_GLO_CFG),
|
||||
+ DUMP_WDMA_RING(WDMA_RING_TX(0)),
|
||||
+ DUMP_WDMA_RING(WDMA_RING_TX(1)),
|
||||
+
|
||||
+ DUMP_STR("WED RX BM"),
|
||||
+ DUMP_WED(WED_RX_BM_BASE),
|
||||
+ DUMP_WED(WED_RX_BM_RX_DMAD),
|
||||
+ DUMP_WED(WED_RX_BM_PTR),
|
||||
+ DUMP_WED(WED_RX_BM_TKID_MIB),
|
||||
+ DUMP_WED(WED_RX_BM_BLEN),
|
||||
+ DUMP_WED(WED_RX_BM_STS),
|
||||
+ DUMP_WED(WED_RX_BM_INTF2),
|
||||
+ DUMP_WED(WED_RX_BM_INTF),
|
||||
+ DUMP_WED(WED_RX_BM_ERR_STS),
|
||||
+ };
|
||||
+ struct mtk_wed_hw *hw = s->private;
|
||||
+ struct mtk_wed_device *dev = hw->wed_dev;
|
||||
+
|
||||
+ if (!dev)
|
||||
+ return 0;
|
||||
+
|
||||
+ dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+DEFINE_SHOW_ATTRIBUTE(wed_rxinfo);
|
||||
|
||||
static int
|
||||
mtk_wed_reg_set(void *data, u64 val)
|
||||
@@ -175,4 +259,7 @@ void mtk_wed_hw_add_debugfs(struct mtk_w
|
||||
debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
|
||||
debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
|
||||
debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
|
||||
+ if (hw->version != 1)
|
||||
+ debugfs_create_file_unsafe("rxinfo", 0400, dir, hw,
|
||||
+ &wed_rxinfo_fops);
|
||||
}
|
Loading…
Reference in New Issue
Block a user