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mediatek: fixes for Ethernet on MT7988 SoC

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* fix switch ports with modes other than 1000M/Full
 * set 32-bit dma_coherent_mask to get PPE to work with 4 GiB of RAM
 * sync driver for built-in 1GE PHY with MediaTek SDK sources

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2024-01-24 05:01:43 +00:00
parent efcc100ef0
commit 4ae2f43b3a
10 changed files with 744 additions and 22 deletions
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46
target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch Normal file
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From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 03:19:49 +0000
Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
working
To: Felix Fietkau <nbd@nbd.name>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
Daniel Golle <daniel@makrotopia.org>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Set DMA coherent mask to 32-bit which makes PPE offloading engine start
working on BPi-R4 which got 4 GiB of RAM.
Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
Suggested-by: Elad Yifee <eladwf@users.github.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4832,7 +4832,10 @@ static int mtk_probe(struct platform_dev
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
+ err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
+ if (!err)
+ err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+
if (err) {
dev_err(&pdev->dev, "Wrong DMA config\n");
return -EINVAL;

45
target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch Normal file
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From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 04:17:11 +0000
Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
To: Arınç ÜNAL <arinc.unal@arinc9.com>,
Daniel Golle <daniel@makrotopia.org>,
DENG Qingfang <dqfext@gmail.com>,
Sean Wang <sean.wang@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Setup PMCR port register for actual speed and duplex on internally
connected PHYs of the MT7988 built-in switch. This fixes links with
speeds other than 1000M.
Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/dsa/mt7530.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2832,8 +2832,7 @@ static void mt753x_phylink_mac_link_up(s
/* MT753x MAC works in 1G full duplex mode for all up-clocked
* variants.
*/
- if (interface == PHY_INTERFACE_MODE_INTERNAL ||
- interface == PHY_INTERFACE_MODE_TRGMII ||
+ if (interface == PHY_INTERFACE_MODE_TRGMII ||
(phy_interface_mode_is_8023z(interface))) {
speed = SPEED_1000;
duplex = DUPLEX_FULL;

46
target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch Normal file
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From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 03:19:49 +0000
Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
working
To: Felix Fietkau <nbd@nbd.name>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
Daniel Golle <daniel@makrotopia.org>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Set DMA coherent mask to 32-bit which makes PPE offloading engine start
working on BPi-R4 which got 4 GiB of RAM.
Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
Suggested-by: Elad Yifee <eladwf@users.github.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -4886,7 +4886,10 @@ static int mtk_probe(struct platform_dev
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
- err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
+ err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
+ if (!err)
+ err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+
if (err) {
dev_err(&pdev->dev, "Wrong DMA config\n");
return -EINVAL;

45
target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch Normal file
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From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 04:17:11 +0000
Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
To: Arınç ÜNAL <arinc.unal@arinc9.com>,
Daniel Golle <daniel@makrotopia.org>,
DENG Qingfang <dqfext@gmail.com>,
Sean Wang <sean.wang@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Setup PMCR port register for actual speed and duplex on internally
connected PHYs of the MT7988 built-in switch. This fixes links with
speeds other than 1000M.
Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/dsa/mt7530.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -2849,8 +2849,7 @@ static void mt753x_phylink_mac_link_up(s
/* MT753x MAC works in 1G full duplex mode for all up-clocked
* variants.
*/
- if (interface == PHY_INTERFACE_MODE_INTERNAL ||
- interface == PHY_INTERFACE_MODE_TRGMII ||
+ if (interface == PHY_INTERFACE_MODE_TRGMII ||
(phy_interface_mode_is_8023z(interface))) {
speed = SPEED_1000;
duplex = DUPLEX_FULL;

270
target/linux/mediatek/patches-5.15/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch Normal file
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From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 02:27:04 +0000
Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
To: Daniel Golle <daniel@makrotopia.org>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Sync initialization and calibration routines with MediaTek's reference
driver. Improves compliance and resolves link stability issues with
CH340 IoT devices connected to MT798x built-in PHYs.
Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
1 file changed, 81 insertions(+), 66 deletions(-)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -479,7 +479,7 @@ static int tx_r50_fill_result(struct phy
u16 reg, val;
if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
- bias = -2;
+ bias = -1;
val = clamp_val(bias + tx_r50_cal_val, 0, 63);
@@ -695,6 +695,11 @@ restore:
static void mt798x_phy_common_finetune(struct phy_device *phydev)
{
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+ __phy_write(phydev, 0x11, 0xc71);
+ __phy_write(phydev, 0x12, 0xc);
+ __phy_write(phydev, 0x10, 0x8fae);
+
/* EnabRandUpdTrig = 1 */
__phy_write(phydev, 0x11, 0x2f00);
__phy_write(phydev, 0x12, 0xe);
@@ -705,15 +710,56 @@ static void mt798x_phy_common_finetune(s
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x83aa);
- /* TrFreeze = 0 */
+ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
+ __phy_write(phydev, 0x11, 0x240);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x9680);
+
+ /* TrFreeze = 0 (mt7988 default) */
__phy_write(phydev, 0x11, 0x0);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9686);
+ /* SSTrKp100 = 5 */
+ /* SSTrKf100 = 6 */
+ /* SSTrKp1000Mas = 5 */
+ /* SSTrKf1000Mas = 6 */
/* SSTrKp1000Slv = 5 */
+ /* SSTrKf1000Slv = 6 */
__phy_write(phydev, 0x11, 0xbaef);
__phy_write(phydev, 0x12, 0x2e);
__phy_write(phydev, 0x10, 0x968c);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+}
+
+static void mt7981_phy_finetune(struct phy_device *phydev)
+{
+ u16 val[8] = { 0x01ce, 0x01c1,
+ 0x020f, 0x0202,
+ 0x03d0, 0x03c0,
+ 0x0013, 0x0005 };
+ int i, k;
+
+ /* 100M eye finetune:
+ * Keep middle level of TX MLT3 shapper as default.
+ * Only change TX MLT3 overshoot level here.
+ */
+ for (k = 0, i = 1; i < 12; i++) {
+ if (i % 3 == 0)
+ continue;
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
+ }
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* ResetSyncOffset = 6 */
+ __phy_write(phydev, 0x11, 0x600);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x8fc0);
+
+ /* VgaDecRate = 1 */
+ __phy_write(phydev, 0x11, 0x4c2a);
+ __phy_write(phydev, 0x12, 0x3e);
+ __phy_write(phydev, 0x10, 0x8fa4);
/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
@@ -728,7 +774,7 @@ static void mt798x_phy_common_finetune(s
__phy_write(phydev, 0x10, 0x8ec0);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
@@ -761,48 +807,6 @@ static void mt798x_phy_common_finetune(s
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
}
-static void mt7981_phy_finetune(struct phy_device *phydev)
-{
- u16 val[8] = { 0x01ce, 0x01c1,
- 0x020f, 0x0202,
- 0x03d0, 0x03c0,
- 0x0013, 0x0005 };
- int i, k;
-
- /* 100M eye finetune:
- * Keep middle level of TX MLT3 shapper as default.
- * Only change TX MLT3 overshoot level here.
- */
- for (k = 0, i = 1; i < 12; i++) {
- if (i % 3 == 0)
- continue;
- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
- }
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
- __phy_write(phydev, 0x11, 0xc71);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
-
- /* FfeUpdGainForce = 4 */
- __phy_write(phydev, 0x11, 0x240);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9680);
-
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
static void mt7988_phy_finetune(struct phy_device *phydev)
{
u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
@@ -817,17 +821,7 @@ static void mt7988_phy_finetune(struct p
/* TCT finetune */
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- /* Disable TX power saving */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
- __phy_write(phydev, 0x11, 0x671);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
/* ResetSyncOffset = 5 */
__phy_write(phydev, 0x11, 0x500);
__phy_write(phydev, 0x12, 0x0);
@@ -835,13 +829,27 @@ static void mt7988_phy_finetune(struct p
/* VgaDecRate is 1 at default on mt7988 */
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
+ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
+ */
+ __phy_write(phydev, 0x11, 0xb90a);
+ __phy_write(phydev, 0x12, 0x6f);
+ __phy_write(phydev, 0x10, 0x8f82);
+
+ /* RemAckCntLimitCtrl = 1 */
+ __phy_write(phydev, 0x11, 0xfbba);
+ __phy_write(phydev, 0x12, 0xc3);
+ __phy_write(phydev, 0x10, 0x87f8);
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
- /* TxClkOffset = 2 */
- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
+
+ /* rg_tr_lpf_cnt_val = 1023 */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
}
static void mt798x_phy_eee(struct phy_device *phydev)
@@ -874,11 +882,11 @@ static void mt798x_phy_eee(struct phy_de
MTK_PHY_LPI_SLV_SEND_TX_EN,
FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
- MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
- MTK_PHY_LPI_TXPCS_LOC_RCV,
- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
+ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
+ MTK_PHY_LPI_TXPCS_LOC_RCV);
+ /* This also fixes some IoT issues, such as CH340 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
@@ -912,7 +920,7 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9690);
- /* REG_EEE_st2TrKf1000 = 3 */
+ /* REG_EEE_st2TrKf1000 = 2 */
__phy_write(phydev, 0x11, 0x114f);
__phy_write(phydev, 0x12, 0x2);
__phy_write(phydev, 0x10, 0x969a);
@@ -937,7 +945,7 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96b8);
- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
__phy_write(phydev, 0x11, 0x1463);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96ca);
@@ -1198,6 +1206,13 @@ static int mt7988_phy_probe(struct phy_d
mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
+ /* Disable TX power saving at probing to:
+ * 1. Meet common mode compliance test criteria
+ * 2. Make sure that TX-VCM calibration works fine
+ */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+
return mt798x_phy_calibration(phydev);
}

18
target/linux/mediatek/patches-5.15/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
View File

@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
if (mtk_is_netsys_v3_or_greater(eth)) { if (mtk_is_netsys_v3_or_greater(eth)) {
@@ -5165,11 +5165,15 @@ static const struct mtk_soc_data mt2701_ @@ -5168,11 +5168,15 @@ static const struct mtk_soc_data mt2701_
.required_clks = MT7623_CLKS_BITMAP, .required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true, .required_pctl = true,
.version = 1, .version = 1,
@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5185,11 +5189,15 @@ static const struct mtk_soc_data mt7621_ @@ -5188,11 +5192,15 @@ static const struct mtk_soc_data mt7621_
.offload_version = 1, .offload_version = 1,
.hash_offset = 2, .hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5207,11 +5215,15 @@ static const struct mtk_soc_data mt7622_ @@ -5210,11 +5218,15 @@ static const struct mtk_soc_data mt7622_
.hash_offset = 2, .hash_offset = 2,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5228,11 +5240,15 @@ static const struct mtk_soc_data mt7623_ @@ -5231,11 +5243,15 @@ static const struct mtk_soc_data mt7623_
.hash_offset = 2, .hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.disable_pll_modes = true, .disable_pll_modes = true,
@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5247,11 +5263,15 @@ static const struct mtk_soc_data mt7629_ @@ -5250,11 +5266,15 @@ static const struct mtk_soc_data mt7629_
.required_pctl = false, .required_pctl = false,
.has_accounting = true, .has_accounting = true,
.version = 1, .version = 1,
@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5269,11 +5289,15 @@ static const struct mtk_soc_data mt7981_ @@ -5272,11 +5292,15 @@ static const struct mtk_soc_data mt7981_
.hash_offset = 4, .hash_offset = 4,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
@@ -5291,11 +5315,15 @@ static const struct mtk_soc_data mt7986_ @@ -5294,11 +5318,15 @@ static const struct mtk_soc_data mt7986_
.hash_offset = 4, .hash_offset = 4,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
@@ -5313,11 +5341,15 @@ static const struct mtk_soc_data mt7988_ @@ -5316,11 +5344,15 @@ static const struct mtk_soc_data mt7988_
.hash_offset = 4, .hash_offset = 4,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
@@ -5330,11 +5362,15 @@ static const struct mtk_soc_data rt5350_ @@ -5333,11 +5365,15 @@ static const struct mtk_soc_data rt5350_
.required_clks = MT7628_CLKS_BITMAP, .required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false, .required_pctl = false,
.version = 1, .version = 1,

4
target/linux/mediatek/patches-5.15/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
View File

@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
/* Set FE to PDMAv2 if necessary */ /* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC); val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
@@ -5295,11 +5295,11 @@ static const struct mtk_soc_data mt7981_ @@ -5298,11 +5298,11 @@ static const struct mtk_soc_data mt7981_
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
.rx = { .rx = {
@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
}, },
}; };
@@ -5321,11 +5321,11 @@ static const struct mtk_soc_data mt7986_ @@ -5324,11 +5324,11 @@ static const struct mtk_soc_data mt7986_
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
.rx = { .rx = {

270
target/linux/mediatek/patches-6.1/734-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch Normal file
View File

@ -0,0 +1,270 @@
From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
From: Daniel Golle <daniel@makrotopia.org>
Date: Wed, 24 Jan 2024 02:27:04 +0000
Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
To: Daniel Golle <daniel@makrotopia.org>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
David S. Miller <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
netdev@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org
Sync initialization and calibration routines with MediaTek's reference
driver. Improves compliance and resolves link stability issues with
CH340 IoT devices connected to MT798x built-in PHYs.
Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
1 file changed, 81 insertions(+), 66 deletions(-)
--- a/drivers/net/phy/mediatek-ge-soc.c
+++ b/drivers/net/phy/mediatek-ge-soc.c
@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy
u16 reg, val;
if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
- bias = -2;
+ bias = -1;
val = clamp_val(bias + tx_r50_cal_val, 0, 63);
@@ -707,6 +707,11 @@ restore:
static void mt798x_phy_common_finetune(struct phy_device *phydev)
{
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
+ __phy_write(phydev, 0x11, 0xc71);
+ __phy_write(phydev, 0x12, 0xc);
+ __phy_write(phydev, 0x10, 0x8fae);
+
/* EnabRandUpdTrig = 1 */
__phy_write(phydev, 0x11, 0x2f00);
__phy_write(phydev, 0x12, 0xe);
@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x83aa);
- /* TrFreeze = 0 */
+ /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
+ __phy_write(phydev, 0x11, 0x240);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x9680);
+
+ /* TrFreeze = 0 (mt7988 default) */
__phy_write(phydev, 0x11, 0x0);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9686);
+ /* SSTrKp100 = 5 */
+ /* SSTrKf100 = 6 */
+ /* SSTrKp1000Mas = 5 */
+ /* SSTrKf1000Mas = 6 */
/* SSTrKp1000Slv = 5 */
+ /* SSTrKf1000Slv = 6 */
__phy_write(phydev, 0x11, 0xbaef);
__phy_write(phydev, 0x12, 0x2e);
__phy_write(phydev, 0x10, 0x968c);
+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+}
+
+static void mt7981_phy_finetune(struct phy_device *phydev)
+{
+ u16 val[8] = { 0x01ce, 0x01c1,
+ 0x020f, 0x0202,
+ 0x03d0, 0x03c0,
+ 0x0013, 0x0005 };
+ int i, k;
+
+ /* 100M eye finetune:
+ * Keep middle level of TX MLT3 shapper as default.
+ * Only change TX MLT3 overshoot level here.
+ */
+ for (k = 0, i = 1; i < 12; i++) {
+ if (i % 3 == 0)
+ continue;
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
+ }
+
+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
+ /* ResetSyncOffset = 6 */
+ __phy_write(phydev, 0x11, 0x600);
+ __phy_write(phydev, 0x12, 0x0);
+ __phy_write(phydev, 0x10, 0x8fc0);
+
+ /* VgaDecRate = 1 */
+ __phy_write(phydev, 0x11, 0x4c2a);
+ __phy_write(phydev, 0x12, 0x3e);
+ __phy_write(phydev, 0x10, 0x8fa4);
/* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
* MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s
__phy_write(phydev, 0x10, 0x8ec0);
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
}
-static void mt7981_phy_finetune(struct phy_device *phydev)
-{
- u16 val[8] = { 0x01ce, 0x01c1,
- 0x020f, 0x0202,
- 0x03d0, 0x03c0,
- 0x0013, 0x0005 };
- int i, k;
-
- /* 100M eye finetune:
- * Keep middle level of TX MLT3 shapper as default.
- * Only change TX MLT3 overshoot level here.
- */
- for (k = 0, i = 1; i < 12; i++) {
- if (i % 3 == 0)
- continue;
- phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
- }
-
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
- __phy_write(phydev, 0x11, 0xc71);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
- /* ResetSyncOffset = 6 */
- __phy_write(phydev, 0x11, 0x600);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x8fc0);
-
- /* VgaDecRate = 1 */
- __phy_write(phydev, 0x11, 0x4c2a);
- __phy_write(phydev, 0x12, 0x3e);
- __phy_write(phydev, 0x10, 0x8fa4);
-
- /* FfeUpdGainForce = 4 */
- __phy_write(phydev, 0x11, 0x240);
- __phy_write(phydev, 0x12, 0x0);
- __phy_write(phydev, 0x10, 0x9680);
-
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-}
-
static void mt7988_phy_finetune(struct phy_device *phydev)
{
u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p
/* TCT finetune */
phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- /* Disable TX power saving */
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
- MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-
- /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
- __phy_write(phydev, 0x11, 0x671);
- __phy_write(phydev, 0x12, 0xc);
- __phy_write(phydev, 0x10, 0x8fae);
-
/* ResetSyncOffset = 5 */
__phy_write(phydev, 0x11, 0x500);
__phy_write(phydev, 0x12, 0x0);
@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p
/* VgaDecRate is 1 at default on mt7988 */
- phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+ /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
+ * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
+ */
+ __phy_write(phydev, 0x11, 0xb90a);
+ __phy_write(phydev, 0x12, 0x6f);
+ __phy_write(phydev, 0x10, 0x8f82);
+
+ /* RemAckCntLimitCtrl = 1 */
+ __phy_write(phydev, 0x11, 0xfbba);
+ __phy_write(phydev, 0x12, 0xc3);
+ __phy_write(phydev, 0x10, 0x87f8);
- phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
- /* TxClkOffset = 2 */
- __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
- FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
+
+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
+
+ /* rg_tr_lpf_cnt_val = 1023 */
+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
}
static void mt798x_phy_eee(struct phy_device *phydev)
@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de
MTK_PHY_LPI_SLV_SEND_TX_EN,
FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
- MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
- MTK_PHY_LPI_TXPCS_LOC_RCV,
- FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
+ /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
+ MTK_PHY_LPI_TXPCS_LOC_RCV);
+ /* This also fixes some IoT issues, such as CH340 */
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x9690);
- /* REG_EEE_st2TrKf1000 = 3 */
+ /* REG_EEE_st2TrKf1000 = 2 */
__phy_write(phydev, 0x11, 0x114f);
__phy_write(phydev, 0x12, 0x2);
__phy_write(phydev, 0x10, 0x969a);
@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96b8);
- /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
__phy_write(phydev, 0x11, 0x1463);
__phy_write(phydev, 0x12, 0x0);
__phy_write(phydev, 0x10, 0x96ca);
@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d
if (err)
return err;
+ /* Disable TX power saving at probing to:
+ * 1. Meet common mode compliance test criteria
+ * 2. Make sure that TX-VCM calibration works fine
+ */
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
+
return mt798x_phy_calibration(phydev);
}

18
target/linux/mediatek/patches-6.1/961-net-ethernet-mediatek-split-tx-and-rx-fields-in-mtk_.patch
View File

@ -347,7 +347,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
if (mtk_is_netsys_v3_or_greater(eth)) { if (mtk_is_netsys_v3_or_greater(eth)) {
@@ -5173,11 +5173,15 @@ static const struct mtk_soc_data mt2701_ @@ -5176,11 +5176,15 @@ static const struct mtk_soc_data mt2701_
.required_clks = MT7623_CLKS_BITMAP, .required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true, .required_pctl = true,
.version = 1, .version = 1,
@ -368,7 +368,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5193,11 +5197,15 @@ static const struct mtk_soc_data mt7621_ @@ -5196,11 +5200,15 @@ static const struct mtk_soc_data mt7621_
.offload_version = 1, .offload_version = 1,
.hash_offset = 2, .hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@ -389,7 +389,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5215,11 +5223,15 @@ static const struct mtk_soc_data mt7622_ @@ -5218,11 +5226,15 @@ static const struct mtk_soc_data mt7622_
.hash_offset = 2, .hash_offset = 2,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
@ -410,7 +410,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5236,11 +5248,15 @@ static const struct mtk_soc_data mt7623_ @@ -5239,11 +5251,15 @@ static const struct mtk_soc_data mt7623_
.hash_offset = 2, .hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.disable_pll_modes = true, .disable_pll_modes = true,
@ -431,7 +431,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5255,11 +5271,15 @@ static const struct mtk_soc_data mt7629_ @@ -5258,11 +5274,15 @@ static const struct mtk_soc_data mt7629_
.required_pctl = false, .required_pctl = false,
.has_accounting = true, .has_accounting = true,
.version = 1, .version = 1,
@ -452,7 +452,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN, .dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16, .dma_len_offset = 16,
}, },
@@ -5277,11 +5297,15 @@ static const struct mtk_soc_data mt7981_ @@ -5280,11 +5300,15 @@ static const struct mtk_soc_data mt7981_
.hash_offset = 4, .hash_offset = 4,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@ -473,7 +473,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
@@ -5299,11 +5323,15 @@ static const struct mtk_soc_data mt7986_ @@ -5302,11 +5326,15 @@ static const struct mtk_soc_data mt7986_
.hash_offset = 4, .hash_offset = 4,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
@ -494,7 +494,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
@@ -5321,11 +5349,15 @@ static const struct mtk_soc_data mt7988_ @@ -5324,11 +5352,15 @@ static const struct mtk_soc_data mt7988_
.hash_offset = 4, .hash_offset = 4,
.has_accounting = true, .has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
@ -515,7 +515,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2, .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
@@ -5338,11 +5370,15 @@ static const struct mtk_soc_data rt5350_ @@ -5341,11 +5373,15 @@ static const struct mtk_soc_data rt5350_
.required_clks = MT7628_CLKS_BITMAP, .required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false, .required_pctl = false,
.version = 1, .version = 1,

4
target/linux/mediatek/patches-6.1/962-net-ethernet-mediatek-use-QDMA-instead-of-ADMAv2-on-.patch
View File

@ -89,7 +89,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
/* Set FE to PDMAv2 if necessary */ /* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC); val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
@@ -5303,11 +5303,11 @@ static const struct mtk_soc_data mt7981_ @@ -5306,11 +5306,11 @@ static const struct mtk_soc_data mt7981_
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
.rx = { .rx = {
@ -105,7 +105,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
}, },
}; };
@@ -5329,11 +5329,11 @@ static const struct mtk_soc_data mt7986_ @@ -5332,11 +5332,11 @@ static const struct mtk_soc_data mt7986_
.dma_len_offset = 8, .dma_len_offset = 8,
}, },
.rx = { .rx = {