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ar71xx: fix AR934X clock frequency calculation

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SVN-Revision: 28973
This commit is contained in:
Gabor Juhos 2011-11-12 10:54:08 +00:00
parent 0939419e24
commit 43e993e5f5
2 changed files with 48 additions and 12 deletions
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52
target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
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@ -183,39 +183,67 @@ static void __init ar71xx_detect_sys_type(void)
static void __init ar934x_detect_sys_frequency(void) static void __init ar934x_detect_sys_frequency(void)
{ {
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
u32 cpu_pll, ddr_pll;
if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40) if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
ar71xx_ref_freq = 40 * 1000 * 1000; ar71xx_ref_freq = 40 * 1000 * 1000;
else else
ar71xx_ref_freq = 25 * 1000 * 1000; ar71xx_ref_freq = 25 * 1000 * 1000;
clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG); pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll); out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll); ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
nint = AR934X_CPU_PLL_CFG_NINT_GET(pll); nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll); frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
(postdiv + 1);
cpu_pll = nint * ar71xx_ref_freq / ref_div;
cpu_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 6));
cpu_pll /= (1 << out_div);
pll = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CONFIG);
out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll); out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll); ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
nint = AR934X_DDR_PLL_CFG_NINT_GET(pll); nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll); frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
(postdiv + 1);
postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl); ddr_pll = nint * ar71xx_ref_freq / ref_div;
ddr_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 10));
ddr_pll /= (1 << out_div);
if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) {
ar71xx_cpu_freq = ar71xx_ref_freq;
} else { } else {
ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1); postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
else
ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
} }
if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) {
ar71xx_ddr_freq = ar71xx_ref_freq;
} else {
postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
ar71xx_ddr_freq = ddr_pll / (postdiv + 1);
else
ar71xx_ddr_freq = cpu_pll / (postdiv + 1);
}
if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) {
ar71xx_ahb_freq = ar71xx_ref_freq;
} else {
postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
ar71xx_ahb_freq = ddr_pll / (postdiv + 1);
else
ar71xx_ahb_freq = cpu_pll / (postdiv + 1);
}
} }
static void __init ar91xx_detect_sys_frequency(void) static void __init ar91xx_detect_sys_frequency(void)

8
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
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@ -212,6 +212,7 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
#define AR934X_PLL_REG_CPU_CONFIG 0x00 #define AR934X_PLL_REG_CPU_CONFIG 0x00
#define AR934X_PLL_REG_DDR_CONFIG 0x04
#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8 #define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21 #define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
@ -372,6 +373,13 @@ extern enum ar71xx_soc_type ar71xx_soc;
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
extern void __iomem *ar71xx_pll_base; extern void __iomem *ar71xx_pll_base;
static inline void ar71xx_pll_wr(unsigned reg, u32 val) static inline void ar71xx_pll_wr(unsigned reg, u32 val)