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mediatek: fix mt7622-rfb1 board support
Make GPIO keys active-low. Add DSA support Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
parent
b7727a8005
commit
431b177afa
@ -13,6 +13,9 @@ mediatek_setup_interfaces()
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bananapi,bpi-r64)
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ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" wan
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;;
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mediatek,mt7622-rfb1)
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ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan
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;;
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*)
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ucidef_add_switch "switch0" \
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"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"
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@ -63,17 +63,15 @@
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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@@ -14,8 +13,8 @@
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@@ -14,7 +13,7 @@
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#include "mt6380.dtsi"
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/ {
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- model = "MediaTek MT7622 RFB1 board";
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- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
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+ model = "MT7622_MT7531 RFB";
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+ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
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compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
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aliases {
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serial0 = &uart0;
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@@ -23,7 +22,7 @@
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chosen {
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@ -83,7 +81,7 @@
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};
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cpus {
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@@ -40,23 +39,45 @@
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@@ -40,23 +39,38 @@
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gpio-keys {
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compatible = "gpio-keys";
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@ -93,24 +91,17 @@
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label = "factory";
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linux,code = <BTN_0>;
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- gpios = <&pio 0 0>;
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+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
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+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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- gpios = <&pio 102 0>;
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+ gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
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+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ gsw: gsw@0 {
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+ compatible = "mediatek,mt753x";
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+ mediatek,ethsys = <ðsys>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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@ -133,7 +124,7 @@
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};
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reg_1p8v: regulator-1p8v {
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@@ -101,27 +122,67 @@
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@@ -101,23 +115,82 @@
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};
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ð {
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@ -169,48 +160,61 @@
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+ mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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-
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- phy5: ethernet-phy@5 {
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- reg = <5>;
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- phy-mode = "sgmii";
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- };
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+ switch@0 {
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+ compatible = "mediatek,mt7531";
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+ reg = <0>;
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+ reset-gpios = <&pio 54 0>;
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "lan1";
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "lan2";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "lan3";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "lan4";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "wan";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ label = "cpu";
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+ ethernet = <&gmac0>;
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+ phy-mode = "2500base-x";
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+
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ pause;
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+ };
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+ };
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+ };
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};
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};
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};
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+&gsw {
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+ mediatek,mdio = <&mdio>;
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+ mediatek,portmap = "llllw";
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+ mediatek,mdio_master_pinmux = <0>;
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+ reset-gpios = <&pio 54 0>;
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+ interrupt-parent = <&pio>;
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+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "okay";
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+
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+ port5: port@5 {
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+ compatible = "mediatek,mt753x-port";
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+ reg = <5>;
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+ phy-mode = "rgmii";
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+ };
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+
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+ port6: port@6 {
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+ compatible = "mediatek,mt753x-port";
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+ reg = <6>;
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+ phy-mode = "sgmii";
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+ fixed-link {
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+ speed = <2500>;
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+ full-duplex;
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+ };
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+ };
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+};
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+
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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@@ -185,15 +246,28 @@
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@@ -185,15 +258,28 @@
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&pcie {
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pinctrl-names = "default";
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@ -240,7 +244,7 @@
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/* eMMC is shared pin with parallel NAND */
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emmc_pins_default: emmc-pins-default {
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mux {
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@@ -460,11 +534,11 @@
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@@ -460,11 +546,11 @@
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};
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&sata {
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@ -22,7 +22,7 @@
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"mediatek,mt8173-nor";
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -108,7 +108,7 @@
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@@ -101,7 +101,7 @@
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};
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&bch {
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@ -31,7 +31,7 @@
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};
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&btif {
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@@ -541,6 +541,62 @@
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@@ -553,6 +553,62 @@
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status = "disable";
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};
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@ -20,7 +20,7 @@
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"syscon";
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -579,7 +579,7 @@
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@@ -591,7 +591,7 @@
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reg = <0x140000 0x0080000>;
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};
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@ -29,7 +29,7 @@
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label = "Factory";
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reg = <0x1c0000 0x0040000>;
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};
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@@ -636,3 +636,8 @@
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@@ -648,3 +648,8 @@
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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@ -382,7 +382,8 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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};
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};
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+ };
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+
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- pcie1: pcie@1,0 {
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+ pcie1: pcie@1a145000 {
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+ compatible = "mediatek,mt7622-pcie";
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+ device_type = "pci";
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@ -407,8 +408,7 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>;
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+ status = "disabled";
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- pcie1: pcie@1,0 {
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+
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+ slot1: pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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@ -389,7 +389,7 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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<0 0 0 2 &pcie_intc1 1>,
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -244,18 +244,16 @@
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@@ -256,18 +256,16 @@
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};
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};
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