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mediatek: fix mt7622-rfb1 board support

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Make GPIO keys active-low.
Add DSA support

Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Felix Fietkau 2020-07-20 18:18:50 +02:00
parent b7727a8005
commit 431b177afa
6 changed files with 68 additions and 61 deletions
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3
target/linux/mediatek/mt7622/base-files/etc/board.d/02_network
View File

@ -13,6 +13,9 @@ mediatek_setup_interfaces()
bananapi,bpi-r64) bananapi,bpi-r64)
ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" wan ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" wan
;; ;;
mediatek,mt7622-rfb1)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" wan
;;
*) *)
ucidef_add_switch "switch0" \ ucidef_add_switch "switch0" \
"0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1" "0:lan" "1:lan" "2:lan" "3:lan" "4:wan" "6u@eth0" "5u@eth1"

110
target/linux/mediatek/patches-5.4/0005-dts-mt7622-add-gsw.patch
View File

@ -63,17 +63,15 @@
* *
* SPDX-License-Identifier: (GPL-2.0 OR MIT) * SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/ */
@@ -14,8 +13,8 @@ @@ -14,7 +13,7 @@
#include "mt6380.dtsi" #include "mt6380.dtsi"
/ { / {
- model = "MediaTek MT7622 RFB1 board"; - model = "MediaTek MT7622 RFB1 board";
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
+ model = "MT7622_MT7531 RFB"; + model = "MT7622_MT7531 RFB";
+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
aliases { aliases {
serial0 = &uart0;
@@ -23,7 +22,7 @@ @@ -23,7 +22,7 @@
chosen { chosen {
@ -83,7 +81,7 @@
}; };
cpus { cpus {
@@ -40,23 +39,45 @@ @@ -40,23 +39,38 @@
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
@ -93,24 +91,17 @@
label = "factory"; label = "factory";
linux,code = <BTN_0>; linux,code = <BTN_0>;
- gpios = <&pio 0 0>; - gpios = <&pio 0 0>;
+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>; + gpios = <&pio 0 GPIO_ACTIVE_LOW>;
}; };
wps { wps {
label = "wps"; label = "wps";
linux,code = <KEY_WPS_BUTTON>; linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 0>; - gpios = <&pio 102 0>;
+ gpios = <&pio 102 GPIO_ACTIVE_HIGH>; + gpios = <&pio 102 GPIO_ACTIVE_LOW>;
+ }; + };
+ }; + };
+ +
+ gsw: gsw@0 {
+ compatible = "mediatek,mt753x";
+ mediatek,ethsys = <&ethsys>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ leds { + leds {
+ compatible = "gpio-leds"; + compatible = "gpio-leds";
+ +
@ -133,7 +124,7 @@
}; };
reg_1p8v: regulator-1p8v { reg_1p8v: regulator-1p8v {
@@ -101,27 +122,67 @@ @@ -101,23 +115,82 @@
}; };
&eth { &eth {
@ -169,48 +160,61 @@
+ mdio: mdio-bus { + mdio: mdio-bus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
-
- phy5: ethernet-phy@5 { - phy5: ethernet-phy@5 {
- reg = <5>; - reg = <5>;
- phy-mode = "sgmii"; - phy-mode = "sgmii";
- }; + switch@0 {
+ compatible = "mediatek,mt7531";
+ reg = <0>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
};
}; };
}; };
@@ -185,15 +258,28 @@
+&gsw {
+ mediatek,mdio = <&mdio>;
+ mediatek,portmap = "llllw";
+ mediatek,mdio_master_pinmux = <0>;
+ reset-gpios = <&pio 54 0>;
+ interrupt-parent = <&pio>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ status = "okay";
+
+ port5: port@5 {
+ compatible = "mediatek,mt753x-port";
+ reg = <5>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+
+ port6: port@6 {
+ compatible = "mediatek,mt753x-port";
+ reg = <6>;
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ };
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -185,15 +246,28 @@
&pcie { &pcie {
pinctrl-names = "default"; pinctrl-names = "default";
@ -240,7 +244,7 @@
/* eMMC is shared pin with parallel NAND */ /* eMMC is shared pin with parallel NAND */
emmc_pins_default: emmc-pins-default { emmc_pins_default: emmc-pins-default {
mux { mux {
@@ -460,11 +534,11 @@ @@ -460,11 +546,11 @@
}; };
&sata { &sata {

4
target/linux/mediatek/patches-5.4/0308-dts-mt7622-add-snand-support.patch
View File

@ -22,7 +22,7 @@
"mediatek,mt8173-nor"; "mediatek,mt8173-nor";
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -108,7 +108,7 @@ @@ -101,7 +101,7 @@
}; };
&bch { &bch {
@ -31,7 +31,7 @@
}; };
&btif { &btif {
@@ -541,6 +541,62 @@ @@ -553,6 +553,62 @@
status = "disable"; status = "disable";
}; };

4
target/linux/mediatek/patches-5.4/0310-dts-add-wmac-support-for-mt7622-rfb1.patch
View File

@ -20,7 +20,7 @@
"syscon"; "syscon";
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -579,7 +579,7 @@ @@ -591,7 +591,7 @@
reg = <0x140000 0x0080000>; reg = <0x140000 0x0080000>;
}; };
@ -29,7 +29,7 @@
label = "Factory"; label = "Factory";
reg = <0x1c0000 0x0040000>; reg = <0x1c0000 0x0040000>;
}; };
@@ -636,3 +636,8 @@ @@ -648,3 +648,8 @@
pinctrl-0 = <&watchdog_pins>; pinctrl-0 = <&watchdog_pins>;
status = "okay"; status = "okay";
}; };

6
target/linux/mediatek/patches-5.4/0991-dt-bindings-PCI-Mediatek-Update-PCIe-binding.patch
View File

@ -382,7 +382,8 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
}; };
}; };
+ }; + };
+
- pcie1: pcie@1,0 {
+ pcie1: pcie@1a145000 { + pcie1: pcie@1a145000 {
+ compatible = "mediatek,mt7622-pcie"; + compatible = "mediatek,mt7622-pcie";
+ device_type = "pci"; + device_type = "pci";
@ -407,8 +408,7 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
+ bus-range = <0x00 0xff>; + bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>; + ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>;
+ status = "disabled"; + status = "disabled";
+
- pcie1: pcie@1,0 {
+ slot1: pcie@1,0 { + slot1: pcie@1,0 {
reg = <0x0800 0 0 0 0>; reg = <0x0800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;

2
target/linux/mediatek/patches-5.4/0993-arm64-dts-mediatek-Split-PCIe-node-for-MT2712-MT7622.patch
View File

@ -389,7 +389,7 @@ Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
<0 0 0 2 &pcie_intc1 1>, <0 0 0 2 &pcie_intc1 1>,
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -244,18 +244,16 @@ @@ -256,18 +256,16 @@
}; };
}; };