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AR7240 requires different IRQ unmasking code
SVN-Revision: 16734
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daaf02e416
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@ -297,6 +297,22 @@ static void ar71xx_misc_irq_unmask(unsigned int irq)
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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}
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}
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static void ar724x_misc_irq_unmask(unsigned int irq)
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
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/* flush write */
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ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
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}
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static void ar71xx_misc_irq_mask(unsigned int irq)
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static void ar71xx_misc_irq_mask(unsigned int irq)
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{
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{
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irq -= AR71XX_MISC_IRQ_BASE;
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irq -= AR71XX_MISC_IRQ_BASE;
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@ -326,6 +342,9 @@ static void __init ar71xx_misc_irq_init(void)
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
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ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
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if (ar71xx_soc == AR71XX_SOC_AR7240)
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ar71xx_misc_irq_chip.unmask = ar724x_misc_irq_unmask;
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for (i = AR71XX_MISC_IRQ_BASE;
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for (i = AR71XX_MISC_IRQ_BASE;
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
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i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].status = IRQ_DISABLED;
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