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Add uboot for xburst package
SVN-Revision: 20832
This commit is contained in:
parent
0946764732
commit
393541dce8
package/uboot-xburst
Makefile
files
board
n516
nanonote
sakc
cpu/mips
jz4740.cjz4740_nand.cjz_lcd.cjz_lcd.hjz_mmc.cjz_mmc.c.origjz_mmc.hjz_serial.cmmc_protocol.hnanonote_gpm940b0.cnanonote_gpm940b0.husb_boot.S
include
nand_spl
patches
102
package/uboot-xburst/Makefile
Normal file
102
package/uboot-xburst/Makefile
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@ -0,0 +1,102 @@
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#
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# Copyright (C) 2008 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_NAME:=u-boot
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PKG_VERSION:=2009.11
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PKG_RELEASE:=1
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PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
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PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
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PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot
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PKG_MD5SUM:=
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PKG_TARGETS:=bin
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include $(INCLUDE_DIR)/package.mk
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define uboot/Default
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TITLE:=
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CONFIG:=
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IMAGE:=
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endef
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define uboot/qi_lb60
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TITLE:=U-boot for the qi_lb60 board
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endef
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define uboot/avt2
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TITLE:=U-boot for the avt2 board
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endef
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define uboot/sakc
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TITLE:=U-boot for the sakc board
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endef
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define uboot/n516
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TITLE:=U-boot for the N516 e-book reader
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CONFIG:=n516_nand
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endef
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UBOOTS:=qi_lb60 n516 avt2 sakc
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define Package/uboot/template
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define Package/uboot-xburst-$(1)
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SECTION:=boot
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CATEGORY:=Boot Loaders
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DEPENDS:=@TARGET_xburst
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TITLE:=$(2)
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URL:=http://www.denx.de/wiki/UBoot/WebHome
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VARIANT:=$(1)
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endef
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endef
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define BuildUbootPackage
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$(eval $(uboot/Default))
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$(eval $(uboot/$(1)))
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$(call Package/uboot/template,$(1),$(TITLE))
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endef
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ifdef BUILD_VARIANT
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$(eval $(call uboot/$(BUILD_VARIANT)))
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UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
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UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),openwrt-$(BOARD)-$(BUILD_BARIANT)-u-boot.bin)
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endif
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define Build/Prepare
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$(call Build/Prepare/Default)
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$(CP) ./files/* $(PKG_BUILD_DIR)
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find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf
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endef
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define Build/Configure
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$(MAKE) -C $(PKG_BUILD_DIR) \
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$(UBOOT_CONFIG)_config
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endef
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define Build/Compile
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$(MAKE) -C $(PKG_BUILD_DIR) \
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CROSS_COMPILE=$(TARGET_CROSS)
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endef
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define Package/uboot/install/template
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define Package/uboot-xburst-$(1)/install
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$(INSTALL_DIR) $$(1)
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$(CP) $(PKG_BUILD_DIR)/u-boot-nand.bin $(BIN_DIR)/$(2)
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endef
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endef
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$(foreach u,$(UBOOTS), \
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$(eval $(call Package/uboot/install/template,$(u),openwrt-$(BOARD)-$(u)-u-boot.bin)) \
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)
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$(foreach u,$(UBOOTS), \
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$(eval $(call BuildUbootPackage,$(u))) \
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$(eval $(call BuildPackage,uboot-xburst-$(u))) \
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)
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40
package/uboot-xburst/files/board/n516/Makefile
Normal file
40
package/uboot-xburst/files/board/n516/Makefile
Normal file
@ -0,0 +1,40 @@
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#
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# (C) Copyright 2006
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# Ingenic Semiconductor, <jlwei@ingenic.cn>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o flash.o
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OBJS = $(addprefix $(obj),$(COBJS))
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SOBJS =
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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#########################################################################
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$(obj).depend: Makefile $(SOBJS:.o=.S) $(COBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(COBJS:.o=.c) > $@
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sinclude $(obj).depend
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#########################################################################
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33
package/uboot-xburst/files/board/n516/config.mk
Normal file
33
package/uboot-xburst/files/board/n516/config.mk
Normal file
@ -0,0 +1,33 @@
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#
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# (C) Copyright 2006
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# Ingenic Semiconductor, <jlwei@ingenic.cn>
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Hanvon n516 e-book, MIPS32 core
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#
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sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
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ifndef TEXT_BASE
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# ROM version
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TEXT_BASE = 0x88000000
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# RAM version
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#TEXT_BASE = 0x80100000
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endif
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50
package/uboot-xburst/files/board/n516/flash.c
Normal file
50
package/uboot-xburst/files/board/n516/flash.c
Normal file
@ -0,0 +1,50 @@
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/*
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* (C) Copyright 2006
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* Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*-----------------------------------------------------------------------
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* flash_init()
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*
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* sets up flash_info and returns size of FLASH (bytes)
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*/
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unsigned long flash_init (void)
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{
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return (0);
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}
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int flash_erase (flash_info_t * info, int s_first, int s_last)
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{
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printf ("flash_erase not implemented\n");
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return 0;
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}
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void flash_print_info (flash_info_t * info)
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{
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printf ("flash_print_info not implemented\n");
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}
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int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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printf ("write_buff not implemented\n");
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return (-1);
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}
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126
package/uboot-xburst/files/board/n516/n516.c
Normal file
126
package/uboot-xburst/files/board/n516/n516.c
Normal file
@ -0,0 +1,126 @@
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/*
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* (C) Copyright 2006
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* Ingenic Semiconductor, <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as
|
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/mipsregs.h>
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#include <asm/jz4740.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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void _machine_restart(void)
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{
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__wdt_select_extalclk();
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__wdt_select_clk_div64();
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__wdt_set_data(100);
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__wdt_set_count(0);
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__tcu_start_wdt_clock();
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__wdt_start();
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while(1);
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}
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static void gpio_init(void)
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{
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REG_GPIO_PXPES(0) = 0xffffffff;
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REG_GPIO_PXPES(1) = 0xffffffff;
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REG_GPIO_PXPES(2) = 0xffffffff;
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REG_GPIO_PXPES(3) = 0xffffffff;
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/*
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* Initialize NAND Flash Pins
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*/
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__gpio_as_nand();
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/*
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* Initialize SDRAM pins
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*/
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__gpio_as_sdram_32bit();
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/*
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* Initialize UART0 pins
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*/
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__gpio_as_uart0();
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/*
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* Initialize MSC pins
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*/
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__gpio_as_msc();
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/*
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* Initialize LCD pins
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*/
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__gpio_as_lcd_16bit();
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/*
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* Initialize Other pins
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*/
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__gpio_as_output(GPIO_SD_VCC_EN_N);
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__gpio_clear_pin(GPIO_SD_VCC_EN_N);
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__gpio_as_input(GPIO_SD_CD_N);
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__gpio_disable_pull(GPIO_SD_CD_N);
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__gpio_as_output(GPIO_DISP_OFF_N);
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__gpio_as_output(GPIO_LED_EN);
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__gpio_set_pin(GPIO_LED_EN);
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__gpio_as_input(127);
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}
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static void cpm_init(void)
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{
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__cpm_stop_ipu();
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__cpm_stop_cim();
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__cpm_stop_i2c();
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__cpm_stop_ssi();
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__cpm_stop_uart1();
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__cpm_stop_sadc();
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__cpm_stop_uhc();
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__cpm_stop_udc();
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__cpm_stop_aic1();
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__cpm_stop_aic2();
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__cpm_suspend_udcphy();
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__cpm_suspend_usbphy();
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}
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//----------------------------------------------------------------------
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// board early init routine
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void board_early_init(void)
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{
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gpio_init();
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cpm_init();
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}
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//----------------------------------------------------------------------
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// U-Boot common routines
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int checkboard (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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printf("Board: Hanvon n516 e-book (CPU Speed %d MHz)\n",
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gd->cpu_clk/1000000);
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return 0; /* success */
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}
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63
package/uboot-xburst/files/board/n516/u-boot-nand.lds
Normal file
63
package/uboot-xburst/files/board/n516/u-boot-nand.lds
Normal file
@ -0,0 +1,63 @@
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/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
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|
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OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
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OUTPUT_ARCH(mips)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
|
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. = ALIGN(4);
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||||
.text :
|
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{
|
||||
*(.text)
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}
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. = ALIGN(4);
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.rodata : { *(.rodata) }
|
||||
|
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. = ALIGN(4);
|
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.data : { *(.data) }
|
||||
|
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. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
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_gp = ALIGN(16);
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||||
|
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__got_start = .;
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.got : { *(.got) }
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||||
__got_end = .;
|
||||
|
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.sdata : { *(.sdata) }
|
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|
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__u_boot_cmd_start = .;
|
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.u_boot_cmd : { *(.u_boot_cmd) }
|
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__u_boot_cmd_end = .;
|
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|
||||
uboot_end_data = .;
|
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num_got_entries = (__got_end - __got_start) >> 2;
|
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. = ALIGN(4);
|
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.sbss : { *(.sbss) }
|
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.bss : { *(.bss) }
|
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uboot_end = .;
|
||||
}
|
63
package/uboot-xburst/files/board/n516/u-boot.lds
Normal file
63
package/uboot-xburst/files/board/n516/u-boot.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
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|
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OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
38
package/uboot-xburst/files/board/nanonote/Makefile
Normal file
38
package/uboot-xburst/files/board/nanonote/Makefile
Normal file
@ -0,0 +1,38 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o
|
||||
SOBJS =
|
||||
|
||||
$(LIB): .depend $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
31
package/uboot-xburst/files/board/nanonote/config.mk
Normal file
31
package/uboot-xburst/files/board/nanonote/config.mk
Normal file
@ -0,0 +1,31 @@
|
||||
#
|
||||
# (C) Copyright 2006 Qi Hardware, Inc.
|
||||
# Author: Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
|
||||
#
|
||||
|
||||
ifndef TEXT_BASE
|
||||
# ROM version
|
||||
# TEXT_BASE = 0x88000000
|
||||
|
||||
# RAM version
|
||||
TEXT_BASE = 0x80100000
|
||||
endif
|
123
package/uboot-xburst/files/board/nanonote/nanonote.c
Normal file
123
package/uboot-xburst/files/board/nanonote/nanonote.c
Normal file
@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 3 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
/*
|
||||
* Initialize NAND Flash Pins
|
||||
*/
|
||||
__gpio_as_nand();
|
||||
|
||||
/*
|
||||
* Initialize SDRAM pins
|
||||
*/
|
||||
__gpio_as_sdram_32bit();
|
||||
|
||||
/*
|
||||
* Initialize LCD pins
|
||||
*/
|
||||
__gpio_as_lcd_18bit();
|
||||
|
||||
/*
|
||||
* Initialize MSC pins
|
||||
*/
|
||||
__gpio_as_msc();
|
||||
|
||||
/*
|
||||
* Initialize Other pins
|
||||
*/
|
||||
unsigned int i;
|
||||
for (i = 0; i < 7; i++){
|
||||
__gpio_as_input(GPIO_KEYIN_BASE + i);
|
||||
__gpio_enable_pull(GPIO_KEYIN_BASE + i);
|
||||
}
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
__gpio_as_output(GPIO_KEYOUT_BASE + i);
|
||||
__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize UART0 pins, in Ben NanoNote uart0 and keyin8 use the
|
||||
* same gpio, init the gpio as uart0 cause a keyboard bug. so for
|
||||
* end user we disable the uart0
|
||||
*/
|
||||
if (__gpio_get_pin(GPIO_KEYIN_BASE + 2) == 0){
|
||||
/* if pressed [S] */
|
||||
printf("[S] pressed, enable UART0\n");
|
||||
gd->boot_option = 5;
|
||||
__gpio_as_uart0();
|
||||
} else {
|
||||
printf("[S] not pressed, disable UART0\n");
|
||||
__gpio_as_input(GPIO_KEYIN_8);
|
||||
__gpio_enable_pull(GPIO_KEYIN_8);
|
||||
}
|
||||
|
||||
__gpio_as_output(GPIO_AUDIO_POP);
|
||||
__gpio_set_pin(GPIO_AUDIO_POP);
|
||||
|
||||
__gpio_as_output(GPIO_LCD_CS);
|
||||
__gpio_clear_pin(GPIO_LCD_CS);
|
||||
|
||||
__gpio_as_output(GPIO_AMP_EN);
|
||||
__gpio_clear_pin(GPIO_AMP_EN);
|
||||
|
||||
__gpio_as_output(GPIO_SDPW_EN);
|
||||
__gpio_disable_pull(GPIO_SDPW_EN);
|
||||
__gpio_clear_pin(GPIO_SDPW_EN);
|
||||
|
||||
__gpio_as_input(GPIO_SD_DETECT);
|
||||
__gpio_disable_pull(GPIO_SD_DETECT);
|
||||
|
||||
__gpio_as_input(GPIO_USB_DETECT);
|
||||
__gpio_enable_pull(GPIO_USB_DETECT);
|
||||
|
||||
if (__gpio_get_pin(GPIO_KEYIN_BASE + 3) == 0) {
|
||||
printf("[M] pressed, boot from sd card\n");
|
||||
gd->boot_option = 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void cpm_init(void)
|
||||
{
|
||||
__cpm_stop_ipu();
|
||||
__cpm_stop_cim();
|
||||
__cpm_stop_i2c();
|
||||
__cpm_stop_ssi();
|
||||
__cpm_stop_uart1();
|
||||
__cpm_stop_sadc();
|
||||
__cpm_stop_uhc();
|
||||
__cpm_stop_udc();
|
||||
__cpm_stop_aic1();
|
||||
/* __cpm_stop_aic2();*/
|
||||
}
|
||||
|
||||
void board_early_init(void)
|
||||
{
|
||||
gpio_init();
|
||||
cpm_init();
|
||||
}
|
||||
|
||||
/* U-Boot common routines */
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
|
||||
printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %d MHz)\n",
|
||||
gd->cpu_clk/1000000);
|
||||
|
||||
return 0; /* success */
|
||||
}
|
63
package/uboot-xburst/files/board/nanonote/u-boot-nand.lds
Normal file
63
package/uboot-xburst/files/board/nanonote/u-boot-nand.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
63
package/uboot-xburst/files/board/nanonote/u-boot.lds
Normal file
63
package/uboot-xburst/files/board/nanonote/u-boot.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
38
package/uboot-xburst/files/board/sakc/Makefile
Normal file
38
package/uboot-xburst/files/board/sakc/Makefile
Normal file
@ -0,0 +1,38 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o
|
||||
SOBJS =
|
||||
|
||||
$(LIB): .depend $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend
|
||||
|
||||
#########################################################################
|
31
package/uboot-xburst/files/board/sakc/config.mk
Normal file
31
package/uboot-xburst/files/board/sakc/config.mk
Normal file
@ -0,0 +1,31 @@
|
||||
#
|
||||
# (C) Copyright 2006 Qi Hardware, Inc.
|
||||
# Author: Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# SAKC Board
|
||||
#
|
||||
|
||||
ifndef TEXT_BASE
|
||||
# ROM version
|
||||
# TEXT_BASE = 0x88000000
|
||||
|
||||
# RAM version
|
||||
TEXT_BASE = 0x80100000
|
||||
endif
|
94
package/uboot-xburst/files/board/sakc/sakc.c
Normal file
94
package/uboot-xburst/files/board/sakc/sakc.c
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 3 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
/*
|
||||
* Initialize NAND Flash Pins
|
||||
*/
|
||||
__gpio_as_nand();
|
||||
|
||||
/*
|
||||
* Initialize SDRAM pins
|
||||
*/
|
||||
__gpio_as_sdram_16bit_4725();
|
||||
|
||||
/*
|
||||
* Initialize UART0 pins
|
||||
*/
|
||||
__gpio_as_uart0();
|
||||
|
||||
/*
|
||||
* Initialize LCD pins
|
||||
*/
|
||||
__gpio_as_lcd_18bit();
|
||||
|
||||
/*
|
||||
* Initialize MSC pins
|
||||
*/
|
||||
__gpio_as_msc();
|
||||
|
||||
/*
|
||||
* Initialize SSI pins
|
||||
*/
|
||||
__gpio_as_ssi();
|
||||
|
||||
/*
|
||||
* Initialize I2C pins
|
||||
*/
|
||||
__gpio_as_i2c();
|
||||
|
||||
/*
|
||||
* Initialize MSC pins
|
||||
*/
|
||||
__gpio_as_msc();
|
||||
|
||||
/*
|
||||
* Initialize Other pins
|
||||
*/
|
||||
__gpio_as_input(GPIO_SD_DETECT);
|
||||
__gpio_disable_pull(GPIO_SD_DETECT);
|
||||
}
|
||||
/* TODO SAKC
|
||||
static void cpm_init(void)
|
||||
{
|
||||
__cpm_stop_ipu();
|
||||
__cpm_stop_cim();
|
||||
__cpm_stop_i2c();
|
||||
__cpm_stop_ssi();
|
||||
__cpm_stop_uart1();
|
||||
__cpm_stop_sadc();
|
||||
__cpm_stop_uhc();
|
||||
__cpm_stop_aic1();
|
||||
__cpm_stop_aic2();
|
||||
}*/
|
||||
|
||||
void board_early_init(void)
|
||||
{
|
||||
gpio_init();
|
||||
//cpm_init(); //TODO SAKC
|
||||
}
|
||||
|
||||
/* U-Boot common routines */
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
|
||||
printf("Board: SAKC (Ingenic XBurst Jz4725 SoC, Speed %d MHz)\n",
|
||||
gd->cpu_clk/1000000);
|
||||
|
||||
return 0; /* success */
|
||||
}
|
63
package/uboot-xburst/files/board/sakc/u-boot-nand.lds
Normal file
63
package/uboot-xburst/files/board/sakc/u-boot-nand.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
63
package/uboot-xburst/files/board/sakc/u-boot.lds
Normal file
63
package/uboot-xburst/files/board/sakc/u-boot.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
559
package/uboot-xburst/files/cpu/mips/jz4740.c
Normal file
559
package/uboot-xburst/files/cpu/mips/jz4740.c
Normal file
@ -0,0 +1,559 @@
|
||||
/*
|
||||
* Jz4740 common routines
|
||||
*
|
||||
* Copyright (c) 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifdef CONFIG_JZ4740
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
extern void board_early_init(void);
|
||||
|
||||
/* PLL output clock = EXTAL * NF / (NR * NO)
|
||||
*
|
||||
* NF = FD + 2, NR = RD + 2
|
||||
* NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
|
||||
*/
|
||||
void pll_init(void)
|
||||
{
|
||||
register unsigned int cfcr, plcr1;
|
||||
int n2FR[33] = {
|
||||
0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
|
||||
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
|
||||
9
|
||||
};
|
||||
int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
|
||||
int nf, pllout2;
|
||||
|
||||
cfcr = CPM_CPCCR_CLKOEN |
|
||||
CPM_CPCCR_PCS |
|
||||
(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
|
||||
(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
|
||||
(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
|
||||
(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
|
||||
(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
|
||||
|
||||
pllout2 = (cfcr & CPM_CPCCR_PCS) ? CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
|
||||
|
||||
/* Init USB Host clock, pllout2 must be n*48MHz */
|
||||
REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
|
||||
|
||||
nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
|
||||
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
|
||||
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
|
||||
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
|
||||
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
|
||||
CPM_CPPCR_PLLEN; /* enable PLL */
|
||||
|
||||
/* init PLL */
|
||||
REG_CPM_CPCCR = cfcr;
|
||||
REG_CPM_CPPCR = plcr1;
|
||||
}
|
||||
|
||||
void pll_add_test(int new_freq)
|
||||
{
|
||||
register unsigned int cfcr, plcr1;
|
||||
int n2FR[33] = {
|
||||
0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
|
||||
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
|
||||
9
|
||||
};
|
||||
int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:M:L */
|
||||
int nf, pllout2;
|
||||
|
||||
cfcr = CPM_CPCCR_CLKOEN |
|
||||
(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
|
||||
(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
|
||||
(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
|
||||
(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
|
||||
(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
|
||||
|
||||
pllout2 = (cfcr & CPM_CPCCR_PCS) ? new_freq : (new_freq / 2);
|
||||
|
||||
/* Init UHC clock */
|
||||
REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
|
||||
|
||||
/* nf = new_freq * 2 / CONFIG_SYS_EXTAL; */
|
||||
nf = new_freq / 1000000; /* step length is 1M */
|
||||
plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
|
||||
(10 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
|
||||
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
|
||||
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
|
||||
CPM_CPPCR_PLLEN; /* enable PLL */
|
||||
|
||||
/* init PLL */
|
||||
REG_CPM_CPCCR = cfcr;
|
||||
REG_CPM_CPPCR = plcr1;
|
||||
}
|
||||
|
||||
void calc_clocks_add_test(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
unsigned int pllout;
|
||||
unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
pllout = __cpm_get_pllout();
|
||||
|
||||
gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
|
||||
gd->sys_clk = pllout / div[__cpm_get_hdiv()];
|
||||
gd->per_clk = pllout / div[__cpm_get_pdiv()];
|
||||
gd->mem_clk = pllout / div[__cpm_get_mdiv()];
|
||||
gd->dev_clk = CONFIG_SYS_EXTAL;
|
||||
}
|
||||
|
||||
void sdram_add_test(int new_freq)
|
||||
{
|
||||
register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
|
||||
|
||||
unsigned int cas_latency_sdmr[2] = {
|
||||
EMC_SDMR_CAS_2,
|
||||
EMC_SDMR_CAS_3,
|
||||
};
|
||||
|
||||
unsigned int cas_latency_dmcr[2] = {
|
||||
1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
|
||||
2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
|
||||
};
|
||||
|
||||
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
cpu_clk = new_freq;
|
||||
mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
|
||||
|
||||
REG_EMC_RTCSR = EMC_RTCSR_CKS_DISABLE;
|
||||
REG_EMC_RTCOR = 0;
|
||||
REG_EMC_RTCNT = 0;
|
||||
|
||||
/* Basic DMCR register value. */
|
||||
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
|
||||
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
|
||||
(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
|
||||
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
|
||||
EMC_DMCR_EPIN |
|
||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* SDRAM timimg parameters */
|
||||
ns = 1000000000 / mem_clk;
|
||||
|
||||
#if 0
|
||||
tmp = SDRAM_TRAS/ns;
|
||||
if (tmp < 4) tmp = 4;
|
||||
if (tmp > 11) tmp = 11;
|
||||
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
|
||||
|
||||
tmp = SDRAM_RCD/ns;
|
||||
if (tmp > 3) tmp = 3;
|
||||
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
|
||||
|
||||
tmp = SDRAM_TPC/ns;
|
||||
if (tmp > 7) tmp = 7;
|
||||
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
|
||||
|
||||
tmp = SDRAM_TRWL/ns;
|
||||
if (tmp > 3) tmp = 3;
|
||||
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
|
||||
|
||||
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
|
||||
if (tmp > 14) tmp = 14;
|
||||
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
|
||||
#else
|
||||
dmcr |= 0xfffc;
|
||||
#endif
|
||||
|
||||
/* First, precharge phase */
|
||||
REG_EMC_DMCR = dmcr;
|
||||
|
||||
/* Set refresh registers */
|
||||
tmp = SDRAM_TREF/ns;
|
||||
tmp = tmp/64 + 1;
|
||||
if (tmp > 0xff) tmp = 0xff;
|
||||
|
||||
REG_EMC_RTCOR = tmp;
|
||||
REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
|
||||
|
||||
/* SDRAM mode values */
|
||||
sdmode = EMC_SDMR_BT_SEQ |
|
||||
EMC_SDMR_OM_NORMAL |
|
||||
EMC_SDMR_BL_4 |
|
||||
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* precharge all chip-selects */
|
||||
REG8(EMC_SDMR0|sdmode) = 0;
|
||||
|
||||
/* wait for precharge, > 200us */
|
||||
tmp = (cpu_clk / 1000000) * 200;
|
||||
while (tmp--);
|
||||
|
||||
/* enable refresh and set SDRAM mode */
|
||||
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
|
||||
|
||||
/* write sdram mode register for each chip-select */
|
||||
REG8(EMC_SDMR0|sdmode) = 0;
|
||||
|
||||
/* everything is ok now */
|
||||
}
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
|
||||
|
||||
unsigned int cas_latency_sdmr[2] = {
|
||||
EMC_SDMR_CAS_2,
|
||||
EMC_SDMR_CAS_3,
|
||||
};
|
||||
|
||||
unsigned int cas_latency_dmcr[2] = {
|
||||
1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
|
||||
2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
|
||||
};
|
||||
|
||||
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
cpu_clk = CONFIG_SYS_CPU_SPEED;
|
||||
mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
|
||||
|
||||
REG_EMC_BCR = 0; /* Disable bus release */
|
||||
REG_EMC_RTCSR = 0; /* Disable clock for counting */
|
||||
|
||||
/* Fault DMCR value for mode register setting*/
|
||||
#define SDRAM_ROW0 11
|
||||
#define SDRAM_COL0 8
|
||||
#define SDRAM_BANK40 0
|
||||
|
||||
dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
|
||||
((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
|
||||
(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
|
||||
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
|
||||
EMC_DMCR_EPIN |
|
||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* Basic DMCR value */
|
||||
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
|
||||
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
|
||||
(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
|
||||
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
|
||||
EMC_DMCR_EPIN |
|
||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* SDRAM timimg */
|
||||
ns = 1000000000 / mem_clk;
|
||||
tmp = SDRAM_TRAS/ns;
|
||||
if (tmp < 4) tmp = 4;
|
||||
if (tmp > 11) tmp = 11;
|
||||
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
|
||||
tmp = SDRAM_RCD/ns;
|
||||
if (tmp > 3) tmp = 3;
|
||||
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
|
||||
tmp = SDRAM_TPC/ns;
|
||||
if (tmp > 7) tmp = 7;
|
||||
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
|
||||
tmp = SDRAM_TRWL/ns;
|
||||
if (tmp > 3) tmp = 3;
|
||||
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
|
||||
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
|
||||
if (tmp > 14) tmp = 14;
|
||||
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
|
||||
|
||||
/* SDRAM mode value */
|
||||
sdmode = EMC_SDMR_BT_SEQ |
|
||||
EMC_SDMR_OM_NORMAL |
|
||||
EMC_SDMR_BL_4 |
|
||||
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
|
||||
REG_EMC_DMCR = dmcr;
|
||||
REG8(EMC_SDMR0|sdmode) = 0;
|
||||
|
||||
/* Wait for precharge, > 200us */
|
||||
tmp = (cpu_clk / 1000000) * 1000;
|
||||
while (tmp--);
|
||||
|
||||
/* Stage 2. Enable auto-refresh */
|
||||
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
|
||||
|
||||
tmp = SDRAM_TREF/ns;
|
||||
tmp = tmp/64 + 1;
|
||||
if (tmp > 0xff) tmp = 0xff;
|
||||
REG_EMC_RTCOR = tmp;
|
||||
REG_EMC_RTCNT = 0;
|
||||
REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
|
||||
|
||||
/* Wait for number of auto-refresh cycles */
|
||||
tmp = (cpu_clk / 1000000) * 1000;
|
||||
while (tmp--);
|
||||
|
||||
/* Stage 3. Mode Register Set */
|
||||
REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
|
||||
REG8(EMC_SDMR0|sdmode) = 0;
|
||||
|
||||
/* Set back to basic DMCR value */
|
||||
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
|
||||
|
||||
/* everything is ok now */
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
|
||||
static void calc_clocks(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
unsigned int pllout;
|
||||
unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
pllout = __cpm_get_pllout();
|
||||
|
||||
gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
|
||||
gd->sys_clk = pllout / div[__cpm_get_hdiv()];
|
||||
gd->per_clk = pllout / div[__cpm_get_pdiv()];
|
||||
gd->mem_clk = pllout / div[__cpm_get_mdiv()];
|
||||
gd->dev_clk = CONFIG_SYS_EXTAL;
|
||||
}
|
||||
|
||||
static void rtc_init(void)
|
||||
{
|
||||
unsigned long rtcsta;
|
||||
|
||||
while ( !__rtc_write_ready()) ;
|
||||
__rtc_enable_alarm(); /* enable alarm */
|
||||
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
REG_RTC_RGR = 0x00007fff; /* type value */
|
||||
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
REG_RTC_HWFCR = 0x0000ffe0; /* Power on delay 2s */
|
||||
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
REG_RTC_HRCR = 0x00000fe0; /* reset delay 125ms */
|
||||
#if 0
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
rtcsta = REG_RTC_HWRSR;
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
if (rtcsta & 0x33) {
|
||||
if (rtcsta & 0x10) {
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
REG_RTC_RSR = 0x0;
|
||||
}
|
||||
while ( !__rtc_write_ready())
|
||||
;
|
||||
REG_RTC_HWRSR = 0x0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* jz4740 board init routine
|
||||
*/
|
||||
int jz_board_init(void)
|
||||
{
|
||||
board_early_init(); /* init gpio, pll etc. */
|
||||
#ifndef CONFIG_NAND_U_BOOT
|
||||
pll_init(); /* init PLL */
|
||||
sdram_init(); /* init sdram memory */
|
||||
#endif
|
||||
calc_clocks(); /* calc the clocks */
|
||||
rtc_init(); /* init rtc on any reset: */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* U-Boot common routines */
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
u32 dmcr;
|
||||
u32 rows, cols, dw, banks;
|
||||
ulong size;
|
||||
|
||||
dmcr = REG_EMC_DMCR;
|
||||
rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
|
||||
cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
|
||||
dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
|
||||
banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
|
||||
|
||||
size = (1 << (rows + cols)) * dw * banks;
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*
|
||||
* Timer routines
|
||||
*/
|
||||
|
||||
#define TIMER_CHAN 0
|
||||
#define TIMER_FDATA 0xffff /* Timer full data value */
|
||||
#define TIMER_HZ CONFIG_SYS_HZ
|
||||
|
||||
#define READ_TIMER REG_TCU_TCNT(TIMER_CHAN) /* macro to read the 16 bit timer */
|
||||
|
||||
static ulong timestamp;
|
||||
static ulong lastdec;
|
||||
|
||||
void reset_timer_masked (void);
|
||||
ulong get_timer_masked (void);
|
||||
void udelay_masked (unsigned long usec);
|
||||
|
||||
/*
|
||||
* timer without interrupts
|
||||
*/
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
REG_TCU_TCSR(TIMER_CHAN) = TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN;
|
||||
REG_TCU_TCNT(TIMER_CHAN) = 0;
|
||||
REG_TCU_TDHR(TIMER_CHAN) = 0;
|
||||
REG_TCU_TDFR(TIMER_CHAN) = TIMER_FDATA;
|
||||
|
||||
REG_TCU_TMSR = (1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)); /* mask irqs */
|
||||
REG_TCU_TSCR = (1 << TIMER_CHAN); /* enable timer clock */
|
||||
REG_TCU_TESR = (1 << TIMER_CHAN); /* start counting up */
|
||||
|
||||
lastdec = 0;
|
||||
timestamp = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_timer(void)
|
||||
{
|
||||
reset_timer_masked ();
|
||||
}
|
||||
|
||||
ulong get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked () - base;
|
||||
}
|
||||
|
||||
void set_timer(ulong t)
|
||||
{
|
||||
timestamp = t;
|
||||
}
|
||||
|
||||
void udelay (unsigned long usec)
|
||||
{
|
||||
ulong tmo,tmp;
|
||||
|
||||
/* normalize */
|
||||
if (usec >= 1000) {
|
||||
tmo = usec / 1000;
|
||||
tmo *= TIMER_HZ;
|
||||
tmo /= 1000;
|
||||
}
|
||||
else {
|
||||
if (usec >= 1) {
|
||||
tmo = usec * TIMER_HZ;
|
||||
tmo /= (1000*1000);
|
||||
}
|
||||
else
|
||||
tmo = 1;
|
||||
}
|
||||
|
||||
/* check for rollover during this delay */
|
||||
tmp = get_timer (0);
|
||||
if ((tmp + tmo) < tmp )
|
||||
reset_timer_masked(); /* timer would roll over */
|
||||
else
|
||||
tmo += tmp;
|
||||
|
||||
while (get_timer_masked () < tmo);
|
||||
}
|
||||
|
||||
void reset_timer_masked (void)
|
||||
{
|
||||
/* reset time */
|
||||
lastdec = READ_TIMER;
|
||||
timestamp = 0;
|
||||
}
|
||||
|
||||
ulong get_timer_masked (void)
|
||||
{
|
||||
ulong now = READ_TIMER;
|
||||
|
||||
if (lastdec <= now) {
|
||||
/* normal mode */
|
||||
timestamp += (now - lastdec);
|
||||
} else {
|
||||
/* we have an overflow ... */
|
||||
timestamp += TIMER_FDATA + now - lastdec;
|
||||
}
|
||||
lastdec = now;
|
||||
|
||||
return timestamp;
|
||||
}
|
||||
|
||||
void udelay_masked (unsigned long usec)
|
||||
{
|
||||
ulong tmo;
|
||||
ulong endtime;
|
||||
signed long diff;
|
||||
|
||||
/* normalize */
|
||||
if (usec >= 1000) {
|
||||
tmo = usec / 1000;
|
||||
tmo *= TIMER_HZ;
|
||||
tmo /= 1000;
|
||||
} else {
|
||||
if (usec > 1) {
|
||||
tmo = usec * TIMER_HZ;
|
||||
tmo /= (1000*1000);
|
||||
} else {
|
||||
tmo = 1;
|
||||
}
|
||||
}
|
||||
|
||||
endtime = get_timer_masked () + tmo;
|
||||
|
||||
do {
|
||||
ulong now = get_timer_masked ();
|
||||
diff = endtime - now;
|
||||
} while (diff >= 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (read timebase as long long).
|
||||
* On MIPS it just returns the timer value.
|
||||
*/
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
return get_timer(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On MIPS it returns the number of timer ticks per second.
|
||||
*/
|
||||
ulong get_tbclk (void)
|
||||
{
|
||||
return TIMER_HZ;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
/* End of timer routine. */
|
||||
|
||||
#endif
|
199
package/uboot-xburst/files/cpu/mips/jz4740_nand.c
Normal file
199
package/uboot-xburst/files/cpu/mips/jz4740_nand.c
Normal file
@ -0,0 +1,199 @@
|
||||
/*
|
||||
* Platform independend driver for JZ4740.
|
||||
*
|
||||
* Copyright (c) 2007 Ingenic Semiconductor Inc.
|
||||
* Author: <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
#include <common.h>
|
||||
|
||||
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_JZ4740)
|
||||
|
||||
#include <nand.h>
|
||||
#include <asm/jz4740.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define PAR_SIZE 9
|
||||
#define __nand_ecc_enable() (REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST )
|
||||
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
|
||||
|
||||
#define __nand_select_rs_ecc() (REG_EMC_NFECR |= EMC_NFECR_RS)
|
||||
|
||||
#define __nand_rs_ecc_encoding() (REG_EMC_NFECR |= EMC_NFECR_RS_ENCODING)
|
||||
#define __nand_rs_ecc_decoding() (REG_EMC_NFECR |= EMC_NFECR_RS_DECODING)
|
||||
#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
|
||||
#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
|
||||
|
||||
static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
/* Change this to use I/O accessors. */
|
||||
if (ctrl & NAND_NCE)
|
||||
REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
|
||||
else
|
||||
REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
|
||||
}
|
||||
|
||||
if (cmd == NAND_CMD_NONE)
|
||||
return;
|
||||
|
||||
if (ctrl & NAND_CLE)
|
||||
nandaddr |= 0x00008000;
|
||||
else /* must be ALE */
|
||||
nandaddr |= 0x00010000;
|
||||
|
||||
writeb(cmd, (uint8_t *)nandaddr);
|
||||
}
|
||||
|
||||
static int jz_device_ready(struct mtd_info *mtd)
|
||||
{
|
||||
int ready;
|
||||
udelay(20); /* FIXME: add 20us delay */
|
||||
ready = (REG_GPIO_PXPIN(2) & 0x40000000) ? 1 : 0;
|
||||
return ready;
|
||||
}
|
||||
|
||||
/*
|
||||
* EMC setup
|
||||
*/
|
||||
static void jz_device_setup(void)
|
||||
{
|
||||
/* Set NFE bit */
|
||||
REG_EMC_NFCSR |= EMC_NFCSR_NFE1;
|
||||
REG_EMC_SMCR1 = 0x094c4400;
|
||||
/* REG_EMC_SMCR3 = 0x04444400; */
|
||||
}
|
||||
|
||||
void board_nand_select_device(struct nand_chip *nand, int chip)
|
||||
{
|
||||
/*
|
||||
* Don't use "chip" to address the NAND device,
|
||||
* generate the cs from the address where it is encoded.
|
||||
*/
|
||||
}
|
||||
|
||||
static int jzsoc_nand_calculate_rs_ecc(struct mtd_info* mtd, const u_char* dat,
|
||||
u_char* ecc_code)
|
||||
{
|
||||
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
|
||||
short i;
|
||||
|
||||
__nand_ecc_encode_sync()
|
||||
__nand_ecc_disable();
|
||||
|
||||
for(i = 0; i < PAR_SIZE; i++)
|
||||
ecc_code[i] = *paraddr++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jzsoc_nand_enable_rs_hwecc(struct mtd_info* mtd, int mode)
|
||||
{
|
||||
__nand_ecc_enable();
|
||||
__nand_select_rs_ecc();
|
||||
|
||||
REG_EMC_NFINTS = 0x0;
|
||||
if (NAND_ECC_READ == mode){
|
||||
__nand_rs_ecc_decoding();
|
||||
}
|
||||
if (NAND_ECC_WRITE == mode){
|
||||
__nand_rs_ecc_encoding();
|
||||
}
|
||||
}
|
||||
|
||||
/* Correct 1~9-bit errors in 512-bytes data */
|
||||
static void jzsoc_rs_correct(unsigned char *dat, int idx, int mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
idx--;
|
||||
|
||||
i = idx + (idx >> 3);
|
||||
if (i >= 512)
|
||||
return;
|
||||
|
||||
mask <<= (idx & 0x7);
|
||||
|
||||
dat[i] ^= mask & 0xff;
|
||||
if (i < 511)
|
||||
dat[i+1] ^= (mask >> 8) & 0xff;
|
||||
}
|
||||
|
||||
static int jzsoc_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc)
|
||||
{
|
||||
volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
|
||||
short k;
|
||||
u32 stat;
|
||||
/* Set PAR values */
|
||||
|
||||
for (k = 0; k < PAR_SIZE; k++) {
|
||||
*paraddr++ = read_ecc[k];
|
||||
}
|
||||
|
||||
/* Set PRDY */
|
||||
REG_EMC_NFECR |= EMC_NFECR_PRDY;
|
||||
|
||||
/* Wait for completion */
|
||||
__nand_ecc_decode_sync();
|
||||
__nand_ecc_disable();
|
||||
|
||||
/* Check decoding */
|
||||
stat = REG_EMC_NFINTS;
|
||||
if (stat & EMC_NFINTS_ERR) {
|
||||
if (stat & EMC_NFINTS_UNCOR) {
|
||||
printk("Uncorrectable error occurred\n");
|
||||
return -1;
|
||||
}
|
||||
else {
|
||||
u32 errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
|
||||
switch (errcnt) {
|
||||
case 4:
|
||||
jzsoc_rs_correct(dat, (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
|
||||
case 3:
|
||||
jzsoc_rs_correct(dat, (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
|
||||
case 2:
|
||||
jzsoc_rs_correct(dat, (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
|
||||
case 1:
|
||||
jzsoc_rs_correct(dat, (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT, (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT);
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* no error need to be correct */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Main initialization routine
|
||||
*/
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
jz_device_setup();
|
||||
|
||||
nand->cmd_ctrl = jz_hwcontrol;
|
||||
nand->dev_ready = jz_device_ready;
|
||||
|
||||
/* FIXME: should use NAND_ECC_SOFT */
|
||||
nand->ecc.hwctl = jzsoc_nand_enable_rs_hwecc;
|
||||
nand->ecc.correct = jzsoc_nand_rs_correct_data;
|
||||
nand->ecc.calculate = jzsoc_nand_calculate_rs_ecc;
|
||||
nand->ecc.mode = NAND_ECC_HW;
|
||||
nand->ecc.size = 512;
|
||||
nand->ecc.bytes = 9;
|
||||
|
||||
/* 20 us command delay time */
|
||||
nand->chip_delay = 20;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* (CONFIG_SYS_CMD_NAND) */
|
484
package/uboot-xburst/files/cpu/mips/jz_lcd.c
Normal file
484
package/uboot-xburst/files/cpu/mips/jz_lcd.c
Normal file
@ -0,0 +1,484 @@
|
||||
/*
|
||||
* JzRISC lcd controller
|
||||
*
|
||||
* xiangfu liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Fallowing macro may be used:
|
||||
* CONFIG_LCD : LCD support
|
||||
* LCD_BPP : Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8
|
||||
* CONFIG_LCD_LOGO : show logo
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <lcd.h>
|
||||
|
||||
#include <asm/io.h> /* virt_to_phys() */
|
||||
|
||||
#if defined(CONFIG_LCD) && !defined(CONFIG_SLCD)
|
||||
|
||||
#if defined(CONFIG_JZ4740)
|
||||
#include <asm/jz4740.h>
|
||||
#endif
|
||||
|
||||
#include "jz_lcd.h"
|
||||
|
||||
|
||||
struct jzfb_info {
|
||||
unsigned int cfg; /* panel mode and pin usage etc. */
|
||||
unsigned int w;
|
||||
unsigned int h;
|
||||
unsigned int bpp; /* bit per pixel */
|
||||
unsigned int fclk; /* frame clk */
|
||||
unsigned int hsw; /* hsync width, in pclk */
|
||||
unsigned int vsw; /* vsync width, in line count */
|
||||
unsigned int elw; /* end of line, in pclk */
|
||||
unsigned int blw; /* begin of line, in pclk */
|
||||
unsigned int efw; /* end of frame, in line count */
|
||||
unsigned int bfw; /* begin of frame, in line count */
|
||||
};
|
||||
|
||||
static struct jzfb_info jzfb = {
|
||||
#if defined(CONFIG_NANONOTE)
|
||||
MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
|
||||
320, 240, 32, 70, 1, 1, 273, 140, 1, 20
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
/************************************************************************/
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
|
||||
320, 240, LCD_BPP,
|
||||
#endif
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
int lcd_line_length;
|
||||
|
||||
int lcd_color_fg;
|
||||
int lcd_color_bg;
|
||||
|
||||
/*
|
||||
* Frame buffer memory information
|
||||
*/
|
||||
void *lcd_base; /* Start of framebuffer memory */
|
||||
void *lcd_console_address; /* Start of console buffer */
|
||||
|
||||
short console_col;
|
||||
short console_row;
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
void lcd_ctrl_init (void *lcdbase);
|
||||
|
||||
void lcd_enable (void);
|
||||
void lcd_disable (void);
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
|
||||
static void jz_lcd_desc_init(vidinfo_t *vid);
|
||||
static int jz_lcd_hw_init( vidinfo_t *vid );
|
||||
extern int flush_cache_all(void);
|
||||
|
||||
#if LCD_BPP == LCD_COLOR8
|
||||
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
|
||||
#endif
|
||||
#if LCD_BPP == LCD_MONOCHROME
|
||||
void lcd_initcolregs (void);
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
void lcd_ctrl_init (void *lcdbase)
|
||||
{
|
||||
__lcd_display_pin_init();
|
||||
|
||||
jz_lcd_init_mem(lcdbase, &panel_info);
|
||||
jz_lcd_desc_init(&panel_info);
|
||||
jz_lcd_hw_init(&panel_info);
|
||||
|
||||
__lcd_display_on() ;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
#if LCD_BPP == LCD_COLOR8
|
||||
void
|
||||
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
#if LCD_BPP == LCD_MONOCHROME
|
||||
static
|
||||
void lcd_initcolregs (void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Before enabled lcd controller, lcd registers should be configured correctly.
|
||||
*/
|
||||
|
||||
void lcd_enable (void)
|
||||
{
|
||||
REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
|
||||
REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
|
||||
}
|
||||
|
||||
void lcd_disable (void)
|
||||
{
|
||||
REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
|
||||
/* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
|
||||
}
|
||||
|
||||
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
|
||||
{
|
||||
u_long palette_mem_size;
|
||||
struct jz_fb_info *fbi = &vid->jz_fb;
|
||||
int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
|
||||
|
||||
fbi->screen = (u_long)lcdbase;
|
||||
fbi->palette_size = 256;
|
||||
palette_mem_size = fbi->palette_size * sizeof(u16);
|
||||
|
||||
debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
|
||||
/* locate palette and descs at end of page following fb */
|
||||
fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_lcd_desc_init(vidinfo_t *vid)
|
||||
{
|
||||
struct jz_fb_info * fbi;
|
||||
fbi = &vid->jz_fb;
|
||||
fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
|
||||
fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
|
||||
fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
|
||||
|
||||
#define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
|
||||
|
||||
/* populate descriptors */
|
||||
fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
|
||||
fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
|
||||
fbi->dmadesc_fblow->fidr = 0;
|
||||
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
|
||||
|
||||
fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
|
||||
|
||||
fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
|
||||
fbi->dmadesc_fbhigh->fidr = 0;
|
||||
fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
|
||||
|
||||
fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
|
||||
fbi->dmadesc_palette->fidr = 0;
|
||||
fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
|
||||
|
||||
if( NBITS(vid->vl_bpix) < 12)
|
||||
{
|
||||
/* assume any mode with <12 bpp is palette driven */
|
||||
fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
|
||||
fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
|
||||
/* flips back and forth between pal and fbhigh */
|
||||
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
|
||||
} else {
|
||||
/* palette shouldn't be loaded in true-color mode */
|
||||
fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
|
||||
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
|
||||
}
|
||||
|
||||
flush_cache_all();
|
||||
}
|
||||
|
||||
static int jz_lcd_hw_init(vidinfo_t *vid)
|
||||
{
|
||||
struct jz_fb_info *fbi = &vid->jz_fb;
|
||||
unsigned int val = 0;
|
||||
unsigned int pclk;
|
||||
unsigned int stnH;
|
||||
#if defined(CONFIG_MIPS_JZ4740)
|
||||
int pll_div;
|
||||
#endif
|
||||
|
||||
/* Setting Control register */
|
||||
switch (jzfb.bpp) {
|
||||
case 1:
|
||||
val |= LCD_CTRL_BPP_1;
|
||||
break;
|
||||
case 2:
|
||||
val |= LCD_CTRL_BPP_2;
|
||||
break;
|
||||
case 4:
|
||||
val |= LCD_CTRL_BPP_4;
|
||||
break;
|
||||
case 8:
|
||||
val |= LCD_CTRL_BPP_8;
|
||||
break;
|
||||
case 15:
|
||||
val |= LCD_CTRL_RGB555;
|
||||
case 16:
|
||||
val |= LCD_CTRL_BPP_16;
|
||||
break;
|
||||
#if defined(CONFIG_MIPS_JZ4740)
|
||||
case 17 ... 32:
|
||||
val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
|
||||
val |= LCD_CTRL_BPP_16;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_STN_MONO_DUAL:
|
||||
case MODE_STN_COLOR_DUAL:
|
||||
case MODE_STN_MONO_SINGLE:
|
||||
case MODE_STN_COLOR_SINGLE:
|
||||
switch (jzfb.bpp) {
|
||||
case 1:
|
||||
/* val |= LCD_CTRL_PEDN; */
|
||||
case 2:
|
||||
val |= LCD_CTRL_FRC_2;
|
||||
break;
|
||||
case 4:
|
||||
val |= LCD_CTRL_FRC_4;
|
||||
break;
|
||||
case 8:
|
||||
default:
|
||||
val |= LCD_CTRL_FRC_16;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
|
||||
val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_STN_MONO_DUAL:
|
||||
case MODE_STN_COLOR_DUAL:
|
||||
case MODE_STN_MONO_SINGLE:
|
||||
case MODE_STN_COLOR_SINGLE:
|
||||
switch (jzfb.cfg & STN_DAT_PINMASK) {
|
||||
#define align2(n) (n)=((((n)+1)>>1)<<1)
|
||||
#define align4(n) (n)=((((n)+3)>>2)<<2)
|
||||
#define align8(n) (n)=((((n)+7)>>3)<<3)
|
||||
case STN_DAT_PIN1:
|
||||
/* Do not adjust the hori-param value. */
|
||||
break;
|
||||
case STN_DAT_PIN2:
|
||||
align2(jzfb.hsw);
|
||||
align2(jzfb.elw);
|
||||
align2(jzfb.blw);
|
||||
break;
|
||||
case STN_DAT_PIN4:
|
||||
align4(jzfb.hsw);
|
||||
align4(jzfb.elw);
|
||||
align4(jzfb.blw);
|
||||
break;
|
||||
case STN_DAT_PIN8:
|
||||
align8(jzfb.hsw);
|
||||
align8(jzfb.elw);
|
||||
align8(jzfb.blw);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
REG_LCD_CTRL = val;
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_STN_MONO_DUAL:
|
||||
case MODE_STN_COLOR_DUAL:
|
||||
case MODE_STN_MONO_SINGLE:
|
||||
case MODE_STN_COLOR_SINGLE:
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
|
||||
stnH = jzfb.h >> 1;
|
||||
else
|
||||
stnH = jzfb.h;
|
||||
|
||||
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
|
||||
REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
|
||||
|
||||
/* Screen setting */
|
||||
REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
|
||||
REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
|
||||
REG_LCD_DAV = (0 << 16) | (stnH);
|
||||
|
||||
/* AC BIAs signal */
|
||||
REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
|
||||
|
||||
break;
|
||||
|
||||
case MODE_TFT_GEN:
|
||||
case MODE_TFT_SHARP:
|
||||
case MODE_TFT_CASIO:
|
||||
case MODE_TFT_SAMSUNG:
|
||||
case MODE_8BIT_SERIAL_TFT:
|
||||
case MODE_TFT_18BIT:
|
||||
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
|
||||
REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
|
||||
#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
|
||||
REG_LCD_DAV = (0 << 16) | ( jzfb.h );
|
||||
#else
|
||||
REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
|
||||
#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
|
||||
REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
|
||||
REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
|
||||
| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_TFT_SAMSUNG:
|
||||
{
|
||||
unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
|
||||
unsigned int rev_s, rev_e, inv_s, inv_e;
|
||||
|
||||
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
|
||||
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
|
||||
|
||||
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
|
||||
tp_s = jzfb.blw + jzfb.w + 1;
|
||||
tp_e = tp_s + 1;
|
||||
/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
|
||||
ckv_s = tp_s - pclk/(1000000000/4100);
|
||||
ckv_e = tp_s + total;
|
||||
rev_s = tp_s - 11; /* -11.5 clk */
|
||||
rev_e = rev_s + total;
|
||||
inv_s = tp_s;
|
||||
inv_e = inv_s + total;
|
||||
REG_LCD_CLS = (tp_s << 16) | tp_e;
|
||||
REG_LCD_PS = (ckv_s << 16) | ckv_e;
|
||||
REG_LCD_SPL = (rev_s << 16) | rev_e;
|
||||
REG_LCD_REV = (inv_s << 16) | inv_e;
|
||||
jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
|
||||
break;
|
||||
}
|
||||
case MODE_TFT_SHARP:
|
||||
{
|
||||
unsigned int total, cls_s, cls_e, ps_s, ps_e;
|
||||
unsigned int spl_s, spl_e, rev_s, rev_e;
|
||||
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
|
||||
#if !defined(CONFIG_JZLCD_INNOLUX_AT080TN42)
|
||||
spl_s = 1;
|
||||
spl_e = spl_s + 1;
|
||||
cls_s = 0;
|
||||
cls_e = total - 60; /* > 4us (pclk = 80ns) */
|
||||
ps_s = cls_s;
|
||||
ps_e = cls_e;
|
||||
rev_s = total - 40; /* > 3us (pclk = 80ns) */
|
||||
rev_e = rev_s + total;
|
||||
jzfb.cfg |= STFT_PSHI;
|
||||
#else /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
|
||||
spl_s = total - 5; /* LD */
|
||||
spl_e = total -3;
|
||||
cls_s = 32; /* CKV */
|
||||
cls_e = 145;
|
||||
ps_s = 0; /* OEV */
|
||||
ps_e = 45;
|
||||
rev_s = 0; /* POL */
|
||||
rev_e = 0;
|
||||
#endif /*#if defined(CONFIG_JZLCD_INNOLUX_AT080TN42)*/
|
||||
REG_LCD_SPL = (spl_s << 16) | spl_e;
|
||||
REG_LCD_CLS = (cls_s << 16) | cls_e;
|
||||
REG_LCD_PS = (ps_s << 16) | ps_e;
|
||||
REG_LCD_REV = (rev_s << 16) | rev_e;
|
||||
break;
|
||||
}
|
||||
case MODE_TFT_CASIO:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Configure the LCD panel */
|
||||
REG_LCD_CFG = jzfb.cfg;
|
||||
|
||||
/* Timing setting */
|
||||
__cpm_stop_lcd();
|
||||
|
||||
val = jzfb.fclk; /* frame clk */
|
||||
if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
|
||||
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
|
||||
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
|
||||
}
|
||||
else {
|
||||
/* serial mode: Hsync period = 3*Width_Pixel */
|
||||
pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
|
||||
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
|
||||
}
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
|
||||
pclk = (pclk * 3);
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
||||
pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
||||
pclk >>= 1;
|
||||
|
||||
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
|
||||
pll_div = pll_div ? 1 : 2 ;
|
||||
val = ( __cpm_get_pllout()/pll_div ) / pclk;
|
||||
val--;
|
||||
if ( val > 0x1ff ) {
|
||||
printf("CPM_LPCDR too large, set it to 0x1ff\n");
|
||||
val = 0x1ff;
|
||||
}
|
||||
__cpm_set_pixdiv(val);
|
||||
|
||||
val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
|
||||
if ( val > 150000000 ) {
|
||||
printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
|
||||
printf("Change LCDClock to 150MHz\n");
|
||||
val = 150000000;
|
||||
}
|
||||
val = ( __cpm_get_pllout()/pll_div ) / val;
|
||||
val--;
|
||||
if ( val > 0x1f ) {
|
||||
printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
|
||||
val = 0x1f;
|
||||
}
|
||||
__cpm_set_ldiv( val );
|
||||
REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
|
||||
|
||||
__cpm_start_lcd();
|
||||
udelay(1000);
|
||||
|
||||
REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
||||
REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
260
package/uboot-xburst/files/cpu/mips/jz_lcd.h
Normal file
260
package/uboot-xburst/files/cpu/mips/jz_lcd.h
Normal file
@ -0,0 +1,260 @@
|
||||
/*
|
||||
* JzRISC lcd controller
|
||||
*
|
||||
* xiangfu liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __JZLCD_H__
|
||||
#define __JZLCD_H__
|
||||
|
||||
#include <asm/io.h>
|
||||
/*
|
||||
* change u-boot macro to celinux macro
|
||||
*/
|
||||
/* Chip type */
|
||||
#if defined(CONFIG_JZ4740)
|
||||
#define CONFIG_MIPS_JZ4740 1
|
||||
#endif
|
||||
|
||||
/* board type */
|
||||
#if defined(CONFIG_NANONOTE)
|
||||
#define CONFIG_MIPS_JZ4740_PI 1
|
||||
#endif
|
||||
|
||||
#define mdelay(n) udelay((n)*1000)
|
||||
|
||||
/*
|
||||
* change u-boot macro to celinux macro
|
||||
*/
|
||||
|
||||
#define NR_PALETTE 256
|
||||
|
||||
struct lcd_desc{
|
||||
unsigned int next_desc; /* LCDDAx */
|
||||
unsigned int databuf; /* LCDSAx */
|
||||
unsigned int frame_id; /* LCDFIDx */
|
||||
unsigned int cmd; /* LCDCMDx */
|
||||
};
|
||||
|
||||
#define MODE_MASK 0x0f
|
||||
#define MODE_TFT_GEN 0x00
|
||||
#define MODE_TFT_SHARP 0x01
|
||||
#define MODE_TFT_CASIO 0x02
|
||||
#define MODE_TFT_SAMSUNG 0x03
|
||||
#define MODE_CCIR656_NONINT 0x04
|
||||
#define MODE_CCIR656_INT 0x05
|
||||
#define MODE_STN_COLOR_SINGLE 0x08
|
||||
#define MODE_STN_MONO_SINGLE 0x09
|
||||
#define MODE_STN_COLOR_DUAL 0x0a
|
||||
#define MODE_STN_MONO_DUAL 0x0b
|
||||
#define MODE_8BIT_SERIAL_TFT 0x0c
|
||||
|
||||
#define MODE_TFT_18BIT (1<<7)
|
||||
|
||||
#define STN_DAT_PIN1 (0x00 << 4)
|
||||
#define STN_DAT_PIN2 (0x01 << 4)
|
||||
#define STN_DAT_PIN4 (0x02 << 4)
|
||||
#define STN_DAT_PIN8 (0x03 << 4)
|
||||
#define STN_DAT_PINMASK STN_DAT_PIN8
|
||||
|
||||
#define STFT_PSHI (1 << 15)
|
||||
#define STFT_CLSHI (1 << 14)
|
||||
#define STFT_SPLHI (1 << 13)
|
||||
#define STFT_REVHI (1 << 12)
|
||||
|
||||
#define SYNC_MASTER (0 << 16)
|
||||
#define SYNC_SLAVE (1 << 16)
|
||||
|
||||
#define DE_P (0 << 9)
|
||||
#define DE_N (1 << 9)
|
||||
|
||||
#define PCLK_P (0 << 10)
|
||||
#define PCLK_N (1 << 10)
|
||||
|
||||
#define HSYNC_P (0 << 11)
|
||||
#define HSYNC_N (1 << 11)
|
||||
|
||||
#define VSYNC_P (0 << 8)
|
||||
#define VSYNC_N (1 << 8)
|
||||
|
||||
#define DATA_NORMAL (0 << 17)
|
||||
#define DATA_INVERSE (1 << 17)
|
||||
|
||||
|
||||
/* Jz LCDFB supported I/O controls. */
|
||||
#define FBIOSETBACKLIGHT 0x4688
|
||||
#define FBIODISPON 0x4689
|
||||
#define FBIODISPOFF 0x468a
|
||||
#define FBIORESET 0x468b
|
||||
#define FBIOPRINT_REG 0x468c
|
||||
|
||||
/*
|
||||
* LCD panel specific definition
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
|
||||
|
||||
#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
|
||||
#define MODE 0xcd /* 24bit parellel RGB */
|
||||
#endif
|
||||
#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
|
||||
#define MODE 0xc9 /* 8bit serial RGB */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MIPS_JZ4740_PI) /* board pavo */
|
||||
#define SPEN (32*2+21) /*LCD_SPL */
|
||||
#define SPCK (32*2+23) /*LCD_CLS */
|
||||
#define SPDA (32*2+22) /*LCD_D12 */
|
||||
#define LCD_RET (32*3+27)
|
||||
#else
|
||||
#error "cpu/misp/Jzlcd.h, please define SPI pins on your board."
|
||||
#endif
|
||||
|
||||
#define __spi_write_reg1(reg, val) \
|
||||
do { \
|
||||
unsigned char no;\
|
||||
unsigned short value;\
|
||||
unsigned char a=0;\
|
||||
unsigned char b=0;\
|
||||
a=reg;\
|
||||
b=val;\
|
||||
__gpio_set_pin(SPEN);\
|
||||
__gpio_set_pin(SPCK);\
|
||||
__gpio_clear_pin(SPDA);\
|
||||
__gpio_clear_pin(SPEN);\
|
||||
udelay(25);\
|
||||
value=((a<<8)|(b&0xFF));\
|
||||
for(no=0;no<16;no++)\
|
||||
{\
|
||||
__gpio_clear_pin(SPCK);\
|
||||
if((value&0x8000)==0x8000)\
|
||||
__gpio_set_pin(SPDA);\
|
||||
else\
|
||||
__gpio_clear_pin(SPDA);\
|
||||
udelay(25);\
|
||||
__gpio_set_pin(SPCK);\
|
||||
value=(value<<1); \
|
||||
udelay(25);\
|
||||
}\
|
||||
__gpio_set_pin(SPEN);\
|
||||
udelay(100);\
|
||||
} while (0)
|
||||
|
||||
#define __spi_write_reg(reg, val) \
|
||||
do {\
|
||||
__spi_write_reg1((reg<<2|2), val);\
|
||||
udelay(100); \
|
||||
}while(0)
|
||||
|
||||
|
||||
#define __lcd_special_pin_init() \
|
||||
do { \
|
||||
__gpio_as_output(SPEN); /* use SPDA */\
|
||||
__gpio_as_output(SPCK); /* use SPCK */\
|
||||
__gpio_as_output(SPDA); /* use SPDA */\
|
||||
__gpio_as_output(LCD_RET);\
|
||||
} while (0)
|
||||
|
||||
#if defined(CONFIG_NANONOTE)
|
||||
#define __lcd_special_on() \
|
||||
do { \
|
||||
udelay(50);\
|
||||
__spi_write_reg1(0x05, 0x16); \
|
||||
__spi_write_reg1(0x04, 0x0b); \
|
||||
__spi_write_reg1(0x07, 0x8d); \
|
||||
__spi_write_reg1(0x01, 0x95); \
|
||||
__spi_write_reg1(0x08, 0xc0); \
|
||||
__spi_write_reg1(0x03, 0x40); \
|
||||
__spi_write_reg1(0x06, 0x15); \
|
||||
__spi_write_reg1(0x05, 0xd7); \
|
||||
} while (0) /* reg 0x0a is control the display direction:DB0->horizontal level DB1->vertical level */
|
||||
|
||||
#define __lcd_special_off() \
|
||||
do { \
|
||||
__spi_write_reg1(0x05, 0x5e); \
|
||||
} while (0)
|
||||
#endif /* CONFIG_NANONOTE */
|
||||
#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 or CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL */
|
||||
|
||||
#ifndef __lcd_special_pin_init
|
||||
#define __lcd_special_pin_init()
|
||||
#endif
|
||||
#ifndef __lcd_special_on
|
||||
#define __lcd_special_on()
|
||||
#endif
|
||||
#ifndef __lcd_special_off
|
||||
#define __lcd_special_off()
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Platform specific definition
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_MIPS_JZ4740_PI)
|
||||
|
||||
/* 100 level: 0,1,...,100 */
|
||||
#define __lcd_set_backlight_level(n)\
|
||||
do { \
|
||||
__gpio_as_output(32*3+27); \
|
||||
__gpio_set_pin(32*3+27); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_close_backlight() \
|
||||
do { \
|
||||
__gpio_as_output(GPIO_PWM); \
|
||||
__gpio_clear_pin(GPIO_PWM); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_pin_init() \
|
||||
do { \
|
||||
__gpio_as_output(GPIO_DISP_OFF_N); \
|
||||
__cpm_start_tcu(); \
|
||||
__lcd_special_pin_init(); \
|
||||
} while (0)
|
||||
/* __lcd_set_backlight_level(100); \*/
|
||||
#define __lcd_display_on() \
|
||||
do { \
|
||||
__gpio_set_pin(GPIO_DISP_OFF_N); \
|
||||
__lcd_special_on(); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_off() \
|
||||
do { \
|
||||
__lcd_special_off(); \
|
||||
__gpio_clear_pin(GPIO_DISP_OFF_N); \
|
||||
} while (0)
|
||||
|
||||
#endif /* CONFIG_MIPS_JZ4740_PI) */
|
||||
|
||||
/*****************************************************************************
|
||||
* LCD display pin dummy macros
|
||||
*****************************************************************************/
|
||||
#ifndef __lcd_display_pin_init
|
||||
#define __lcd_display_pin_init()
|
||||
#endif
|
||||
#ifndef __lcd_display_on
|
||||
#define __lcd_display_on()
|
||||
#endif
|
||||
#ifndef __lcd_display_off
|
||||
#define __lcd_display_off()
|
||||
#endif
|
||||
#ifndef __lcd_set_backlight_level
|
||||
#define __lcd_set_backlight_level(n)
|
||||
#endif
|
||||
|
1416
package/uboot-xburst/files/cpu/mips/jz_mmc.c
Normal file
1416
package/uboot-xburst/files/cpu/mips/jz_mmc.c
Normal file
File diff suppressed because it is too large
Load Diff
1399
package/uboot-xburst/files/cpu/mips/jz_mmc.c.orig
Normal file
1399
package/uboot-xburst/files/cpu/mips/jz_mmc.c.orig
Normal file
File diff suppressed because it is too large
Load Diff
113
package/uboot-xburst/files/cpu/mips/jz_mmc.h
Normal file
113
package/uboot-xburst/files/cpu/mips/jz_mmc.h
Normal file
@ -0,0 +1,113 @@
|
||||
/*
|
||||
* linux/drivers/mmc/jz_mmc.h
|
||||
*
|
||||
* Author: Vladimir Shebordaev, Igor Oblakov
|
||||
* Copyright: MontaVista Software Inc.
|
||||
*
|
||||
* $Id: jz_mmc.h,v 1.3 2007-06-15 08:04:20 jlwei Exp $
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __MMC_JZMMC_H__
|
||||
#define __MMC_JZMMC_H__
|
||||
|
||||
#include "mmc_protocol.h"
|
||||
|
||||
#define MMC_DEBUG_LEVEL 0 /* Enable Debug: 0 - no debug */
|
||||
|
||||
#define MMC_BLOCK_SIZE 512 /* MMC/SD Block Size */
|
||||
|
||||
#define ID_TO_RCA(x) ((x)+1)
|
||||
|
||||
#define MMC_OCR_ARG 0x00ff8000 /* Argument of OCR */
|
||||
|
||||
enum mmc_result_t {
|
||||
MMC_NO_RESPONSE = -1,
|
||||
MMC_NO_ERROR = 0,
|
||||
MMC_ERROR_OUT_OF_RANGE,
|
||||
MMC_ERROR_ADDRESS,
|
||||
MMC_ERROR_BLOCK_LEN,
|
||||
MMC_ERROR_ERASE_SEQ,
|
||||
MMC_ERROR_ERASE_PARAM,
|
||||
MMC_ERROR_WP_VIOLATION,
|
||||
MMC_ERROR_CARD_IS_LOCKED,
|
||||
MMC_ERROR_LOCK_UNLOCK_FAILED,
|
||||
MMC_ERROR_COM_CRC,
|
||||
MMC_ERROR_ILLEGAL_COMMAND,
|
||||
MMC_ERROR_CARD_ECC_FAILED,
|
||||
MMC_ERROR_CC,
|
||||
MMC_ERROR_GENERAL,
|
||||
MMC_ERROR_UNDERRUN,
|
||||
MMC_ERROR_OVERRUN,
|
||||
MMC_ERROR_CID_CSD_OVERWRITE,
|
||||
MMC_ERROR_STATE_MISMATCH,
|
||||
MMC_ERROR_HEADER_MISMATCH,
|
||||
MMC_ERROR_TIMEOUT,
|
||||
MMC_ERROR_CRC,
|
||||
MMC_ERROR_DRIVER_FAILURE,
|
||||
};
|
||||
|
||||
/* the information structure of MMC/SD Card */
|
||||
typedef struct MMC_INFO
|
||||
{
|
||||
int id; /* Card index */
|
||||
int sd; /* MMC or SD card */
|
||||
int rca; /* RCA */
|
||||
u32 scr; /* SCR 63:32*/
|
||||
int flags; /* Ejected, inserted */
|
||||
enum card_state state; /* empty, ident, ready, whatever */
|
||||
|
||||
/* Card specific information */
|
||||
struct mmc_cid cid;
|
||||
struct mmc_csd csd;
|
||||
u32 block_num;
|
||||
u32 block_len;
|
||||
u32 erase_unit;
|
||||
} mmc_info;
|
||||
|
||||
mmc_info mmcinfo;
|
||||
|
||||
struct mmc_request {
|
||||
int index; /* Slot index - used for CS lines */
|
||||
int cmd; /* Command to send */
|
||||
u32 arg; /* Argument to send */
|
||||
enum mmc_rsp_t rtype; /* Response type expected */
|
||||
|
||||
/* Data transfer (these may be modified at the low level) */
|
||||
u16 nob; /* Number of blocks to transfer*/
|
||||
u16 block_len; /* Block length */
|
||||
u8 *buffer; /* Data buffer */
|
||||
u32 cnt; /* Data length, for PIO */
|
||||
|
||||
/* Results */
|
||||
u8 response[18]; /* Buffer to store response - CRC is optional */
|
||||
enum mmc_result_t result;
|
||||
};
|
||||
|
||||
char * mmc_result_to_string(int);
|
||||
int mmc_unpack_csd(struct mmc_request *request, struct mmc_csd *csd);
|
||||
int mmc_unpack_r1(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state);
|
||||
int mmc_unpack_r6(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, int *rca);
|
||||
int mmc_unpack_scr(struct mmc_request *request, struct mmc_response_r1 *r1, enum card_state state, u32 *scr);
|
||||
int mmc_unpack_cid(struct mmc_request *request, struct mmc_cid *cid);
|
||||
int mmc_unpack_r3(struct mmc_request *request, struct mmc_response_r3 *r3);
|
||||
|
||||
void mmc_send_cmd(struct mmc_request *request, int cmd, u32 arg,
|
||||
u16 nob, u16 block_len, enum mmc_rsp_t rtype, u8 *buffer);
|
||||
u32 mmc_tran_speed(u8 ts);
|
||||
void jz_mmc_set_clock(int sd, u32 rate);
|
||||
void jz_mmc_hardware_init(void);
|
||||
|
||||
static inline void mmc_simple_cmd(struct mmc_request *request, int cmd, u32 arg, enum mmc_rsp_t rtype)
|
||||
{
|
||||
mmc_send_cmd( request, cmd, arg, 0, 0, rtype, 0);
|
||||
}
|
||||
|
||||
int mmc_legacy_init(int verbose);
|
||||
int mmc_read(ulong src, uchar *dst, int size);
|
||||
int mmc_write(uchar *src, ulong dst, int size);
|
||||
int mmc2info(ulong addr);
|
||||
|
||||
#endif /* __MMC_JZMMC_H__ */
|
141
package/uboot-xburst/files/cpu/mips/jz_serial.c
Normal file
141
package/uboot-xburst/files/cpu/mips/jz_serial.c
Normal file
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Jz47xx UART support
|
||||
*
|
||||
* Hardcoded to UART 0 for now
|
||||
* Options also hardcoded to 8N1
|
||||
*
|
||||
* Copyright (c) 2005
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#if defined(CONFIG_JZ4740)
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
#undef UART_BASE
|
||||
#ifndef CONFIG_SYS_UART_BASE
|
||||
#define UART_BASE UART0_BASE
|
||||
#else
|
||||
#define UART_BASE CONFIG_SYS_UART_BASE
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
*
|
||||
* serial_init - initialize a channel
|
||||
*
|
||||
* This routine initializes the number of data bits, parity
|
||||
* and set the selected baud rate. Interrupts are disabled.
|
||||
* Set the modem control signals if the option is selected.
|
||||
*
|
||||
* RETURNS: N/A
|
||||
*/
|
||||
|
||||
int serial_init (void)
|
||||
{
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
|
||||
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
||||
volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
|
||||
volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
|
||||
|
||||
/* Disable port interrupts while changing hardware */
|
||||
*uart_ier = 0;
|
||||
|
||||
/* Disable UART unit function */
|
||||
*uart_fcr = ~UART_FCR_UUE;
|
||||
|
||||
/* Set both receiver and transmitter in UART mode (not SIR) */
|
||||
*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
|
||||
|
||||
/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
|
||||
*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
|
||||
|
||||
/* Set baud rate */
|
||||
serial_setbrg();
|
||||
|
||||
/* Enable UART unit, enable and clear FIFO */
|
||||
*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
||||
volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
|
||||
volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
|
||||
u32 baud_div, tmp;
|
||||
|
||||
baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
|
||||
|
||||
tmp = *uart_lcr;
|
||||
tmp |= UART_LCR_DLAB;
|
||||
*uart_lcr = tmp;
|
||||
|
||||
*uart_dlhr = (baud_div >> 8) & 0xff;
|
||||
*uart_dllr = baud_div & 0xff;
|
||||
|
||||
tmp &= ~UART_LCR_DLAB;
|
||||
*uart_lcr = tmp;
|
||||
}
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
|
||||
volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR);
|
||||
|
||||
if (c == '\n') serial_putc ('\r');
|
||||
|
||||
/* Wait for fifo to shift out some bytes */
|
||||
while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
|
||||
|
||||
*uart_tdr = (u8)c;
|
||||
}
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
{
|
||||
volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR);
|
||||
|
||||
while (!serial_tstc());
|
||||
|
||||
return *uart_rdr;
|
||||
}
|
||||
|
||||
int serial_tstc (void)
|
||||
{
|
||||
volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
|
||||
|
||||
if (*uart_lsr & UART_LSR_DR) {
|
||||
/* Data in rfifo */
|
||||
return (1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
273
package/uboot-xburst/files/cpu/mips/mmc_protocol.h
Normal file
273
package/uboot-xburst/files/cpu/mips/mmc_protocol.h
Normal file
@ -0,0 +1,273 @@
|
||||
/*
|
||||
**********************************************************************
|
||||
*
|
||||
* uC/MMC
|
||||
*
|
||||
* (c) Copyright 2005 - 2007, Ingenic Semiconductor, Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
***********************************************************************
|
||||
|
||||
----------------------------------------------------------------------
|
||||
File : mmc_protocol.h
|
||||
Purpose : MMC protocol definitions.
|
||||
|
||||
----------------------------------------------------------------------
|
||||
Version-Date-----Author-Explanation
|
||||
----------------------------------------------------------------------
|
||||
1.00.00 20060831 WeiJianli First release
|
||||
|
||||
----------------------------------------------------------------------
|
||||
Known problems or limitations with current version
|
||||
----------------------------------------------------------------------
|
||||
(none)
|
||||
---------------------------END-OF-HEADER------------------------------
|
||||
*/
|
||||
|
||||
#ifndef __MMC_PROTOCOL__
|
||||
#define __MMC_PROTOCOL__
|
||||
|
||||
/* Standard MMC/SD clock speeds */
|
||||
#define MMC_CLOCK_SLOW 400000 /* 400 kHz for initial setup */
|
||||
#define MMC_CLOCK_FAST 20000000 /* 20 MHz for maximum for normal operation */
|
||||
#define SD_CLOCK_FAST 24000000 /* 24 MHz for SD Cards */
|
||||
|
||||
/* Extra MMC commands for state control */
|
||||
/* Use negative numbers to disambiguate */
|
||||
#define MMC_CIM_RESET -1
|
||||
|
||||
/* Standard MMC commands (3.1) type argument response */
|
||||
/* class 1 */
|
||||
#define MMC_GO_IDLE_STATE 0 /* bc */
|
||||
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
|
||||
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
|
||||
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
|
||||
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
|
||||
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
|
||||
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
|
||||
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
|
||||
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
|
||||
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
|
||||
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
|
||||
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
|
||||
|
||||
/* class 2 */
|
||||
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
|
||||
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
|
||||
|
||||
/* class 3 */
|
||||
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
|
||||
|
||||
/* class 4 */
|
||||
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
|
||||
#define MMC_PROGRAM_CID 26 /* adtc R1 */
|
||||
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
|
||||
|
||||
/* class 6 */
|
||||
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
|
||||
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
|
||||
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
|
||||
|
||||
/* class 5 */
|
||||
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
|
||||
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
|
||||
#define MMC_ERASE 37 /* ac R1b */
|
||||
|
||||
/* class 9 */
|
||||
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
|
||||
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
|
||||
|
||||
/* class 7 */
|
||||
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
|
||||
|
||||
/* class 8 */
|
||||
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
|
||||
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1b */
|
||||
|
||||
/* SD class */
|
||||
#define SD_SEND_OP_COND 41 /* bcr [31:0] OCR R3 */
|
||||
#define SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
|
||||
#define SEND_SCR 51 /* adtc [31:0] staff R1 */
|
||||
|
||||
/* Don't change the order of these; they are used in dispatch tables */
|
||||
enum mmc_rsp_t {
|
||||
RESPONSE_NONE = 0,
|
||||
RESPONSE_R1 = 1,
|
||||
RESPONSE_R1B = 2,
|
||||
RESPONSE_R2_CID = 3,
|
||||
RESPONSE_R2_CSD = 4,
|
||||
RESPONSE_R3 = 5,
|
||||
RESPONSE_R4 = 6,
|
||||
RESPONSE_R5 = 7,
|
||||
RESPONSE_R6 = 8,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
MMC status in R1
|
||||
Type
|
||||
e : error bit
|
||||
s : status bit
|
||||
r : detected and set for the actual command response
|
||||
x : detected and set during command execution. the host must poll
|
||||
the card by sending status command in order to read these bits.
|
||||
Clear condition
|
||||
a : according to the card state
|
||||
b : always related to the previous command. Reception of
|
||||
a valid command will clear it (with a delay of one command)
|
||||
c : clear by read
|
||||
*/
|
||||
|
||||
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
|
||||
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
|
||||
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
|
||||
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
|
||||
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
|
||||
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
|
||||
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
|
||||
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
|
||||
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
|
||||
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
|
||||
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
|
||||
#define R1_CC_ERROR (1 << 20) /* erx, c */
|
||||
#define R1_ERROR (1 << 19) /* erx, c */
|
||||
#define R1_UNDERRUN (1 << 18) /* ex, c */
|
||||
#define R1_OVERRUN (1 << 17) /* ex, c */
|
||||
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
|
||||
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
|
||||
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
|
||||
#define R1_ERASE_RESET (1 << 13) /* sr, c */
|
||||
#define R1_STATUS(x) (x & 0xFFFFE000)
|
||||
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
|
||||
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
|
||||
#define R1_APP_CMD (1 << 7) /* sr, c */
|
||||
|
||||
enum card_state {
|
||||
CARD_STATE_EMPTY = -1,
|
||||
CARD_STATE_IDLE = 0,
|
||||
CARD_STATE_READY = 1,
|
||||
CARD_STATE_IDENT = 2,
|
||||
CARD_STATE_STBY = 3,
|
||||
CARD_STATE_TRAN = 4,
|
||||
CARD_STATE_DATA = 5,
|
||||
CARD_STATE_RCV = 6,
|
||||
CARD_STATE_PRG = 7,
|
||||
CARD_STATE_DIS = 8,
|
||||
};
|
||||
|
||||
/* These are unpacked versions of the actual responses */
|
||||
|
||||
struct mmc_response_r1 {
|
||||
u8 cmd;
|
||||
u32 status;
|
||||
};
|
||||
|
||||
typedef struct mmc_cid {
|
||||
u8 mid;
|
||||
u16 oid;
|
||||
u8 pnm[7]; /* Product name (we null-terminate) */
|
||||
u8 prv;
|
||||
u32 psn;
|
||||
u8 mdt;
|
||||
}mmc_cid_t;
|
||||
|
||||
typedef struct mmc_csd {
|
||||
u8 csd_structure;
|
||||
u8 spec_vers;
|
||||
u8 taac;
|
||||
u8 nsac;
|
||||
u8 tran_speed;
|
||||
u16 ccc;
|
||||
u8 read_bl_len;
|
||||
u8 read_bl_partial;
|
||||
u8 write_blk_misalign;
|
||||
u8 read_blk_misalign;
|
||||
u8 dsr_imp;
|
||||
u16 c_size;
|
||||
u8 vdd_r_curr_min;
|
||||
u8 vdd_r_curr_max;
|
||||
u8 vdd_w_curr_min;
|
||||
u8 vdd_w_curr_max;
|
||||
u8 c_size_mult;
|
||||
union {
|
||||
struct { /* MMC system specification version 3.1 */
|
||||
u8 erase_grp_size;
|
||||
u8 erase_grp_mult;
|
||||
} v31;
|
||||
struct { /* MMC system specification version 2.2 */
|
||||
u8 sector_size;
|
||||
u8 erase_grp_size;
|
||||
} v22;
|
||||
} erase;
|
||||
u8 wp_grp_size;
|
||||
u8 wp_grp_enable;
|
||||
u8 default_ecc;
|
||||
u8 r2w_factor;
|
||||
u8 write_bl_len;
|
||||
u8 write_bl_partial;
|
||||
u8 file_format_grp;
|
||||
u8 copy;
|
||||
u8 perm_write_protect;
|
||||
u8 tmp_write_protect;
|
||||
u8 file_format;
|
||||
u8 ecc;
|
||||
}mmc_csd_t;;
|
||||
|
||||
struct mmc_response_r3 {
|
||||
u32 ocr;
|
||||
};
|
||||
|
||||
#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
|
||||
#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
|
||||
#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
|
||||
#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
|
||||
#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
|
||||
#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
|
||||
#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
|
||||
#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
|
||||
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
|
||||
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
|
||||
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
|
||||
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
|
||||
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
|
||||
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
|
||||
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
|
||||
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
|
||||
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
|
||||
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
|
||||
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
|
||||
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
|
||||
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
|
||||
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
|
||||
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
||||
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
||||
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
|
||||
|
||||
|
||||
/* CSD field definitions */
|
||||
|
||||
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
|
||||
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
|
||||
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */
|
||||
|
||||
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
|
||||
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
|
||||
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
|
||||
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */
|
||||
|
||||
#if MMC_DEBUG_LEVEL
|
||||
|
||||
#define DEBUG(n, args...) \
|
||||
do { \
|
||||
if (n <= MMC_DEBUG_LEVEL) { \
|
||||
printf(args); \
|
||||
} \
|
||||
} while(0)
|
||||
#else
|
||||
#define DEBUG(n, args...)
|
||||
#endif /* MMC_DEBUG_EN */
|
||||
|
||||
#endif /* __MMC_PROTOCOL__ */
|
420
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c
Normal file
420
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.c
Normal file
@ -0,0 +1,420 @@
|
||||
/*
|
||||
* JzRISC lcd controller
|
||||
*
|
||||
* xiangfu liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <lcd.h>
|
||||
|
||||
#include <asm/io.h> /* virt_to_phys() */
|
||||
|
||||
#include <asm/jz4740.h>
|
||||
#include "nanonote_gpm940b0.h"
|
||||
|
||||
#define align2(n) (n)=((((n)+1)>>1)<<1)
|
||||
#define align4(n) (n)=((((n)+3)>>2)<<2)
|
||||
#define align8(n) (n)=((((n)+7)>>3)<<3)
|
||||
|
||||
struct jzfb_info {
|
||||
unsigned int cfg; /* panel mode and pin usage etc. */
|
||||
unsigned int w;
|
||||
unsigned int h;
|
||||
unsigned int bpp; /* bit per pixel */
|
||||
unsigned int fclk; /* frame clk */
|
||||
unsigned int hsw; /* hsync width, in pclk */
|
||||
unsigned int vsw; /* vsync width, in line count */
|
||||
unsigned int elw; /* end of line, in pclk */
|
||||
unsigned int blw; /* begin of line, in pclk */
|
||||
unsigned int efw; /* end of frame, in line count */
|
||||
unsigned int bfw; /* begin of frame, in line count */
|
||||
};
|
||||
|
||||
static struct jzfb_info jzfb = {
|
||||
MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
|
||||
320, 240, 32, 70, 1, 1, 273, 140, 1, 20
|
||||
};
|
||||
|
||||
vidinfo_t panel_info = {
|
||||
320, 240, LCD_BPP,
|
||||
};
|
||||
|
||||
int lcd_line_length;
|
||||
|
||||
int lcd_color_fg;
|
||||
int lcd_color_bg;
|
||||
/*
|
||||
* Frame buffer memory information
|
||||
*/
|
||||
void *lcd_base; /* Start of framebuffer memory */
|
||||
void *lcd_console_address; /* Start of console buffer */
|
||||
|
||||
short console_col;
|
||||
short console_row;
|
||||
|
||||
void lcd_ctrl_init (void *lcdbase);
|
||||
void lcd_enable (void);
|
||||
void lcd_disable (void);
|
||||
|
||||
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid);
|
||||
static void jz_lcd_desc_init(vidinfo_t *vid);
|
||||
static int jz_lcd_hw_init( vidinfo_t *vid );
|
||||
extern int flush_cache_all(void);
|
||||
|
||||
void lcd_ctrl_init (void *lcdbase)
|
||||
{
|
||||
__lcd_display_pin_init();
|
||||
|
||||
jz_lcd_init_mem(lcdbase, &panel_info);
|
||||
jz_lcd_desc_init(&panel_info);
|
||||
jz_lcd_hw_init(&panel_info);
|
||||
|
||||
__lcd_display_on() ;
|
||||
}
|
||||
|
||||
/*
|
||||
* Before enabled lcd controller, lcd registers should be configured correctly.
|
||||
*/
|
||||
|
||||
void lcd_enable (void)
|
||||
{
|
||||
REG_LCD_CTRL &= ~(1<<4); /* LCDCTRL.DIS */
|
||||
REG_LCD_CTRL |= 1<<3; /* LCDCTRL.ENA*/
|
||||
}
|
||||
|
||||
void lcd_disable (void)
|
||||
{
|
||||
REG_LCD_CTRL |= (1<<4); /* LCDCTRL.DIS, regular disable */
|
||||
/* REG_LCD_CTRL |= (1<<3); */ /* LCDCTRL.DIS, quikly disable */
|
||||
}
|
||||
|
||||
static int jz_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
|
||||
{
|
||||
u_long palette_mem_size;
|
||||
struct jz_fb_info *fbi = &vid->jz_fb;
|
||||
int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
|
||||
|
||||
fbi->screen = (u_long)lcdbase;
|
||||
fbi->palette_size = 256;
|
||||
palette_mem_size = fbi->palette_size * sizeof(u16);
|
||||
|
||||
debug("jz_lcd.c palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
|
||||
/* locate palette and descs at end of page following fb */
|
||||
fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void jz_lcd_desc_init(vidinfo_t *vid)
|
||||
{
|
||||
struct jz_fb_info * fbi;
|
||||
fbi = &vid->jz_fb;
|
||||
fbi->dmadesc_fblow = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
|
||||
fbi->dmadesc_fbhigh = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
|
||||
fbi->dmadesc_palette = (struct jz_fb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
|
||||
|
||||
#define BYTES_PER_PANEL (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)
|
||||
|
||||
/* populate descriptors */
|
||||
fbi->dmadesc_fblow->fdadr = virt_to_phys(fbi->dmadesc_fblow);
|
||||
fbi->dmadesc_fblow->fsadr = virt_to_phys((void *)(fbi->screen + BYTES_PER_PANEL));
|
||||
fbi->dmadesc_fblow->fidr = 0;
|
||||
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL / 4 ;
|
||||
|
||||
fbi->fdadr1 = virt_to_phys(fbi->dmadesc_fblow); /* only used in dual-panel mode */
|
||||
|
||||
fbi->dmadesc_fbhigh->fsadr = virt_to_phys((void *)fbi->screen);
|
||||
fbi->dmadesc_fbhigh->fidr = 0;
|
||||
fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL / 4; /* length in word */
|
||||
|
||||
fbi->dmadesc_palette->fsadr = virt_to_phys((void *)fbi->palette);
|
||||
fbi->dmadesc_palette->fidr = 0;
|
||||
fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2)/4 | (1<<28);
|
||||
|
||||
if(NBITS(vid->vl_bpix) < 12)
|
||||
{
|
||||
/* assume any mode with <12 bpp is palette driven */
|
||||
fbi->dmadesc_palette->fdadr = virt_to_phys(fbi->dmadesc_fbhigh);
|
||||
fbi->dmadesc_fbhigh->fdadr = virt_to_phys(fbi->dmadesc_palette);
|
||||
/* flips back and forth between pal and fbhigh */
|
||||
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_palette);
|
||||
} else {
|
||||
/* palette shouldn't be loaded in true-color mode */
|
||||
fbi->dmadesc_fbhigh->fdadr = virt_to_phys((void *)fbi->dmadesc_fbhigh);
|
||||
fbi->fdadr0 = virt_to_phys(fbi->dmadesc_fbhigh); /* no pal just fbhigh */
|
||||
}
|
||||
|
||||
flush_cache_all();
|
||||
}
|
||||
|
||||
static int jz_lcd_hw_init(vidinfo_t *vid)
|
||||
{
|
||||
struct jz_fb_info *fbi = &vid->jz_fb;
|
||||
unsigned int val = 0;
|
||||
unsigned int pclk;
|
||||
unsigned int stnH;
|
||||
int pll_div;
|
||||
|
||||
/* Setting Control register */
|
||||
switch (jzfb.bpp) {
|
||||
case 1:
|
||||
val |= LCD_CTRL_BPP_1;
|
||||
break;
|
||||
case 2:
|
||||
val |= LCD_CTRL_BPP_2;
|
||||
break;
|
||||
case 4:
|
||||
val |= LCD_CTRL_BPP_4;
|
||||
break;
|
||||
case 8:
|
||||
val |= LCD_CTRL_BPP_8;
|
||||
break;
|
||||
case 15:
|
||||
val |= LCD_CTRL_RGB555;
|
||||
case 16:
|
||||
val |= LCD_CTRL_BPP_16;
|
||||
break;
|
||||
case 17 ... 32:
|
||||
val |= LCD_CTRL_BPP_18_24; /* target is 4bytes/pixel */
|
||||
break;
|
||||
|
||||
default:
|
||||
printf("jz_lcd.c The BPP %d is not supported\n", jzfb.bpp);
|
||||
val |= LCD_CTRL_BPP_16;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_STN_MONO_DUAL:
|
||||
case MODE_STN_COLOR_DUAL:
|
||||
case MODE_STN_MONO_SINGLE:
|
||||
case MODE_STN_COLOR_SINGLE:
|
||||
switch (jzfb.bpp) {
|
||||
case 1:
|
||||
/* val |= LCD_CTRL_PEDN; */
|
||||
case 2:
|
||||
val |= LCD_CTRL_FRC_2;
|
||||
break;
|
||||
case 4:
|
||||
val |= LCD_CTRL_FRC_4;
|
||||
break;
|
||||
case 8:
|
||||
default:
|
||||
val |= LCD_CTRL_FRC_16;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
val |= LCD_CTRL_BST_16; /* Burst Length is 16WORD=64Byte */
|
||||
val |= LCD_CTRL_OFUP; /* OutFIFO underrun protect */
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_STN_MONO_DUAL:
|
||||
case MODE_STN_COLOR_DUAL:
|
||||
case MODE_STN_MONO_SINGLE:
|
||||
case MODE_STN_COLOR_SINGLE:
|
||||
switch (jzfb.cfg & STN_DAT_PINMASK) {
|
||||
case STN_DAT_PIN1:
|
||||
/* Do not adjust the hori-param value. */
|
||||
break;
|
||||
case STN_DAT_PIN2:
|
||||
align2(jzfb.hsw);
|
||||
align2(jzfb.elw);
|
||||
align2(jzfb.blw);
|
||||
break;
|
||||
case STN_DAT_PIN4:
|
||||
align4(jzfb.hsw);
|
||||
align4(jzfb.elw);
|
||||
align4(jzfb.blw);
|
||||
break;
|
||||
case STN_DAT_PIN8:
|
||||
align8(jzfb.hsw);
|
||||
align8(jzfb.elw);
|
||||
align8(jzfb.blw);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
REG_LCD_CTRL = val;
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_STN_MONO_DUAL:
|
||||
case MODE_STN_COLOR_DUAL:
|
||||
case MODE_STN_MONO_SINGLE:
|
||||
case MODE_STN_COLOR_SINGLE:
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
|
||||
stnH = jzfb.h >> 1;
|
||||
else
|
||||
stnH = jzfb.h;
|
||||
|
||||
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
|
||||
REG_LCD_HSYNC = ((jzfb.blw+jzfb.w) << 16) | (jzfb.blw+jzfb.w+jzfb.hsw);
|
||||
|
||||
/* Screen setting */
|
||||
REG_LCD_VAT = ((jzfb.blw + jzfb.w + jzfb.hsw + jzfb.elw) << 16) | (stnH + jzfb.vsw + jzfb.bfw + jzfb.efw);
|
||||
REG_LCD_DAH = (jzfb.blw << 16) | (jzfb.blw + jzfb.w);
|
||||
REG_LCD_DAV = (0 << 16) | (stnH);
|
||||
|
||||
/* AC BIAs signal */
|
||||
REG_LCD_PS = (0 << 16) | (stnH+jzfb.vsw+jzfb.efw+jzfb.bfw);
|
||||
|
||||
break;
|
||||
|
||||
case MODE_TFT_GEN:
|
||||
case MODE_TFT_SHARP:
|
||||
case MODE_TFT_CASIO:
|
||||
case MODE_TFT_SAMSUNG:
|
||||
case MODE_8BIT_SERIAL_TFT:
|
||||
case MODE_TFT_18BIT:
|
||||
REG_LCD_VSYNC = (0 << 16) | jzfb.vsw;
|
||||
REG_LCD_HSYNC = (0 << 16) | jzfb.hsw;
|
||||
REG_LCD_DAV =((jzfb.vsw+jzfb.bfw) << 16) | (jzfb.vsw +jzfb.bfw+jzfb.h);
|
||||
REG_LCD_DAH = ((jzfb.hsw + jzfb.blw) << 16) | (jzfb.hsw + jzfb.blw + jzfb.w );
|
||||
REG_LCD_VAT = (((jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw)) << 16) \
|
||||
| (jzfb.vsw + jzfb.bfw + jzfb.h + jzfb.efw);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (jzfb.cfg & MODE_MASK) {
|
||||
case MODE_TFT_SAMSUNG:
|
||||
{
|
||||
unsigned int total, tp_s, tp_e, ckv_s, ckv_e;
|
||||
unsigned int rev_s, rev_e, inv_s, inv_e;
|
||||
|
||||
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
|
||||
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
|
||||
|
||||
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
|
||||
tp_s = jzfb.blw + jzfb.w + 1;
|
||||
tp_e = tp_s + 1;
|
||||
/* ckv_s = tp_s - jz_clocks.pixclk/(1000000000/4100); */
|
||||
ckv_s = tp_s - pclk/(1000000000/4100);
|
||||
ckv_e = tp_s + total;
|
||||
rev_s = tp_s - 11; /* -11.5 clk */
|
||||
rev_e = rev_s + total;
|
||||
inv_s = tp_s;
|
||||
inv_e = inv_s + total;
|
||||
REG_LCD_CLS = (tp_s << 16) | tp_e;
|
||||
REG_LCD_PS = (ckv_s << 16) | ckv_e;
|
||||
REG_LCD_SPL = (rev_s << 16) | rev_e;
|
||||
REG_LCD_REV = (inv_s << 16) | inv_e;
|
||||
jzfb.cfg |= STFT_REVHI | STFT_SPLHI;
|
||||
break;
|
||||
}
|
||||
case MODE_TFT_SHARP:
|
||||
{
|
||||
unsigned int total, cls_s, cls_e, ps_s, ps_e;
|
||||
unsigned int spl_s, spl_e, rev_s, rev_e;
|
||||
total = jzfb.blw + jzfb.w + jzfb.elw + jzfb.hsw;
|
||||
spl_s = 1;
|
||||
spl_e = spl_s + 1;
|
||||
cls_s = 0;
|
||||
cls_e = total - 60; /* > 4us (pclk = 80ns) */
|
||||
ps_s = cls_s;
|
||||
ps_e = cls_e;
|
||||
rev_s = total - 40; /* > 3us (pclk = 80ns) */
|
||||
rev_e = rev_s + total;
|
||||
jzfb.cfg |= STFT_PSHI;
|
||||
REG_LCD_SPL = (spl_s << 16) | spl_e;
|
||||
REG_LCD_CLS = (cls_s << 16) | cls_e;
|
||||
REG_LCD_PS = (ps_s << 16) | ps_e;
|
||||
REG_LCD_REV = (rev_s << 16) | rev_e;
|
||||
break;
|
||||
}
|
||||
case MODE_TFT_CASIO:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Configure the LCD panel */
|
||||
REG_LCD_CFG = jzfb.cfg;
|
||||
|
||||
/* Timing setting */
|
||||
__cpm_stop_lcd();
|
||||
|
||||
val = jzfb.fclk; /* frame clk */
|
||||
if ( (jzfb.cfg & MODE_MASK) != MODE_8BIT_SERIAL_TFT) {
|
||||
pclk = val * (jzfb.w + jzfb.hsw + jzfb.elw + jzfb.blw) *
|
||||
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
|
||||
} else {
|
||||
/* serial mode: Hsync period = 3*Width_Pixel */
|
||||
pclk = val * (jzfb.w*3 + jzfb.hsw + jzfb.elw + jzfb.blw) *
|
||||
(jzfb.h + jzfb.vsw + jzfb.efw + jzfb.bfw); /* Pixclk */
|
||||
}
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL))
|
||||
pclk = (pclk * 3);
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_SINGLE) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_SINGLE) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
||||
pclk = pclk >> ((jzfb.cfg & STN_DAT_PINMASK) >> 4);
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
||||
pclk >>= 1;
|
||||
|
||||
pll_div = ( REG_CPM_CPCCR & CPM_CPCCR_PCS ); /* clock source,0:pllout/2 1: pllout */
|
||||
pll_div = pll_div ? 1 : 2 ;
|
||||
val = ( __cpm_get_pllout()/pll_div ) / pclk;
|
||||
val--;
|
||||
if ( val > 0x1ff ) {
|
||||
printf("CPM_LPCDR too large, set it to 0x1ff\n");
|
||||
val = 0x1ff;
|
||||
}
|
||||
__cpm_set_pixdiv(val);
|
||||
|
||||
val = pclk * 3 ; /* LCDClock > 2.5*Pixclock */
|
||||
if ( val > 150000000 ) {
|
||||
printf("Warning: LCDClock=%d\n, LCDClock must less or equal to 150MHz.\n", val);
|
||||
printf("Change LCDClock to 150MHz\n");
|
||||
val = 150000000;
|
||||
}
|
||||
val = ( __cpm_get_pllout()/pll_div ) / val;
|
||||
val--;
|
||||
if ( val > 0x1f ) {
|
||||
printf("CPM_CPCCR.LDIV too large, set it to 0x1f\n");
|
||||
val = 0x1f;
|
||||
}
|
||||
__cpm_set_ldiv( val );
|
||||
REG_CPM_CPCCR |= CPM_CPCCR_CE ; /* update divide */
|
||||
|
||||
__cpm_start_lcd();
|
||||
udelay(1000);
|
||||
|
||||
REG_LCD_DA0 = fbi->fdadr0; /* frame descripter*/
|
||||
|
||||
if (((jzfb.cfg & MODE_MASK) == MODE_STN_COLOR_DUAL) ||
|
||||
((jzfb.cfg & MODE_MASK) == MODE_STN_MONO_DUAL))
|
||||
REG_LCD_DA1 = fbi->fdadr1; /* frame descripter*/
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
|
||||
{
|
||||
}
|
||||
|
||||
void lcd_initcolregs (void)
|
||||
{
|
||||
}
|
231
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h
Normal file
231
package/uboot-xburst/files/cpu/mips/nanonote_gpm940b0.h
Normal file
@ -0,0 +1,231 @@
|
||||
/*
|
||||
* JzRISC lcd controller
|
||||
*
|
||||
* xiangfu liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __QI_LB60_GPM940B0_H__
|
||||
#define __QI_LB60_GPM940B0_H__
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#define mdelay(n) udelay((n)*1000)
|
||||
|
||||
#define NR_PALETTE 256
|
||||
|
||||
struct lcd_desc{
|
||||
unsigned int next_desc; /* LCDDAx */
|
||||
unsigned int databuf; /* LCDSAx */
|
||||
unsigned int frame_id; /* LCDFIDx */
|
||||
unsigned int cmd; /* LCDCMDx */
|
||||
};
|
||||
|
||||
#define MODE_MASK 0x0f
|
||||
#define MODE_TFT_GEN 0x00
|
||||
#define MODE_TFT_SHARP 0x01
|
||||
#define MODE_TFT_CASIO 0x02
|
||||
#define MODE_TFT_SAMSUNG 0x03
|
||||
#define MODE_CCIR656_NONINT 0x04
|
||||
#define MODE_CCIR656_INT 0x05
|
||||
#define MODE_STN_COLOR_SINGLE 0x08
|
||||
#define MODE_STN_MONO_SINGLE 0x09
|
||||
#define MODE_STN_COLOR_DUAL 0x0a
|
||||
#define MODE_STN_MONO_DUAL 0x0b
|
||||
#define MODE_8BIT_SERIAL_TFT 0x0c
|
||||
|
||||
#define MODE_TFT_18BIT (1<<7)
|
||||
|
||||
#define STN_DAT_PIN1 (0x00 << 4)
|
||||
#define STN_DAT_PIN2 (0x01 << 4)
|
||||
#define STN_DAT_PIN4 (0x02 << 4)
|
||||
#define STN_DAT_PIN8 (0x03 << 4)
|
||||
#define STN_DAT_PINMASK STN_DAT_PIN8
|
||||
|
||||
#define STFT_PSHI (1 << 15)
|
||||
#define STFT_CLSHI (1 << 14)
|
||||
#define STFT_SPLHI (1 << 13)
|
||||
#define STFT_REVHI (1 << 12)
|
||||
|
||||
#define SYNC_MASTER (0 << 16)
|
||||
#define SYNC_SLAVE (1 << 16)
|
||||
|
||||
#define DE_P (0 << 9)
|
||||
#define DE_N (1 << 9)
|
||||
|
||||
#define PCLK_P (0 << 10)
|
||||
#define PCLK_N (1 << 10)
|
||||
|
||||
#define HSYNC_P (0 << 11)
|
||||
#define HSYNC_N (1 << 11)
|
||||
|
||||
#define VSYNC_P (0 << 8)
|
||||
#define VSYNC_N (1 << 8)
|
||||
|
||||
#define DATA_NORMAL (0 << 17)
|
||||
#define DATA_INVERSE (1 << 17)
|
||||
|
||||
|
||||
/* Jz LCDFB supported I/O controls. */
|
||||
#define FBIOSETBACKLIGHT 0x4688
|
||||
#define FBIODISPON 0x4689
|
||||
#define FBIODISPOFF 0x468a
|
||||
#define FBIORESET 0x468b
|
||||
#define FBIOPRINT_REG 0x468c
|
||||
|
||||
/*
|
||||
* LCD panel specific definition
|
||||
*/
|
||||
#define MODE 0xc9 /* 8bit serial RGB */
|
||||
#define SPEN (32*2+21) /*LCD_SPL */
|
||||
#define SPCK (32*2+23) /*LCD_CLS */
|
||||
#define SPDA (32*2+22) /*LCD_D12 */
|
||||
#define LCD_RET (32*3+27)
|
||||
|
||||
#define __spi_write_reg1(reg, val) \
|
||||
do { \
|
||||
unsigned char no;\
|
||||
unsigned short value;\
|
||||
unsigned char a=0;\
|
||||
unsigned char b=0;\
|
||||
a=reg;\
|
||||
b=val;\
|
||||
__gpio_set_pin(SPEN);\
|
||||
__gpio_set_pin(SPCK);\
|
||||
__gpio_clear_pin(SPDA);\
|
||||
__gpio_clear_pin(SPEN);\
|
||||
udelay(25);\
|
||||
value=((a<<8)|(b&0xFF));\
|
||||
for(no=0;no<16;no++)\
|
||||
{\
|
||||
__gpio_clear_pin(SPCK);\
|
||||
if((value&0x8000)==0x8000)\
|
||||
__gpio_set_pin(SPDA);\
|
||||
else\
|
||||
__gpio_clear_pin(SPDA);\
|
||||
udelay(25);\
|
||||
__gpio_set_pin(SPCK);\
|
||||
value=(value<<1); \
|
||||
udelay(25);\
|
||||
}\
|
||||
__gpio_set_pin(SPEN);\
|
||||
udelay(100);\
|
||||
} while (0)
|
||||
|
||||
#define __spi_write_reg(reg, val) \
|
||||
do {\
|
||||
__spi_write_reg1((reg<<2|2), val);\
|
||||
udelay(100); \
|
||||
}while(0)
|
||||
|
||||
#define __lcd_special_pin_init() \
|
||||
do { \
|
||||
__gpio_as_output(SPEN); /* use SPDA */\
|
||||
__gpio_as_output(SPCK); /* use SPCK */\
|
||||
__gpio_as_output(SPDA); /* use SPDA */\
|
||||
__gpio_as_output(LCD_RET);\
|
||||
} while (0)
|
||||
|
||||
#define __lcd_special_on() \
|
||||
do { \
|
||||
udelay(50);\
|
||||
__spi_write_reg1(0x05, 0x16); \
|
||||
__spi_write_reg1(0x04, 0x0b); \
|
||||
__spi_write_reg1(0x07, 0x8d); \
|
||||
__spi_write_reg1(0x01, 0x95); \
|
||||
__spi_write_reg1(0x08, 0xc0); \
|
||||
__spi_write_reg1(0x03, 0x40); \
|
||||
__spi_write_reg1(0x06, 0x75); \
|
||||
__spi_write_reg1(0x13, 0x01); \
|
||||
__spi_write_reg1(0x05, 0x57); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_special_off() \
|
||||
do { \
|
||||
__spi_write_reg1(0x05, 0x5e); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_pin_init() \
|
||||
do { \
|
||||
__lcd_special_pin_init();\
|
||||
__gpio_as_pwm();\
|
||||
__lcd_set_backlight_level(8);\
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_on() \
|
||||
do { \
|
||||
__lcd_set_backlight_level(8); \
|
||||
__lcd_special_on();\
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_off() \
|
||||
do { \
|
||||
__lcd_set_backlight_level(0); \
|
||||
__lcd_special_off();\
|
||||
} while (0)
|
||||
|
||||
#define __lcd_set_backlight_level(n)\
|
||||
do { \
|
||||
__gpio_as_output(LCD_RET); \
|
||||
__gpio_set_pin(LCD_RET); \
|
||||
} while (0)
|
||||
|
||||
#if defined(CONFIG_SAKC)
|
||||
#define __lcd_close_backlight() \
|
||||
do { \
|
||||
__gpio_as_output(GPIO_PWM); \
|
||||
__gpio_clear_pin(GPIO_PWM); \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SAKC)
|
||||
#define __lcd_display_pin_init() \
|
||||
do { \
|
||||
__cpm_start_tcu(); \
|
||||
__lcd_special_pin_init(); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_on() \
|
||||
do { \
|
||||
__lcd_special_on(); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_off() \
|
||||
do { \
|
||||
__lcd_special_off(); \
|
||||
} while (0)
|
||||
#else
|
||||
#define __lcd_display_pin_init() \
|
||||
do { \
|
||||
__cpm_start_tcu(); \
|
||||
__lcd_special_pin_init(); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_on() \
|
||||
do { \
|
||||
__gpio_set_pin(GPIO_DISP_OFF_N); \
|
||||
__lcd_special_on(); \
|
||||
} while (0)
|
||||
|
||||
#define __lcd_display_off() \
|
||||
do { \
|
||||
__lcd_special_off(); \
|
||||
__gpio_clear_pin(GPIO_DISP_OFF_N); \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#endif /* __QI_LB60_GPM940B0_H__ */
|
880
package/uboot-xburst/files/cpu/mips/usb_boot.S
Normal file
880
package/uboot-xburst/files/cpu/mips/usb_boot.S
Normal file
@ -0,0 +1,880 @@
|
||||
/*
|
||||
* for jz4740 usb boot
|
||||
*
|
||||
* Copyright (c) 2009 Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
.set noreorder
|
||||
.globl usb_boot
|
||||
.text
|
||||
|
||||
//----------------------------------------------------------------------
|
||||
// Both NAND and USB boot load data to D-Cache first, then transfer
|
||||
// data from D-Cache to I-Cache, and jump to execute the code in I-Cache.
|
||||
// So init caches first and then dispatch to a proper boot routine.
|
||||
//----------------------------------------------------------------------
|
||||
|
||||
.macro load_addr reg addr
|
||||
li \reg, 0x80000000
|
||||
addiu \reg, \reg, \addr
|
||||
la $2, usbboot_begin
|
||||
subu \reg, \reg, $2
|
||||
.endm
|
||||
|
||||
usb_boot:
|
||||
//--------------------------------------------------------------
|
||||
// Initialize PLL: set ICLK to 84MHz and HCLK to 42MHz.
|
||||
//--------------------------------------------------------------
|
||||
la $9, 0xB0000000 // CPCCR: Clock Control Register
|
||||
la $8, 0x42041110 // I:S:M:P=1:2:2:2
|
||||
sw $8, 0($9)
|
||||
|
||||
la $9, 0xB0000010 // CPPCR: PLL Control Register
|
||||
la $8, 0x06000120 // M=12 N=0 D=0 CLK=12*(M+2)/(N+2)
|
||||
sw $8, 0($9)
|
||||
|
||||
mtc0 $0, $26 // CP0_ERRCTL, restore WST reset state
|
||||
nop
|
||||
|
||||
mtc0 $0, $16 // CP0_CONFIG
|
||||
nop
|
||||
|
||||
// Relocate code to beginning of the ram
|
||||
|
||||
la $2, usbboot_begin
|
||||
la $3, usbboot_end
|
||||
li $4, 0x80000000
|
||||
|
||||
1:
|
||||
lw $5, 0($2)
|
||||
sw $5, 0($4)
|
||||
addiu $2, $2, 4
|
||||
bne $2, $3, 1b
|
||||
addiu $4, $4, 4
|
||||
|
||||
li $2, 0x80000000
|
||||
ori $3, $2, 0
|
||||
addiu $3, $3, usbboot_end
|
||||
la $4, usbboot_begin
|
||||
subu $3, $3, $4
|
||||
|
||||
|
||||
2:
|
||||
cache 0x0, 0($2) // Index_Invalidate_I
|
||||
cache 0x1, 0($2) // Index_Writeback_Inv_D
|
||||
addiu $2, $2, 32
|
||||
subu $4, $3, $2
|
||||
bgtz $4, 2b
|
||||
nop
|
||||
|
||||
load_addr $3, usb_boot_return
|
||||
|
||||
jr $3
|
||||
|
||||
usbboot_begin:
|
||||
|
||||
init_caches:
|
||||
li $2, 3 // cacheable for kseg0 access
|
||||
mtc0 $2, $16 // CP0_CONFIG
|
||||
nop
|
||||
|
||||
li $2, 0x20000000 // enable idx-store-data cache insn
|
||||
mtc0 $2, $26 // CP0_ERRCTL
|
||||
|
||||
ori $2, $28, 0 // start address
|
||||
ori $3, $2, 0x3fe0 // end address, total 16KB
|
||||
mtc0 $0, $28, 0 // CP0_TAGLO
|
||||
mtc0 $0, $28, 1 // CP0_DATALO
|
||||
cache_clear_a_line:
|
||||
cache 0x8, 0($2) // Index_Store_Tag_I
|
||||
cache 0x9, 0($2) // Index_Store_Tag_D
|
||||
bne $2, $3, cache_clear_a_line
|
||||
addiu $2, $2, 32 // increment CACHE_LINE_SIZE
|
||||
|
||||
ori $2, $28, 0 // start address
|
||||
ori $3, $2, 0x3fe0 // end address, total 16KB
|
||||
la $4, 0x1ffff000 // physical address and 4KB page mask
|
||||
cache_alloc_a_line:
|
||||
and $5, $2, $4
|
||||
ori $5, $5, 1 // V bit of the physical tag
|
||||
mtc0 $5, $28, 0 // CP0_TAGLO
|
||||
cache 0x8, 0($2) // Index_Store_Tag_I
|
||||
cache 0x9, 0($2) // Index_Store_Tag_D
|
||||
bne $2, $3, cache_alloc_a_line
|
||||
addiu $2, $2, 32 // increment CACHE_LINE_SIZE
|
||||
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
//--------------------------------------------------------------
|
||||
// Transfer data from dcache to icache, then jump to icache.
|
||||
//
|
||||
// Input parameters:
|
||||
//
|
||||
// $19: data length in bytes
|
||||
// $20: jump target address
|
||||
//--------------------------------------------------------------
|
||||
xfer_d2i:
|
||||
|
||||
ori $8, $20, 0
|
||||
addu $9, $8, $19 // total 16KB
|
||||
|
||||
1:
|
||||
cache 0x0, 0($8) // Index_Invalidate_I
|
||||
cache 0x1, 0($8) // Index_Writeback_Inv_D
|
||||
bne $8, $9, 1b
|
||||
addiu $8, $8, 32
|
||||
|
||||
// flush write-buffer
|
||||
sync
|
||||
|
||||
// Invalidate BTB
|
||||
mfc0 $8, $16, 7 // CP0_CONFIG
|
||||
nop
|
||||
ori $8, 2
|
||||
mtc0 $8, $16, 7
|
||||
nop
|
||||
|
||||
// Overwrite config to disable ram initalisation
|
||||
li $2, 0xff
|
||||
sb $2, 20($20)
|
||||
|
||||
jalr $20
|
||||
nop
|
||||
|
||||
icache_return:
|
||||
//--------------------------------------------------------------
|
||||
// User code can return to here after executing itself in
|
||||
// icache, by jumping to $31.
|
||||
//--------------------------------------------------------------
|
||||
b usb_boot_return
|
||||
nop
|
||||
|
||||
|
||||
usb_boot_return:
|
||||
//--------------------------------------------------------------
|
||||
// Enable the USB PHY
|
||||
//--------------------------------------------------------------
|
||||
la $9, 0xB0000024 // CPM_SCR
|
||||
lw $8, 0($9)
|
||||
ori $8, 0x40 // USBPHY_ENABLE
|
||||
sw $8, 0($9)
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Initialize USB registers
|
||||
//--------------------------------------------------------------
|
||||
la $27, 0xb3040000 // USB registers base address
|
||||
|
||||
sb $0, 0x0b($27) // INTRUSBE: disable common USB interrupts
|
||||
sh $0, 0x06($27) // INTRINE: disable EPIN interrutps
|
||||
sh $0, 0x08($27) // INTROUTE: disable EPOUT interrutps
|
||||
|
||||
li $9, 0x61
|
||||
sb $9, 0x01($27) // POWER: HSENAB | SUSPENDM | SOFTCONN
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Initialize USB states
|
||||
//--------------------------------------------------------------
|
||||
li $22, 0 // set EP0 to IDLE state
|
||||
li $23, 1 // no data stage
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Main loop of polling the usb commands
|
||||
//--------------------------------------------------------------
|
||||
usb_command_loop:
|
||||
lbu $9, 0x0a($27) // read INTRUSB
|
||||
andi $9, 0x04 // check USB_INTR_RESET
|
||||
beqz $9, check_intr_ep0in
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 1. Handle USB reset interrupt
|
||||
//--------------------------------------------------------------
|
||||
handle_reset_intr:
|
||||
lbu $9, 0x01($27) // read POWER
|
||||
andi $9, 0x10 // test HS_MODE
|
||||
bnez $9, _usb_set_maxpktsize
|
||||
li $9, 512 // max packet size of HS mode
|
||||
li $9, 64 // max packet size of FS mode
|
||||
|
||||
_usb_set_maxpktsize:
|
||||
li $8, 1
|
||||
sb $8, 0x0e($27) // set INDEX 1
|
||||
|
||||
sh $9, 0x10($27) // INMAXP
|
||||
sb $0, 0x13($27) // INCSRH
|
||||
sh $9, 0x14($27) // OUTMAXP
|
||||
sb $0, 0x17($27) // OUTCSRH
|
||||
|
||||
_usb_flush_fifo:
|
||||
li $8, 0x48 // INCSR_CDT && INCSR_FF
|
||||
sb $8, 0x12($27) // INCSR
|
||||
li $8, 0x90 // OUTCSR_CDT && OUTCSR_FF
|
||||
sb $8, 0x16($27) // OUTCSR
|
||||
|
||||
li $22, 0 // set EP0 to IDLE state
|
||||
li $23, 1 // no data stage
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 2. Check and handle EP0 interrupt
|
||||
//--------------------------------------------------------------
|
||||
check_intr_ep0in:
|
||||
lhu $10, 0x02($27) // read INTRIN
|
||||
andi $9, $10, 0x1 // check EP0 interrupt
|
||||
beqz $9, check_intr_ep1in
|
||||
nop
|
||||
|
||||
handle_ep0_intr:
|
||||
sb $0, 0x0e($27) // set INDEX 0
|
||||
lbu $11, 0x12($27) // read CSR0
|
||||
|
||||
andi $9, $11, 0x04 // check SENTSTALL
|
||||
beqz $9, _ep0_setupend
|
||||
nop
|
||||
|
||||
_ep0_sentstall:
|
||||
andi $9, $11, 0xdb
|
||||
sb $9, 0x12($27) // clear SENDSTALL and SENTSTALL
|
||||
li $22, 0 // set EP0 to IDLE state
|
||||
|
||||
_ep0_setupend:
|
||||
andi $9, $11, 0x10 // check SETUPEND
|
||||
beqz $9, ep0_idle_state
|
||||
nop
|
||||
|
||||
ori $9, $11, 0x80
|
||||
sb $9, 0x12($27) // set SVDSETUPEND
|
||||
li $22, 0 // set EP0 to IDLE state
|
||||
|
||||
ep0_idle_state:
|
||||
bnez $22, ep0_tx_state
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 2.1 Handle EP0 IDLE state interrupt
|
||||
//--------------------------------------------------------------
|
||||
andi $9, $11, 0x01 // check OUTPKTRDY
|
||||
beqz $9, check_intr_ep1in
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Read 8-bytes setup packet from the FIFO
|
||||
//--------------------------------------------------------------
|
||||
lw $25, 0x20($27) // first word of setup packet
|
||||
lw $26, 0x20($27) // second word of setup packet
|
||||
|
||||
andi $9, $25, 0x60 // bRequestType & USB_TYPE_MASK
|
||||
beqz $9, _ep0_std_req
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 2.1.1 Vendor-specific setup request
|
||||
//--------------------------------------------------------------
|
||||
_ep0_vend_req:
|
||||
li $22, 0 // set EP0 to IDLE state
|
||||
li $23, 1 // NoData = 1
|
||||
|
||||
andi $9, $25, 0xff00 // check bRequest
|
||||
srl $9, $9, 8
|
||||
beqz $9, __ep0_get_cpu_info
|
||||
sub $8, $9, 0x1
|
||||
beqz $8, __ep0_set_data_address
|
||||
sub $8, $9, 0x2
|
||||
beqz $8, __ep0_set_data_length
|
||||
sub $8, $9, 0x3
|
||||
beqz $8, __ep0_flush_caches
|
||||
sub $8, $9, 0x4
|
||||
beqz $8, __ep0_prog_start1
|
||||
sub $8, $9, 0x5
|
||||
beqz $8, __ep0_prog_start2
|
||||
nop
|
||||
b _ep0_idle_state_fini // invalid request
|
||||
nop
|
||||
|
||||
__ep0_get_cpu_info:
|
||||
load_addr $20, cpu_info_data // data pointer to transfer
|
||||
li $21, 8 // bytes left to transfer
|
||||
li $22, 1 // set EP0 to TX state
|
||||
li $23, 0 // NoData = 0
|
||||
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
__ep0_set_data_address:
|
||||
li $9, 0xffff0000
|
||||
and $9, $25, $9
|
||||
andi $8, $26, 0xffff
|
||||
or $20, $9, $8 // data address of next transfer
|
||||
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
__ep0_set_data_length:
|
||||
li $9, 0xffff0000
|
||||
and $9, $25, $9
|
||||
andi $8, $26, 0xffff
|
||||
or $21, $9, $8 // data length of next transfer
|
||||
|
||||
li $9, 0x48 // SVDOUTPKTRDY and DATAEND
|
||||
sb $9, 0x12($27) // CSR0
|
||||
|
||||
// We must write packet to FIFO before EP1-IN interrupt here.
|
||||
b handle_epin1_intr
|
||||
nop
|
||||
|
||||
__ep0_flush_caches:
|
||||
// Flush dcache and invalidate icache.
|
||||
li $8, 0x80000000
|
||||
addi $9, $8, 0x3fe0 // total 16KB
|
||||
|
||||
1:
|
||||
cache 0x0, 0($8) // Index_Invalidate_I
|
||||
cache 0x1, 0($8) // Index_Writeback_Inv_D
|
||||
bne $8, $9, 1b
|
||||
addiu $8, $8, 32
|
||||
|
||||
// flush write-buffer
|
||||
sync
|
||||
|
||||
// Invalidate BTB
|
||||
mfc0 $8, $16, 7 // CP0_CONFIG
|
||||
nop
|
||||
ori $8, 2
|
||||
mtc0 $8, $16, 7
|
||||
nop
|
||||
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
__ep0_prog_start1:
|
||||
li $9, 0x48 // SVDOUTPKTRDY and DATAEND
|
||||
sb $9, 0x12($27) // CSR0
|
||||
|
||||
li $9, 0xffff0000
|
||||
and $9, $25, $9
|
||||
andi $8, $26, 0xffff
|
||||
or $20, $9, $8 // target address
|
||||
|
||||
b xfer_d2i
|
||||
li $19, 0x2000 // 16KB data length
|
||||
|
||||
__ep0_prog_start2:
|
||||
li $9, 0x48 // SVDOUTPKTRDY and DATAEND
|
||||
sb $9, 0x12($27) // CSR0
|
||||
|
||||
li $9, 0xffff0000
|
||||
and $9, $25, $9
|
||||
andi $8, $26, 0xffff
|
||||
or $20, $9, $8 // target address
|
||||
|
||||
jalr $20 // jump, and place the return address in $31
|
||||
nop
|
||||
|
||||
__ep0_prog_start2_return:
|
||||
// User code can return to here after executing itself, by jumping to $31.
|
||||
b usb_boot_return
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 2.1.2 Standard setup request
|
||||
//--------------------------------------------------------------
|
||||
_ep0_std_req:
|
||||
andi $12, $25, 0xff00 // check bRequest
|
||||
srl $12, $12, 8
|
||||
sub $9, $12, 0x05 // check USB_REQ_SET_ADDRESS
|
||||
bnez $9, __ep0_req_set_config
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Handle USB_REQ_SET_ADDRESS
|
||||
//--------------------------------------------------------------
|
||||
__ep0_req_set_addr:
|
||||
srl $9, $25, 16 // get wValue
|
||||
sb $9, 0x0($27) // set FADDR
|
||||
li $23, 1 // NoData = 1
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
__ep0_req_set_config:
|
||||
sub $9, $12, 0x09 // check USB_REQ_SET_CONFIGURATION
|
||||
bnez $9, __ep0_req_get_desc
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Handle USB_REQ_SET_CONFIGURATION
|
||||
//--------------------------------------------------------------
|
||||
li $23, 1 // NoData = 1
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
__ep0_req_get_desc:
|
||||
sub $9, $12, 0x06 // check USB_REQ_GET_DESCRIPTOR
|
||||
bnez $9, _ep0_idle_state_fini
|
||||
li $23, 1 // NoData = 1
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Handle USB_REQ_GET_DESCRIPTOR
|
||||
//--------------------------------------------------------------
|
||||
li $23, 0 // NoData = 0
|
||||
|
||||
srl $9, $25, 24 // wValue >> 8
|
||||
sub $8, $9, 0x01 // check USB_DT_DEVICE
|
||||
beqz $8, ___ep0_get_dev_desc
|
||||
srl $21, $26, 16 // get wLength
|
||||
sub $8, $9, 0x02 // check USB_DT_CONFIG
|
||||
beqz $8, ___ep0_get_conf_desc
|
||||
sub $8, $9, 0x03 // check USB_DT_STRING
|
||||
beqz $8, ___ep0_get_string_desc
|
||||
sub $8, $9, 0x06 // check USB_DT_DEVICE_QUALIFIER
|
||||
beqz $8, ___ep0_get_dev_qualifier
|
||||
nop
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
___ep0_get_dev_desc:
|
||||
load_addr $20, device_desc // data pointer
|
||||
li $22, 1 // set EP0 to TX state
|
||||
sub $8, $21, 18
|
||||
blez $8, _ep0_idle_state_fini // wLength <= 18
|
||||
nop
|
||||
li $21, 18 // max length of device_desc
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
___ep0_get_dev_qualifier:
|
||||
load_addr $20, dev_qualifier // data pointer
|
||||
li $22, 1 // set EP0 to TX state
|
||||
sub $8, $21, 10
|
||||
blez $8, _ep0_idle_state_fini // wLength <= 10
|
||||
nop
|
||||
li $21, 10 // max length of dev_qualifier
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
___ep0_get_conf_desc:
|
||||
load_addr $20, config_desc_fs // data pointer of FS mode
|
||||
lbu $8, 0x01($27) // read POWER
|
||||
andi $8, 0x10 // test HS_MODE
|
||||
beqz $8, ___ep0_get_conf_desc2
|
||||
nop
|
||||
load_addr $20, config_desc_hs // data pointer of HS mode
|
||||
|
||||
___ep0_get_conf_desc2:
|
||||
li $22, 1 // set EP0 to TX state
|
||||
sub $8, $21, 32
|
||||
blez $8, _ep0_idle_state_fini // wLength <= 32
|
||||
nop
|
||||
li $21, 32 // max length of config_desc
|
||||
b _ep0_idle_state_fini
|
||||
nop
|
||||
|
||||
___ep0_get_string_desc:
|
||||
li $22, 1 // set EP0 to TX state
|
||||
|
||||
srl $9, $25, 16 // wValue & 0xff
|
||||
andi $9, 0xff
|
||||
|
||||
sub $8, $9, 1
|
||||
beqz $8, ___ep0_get_string_manufacture
|
||||
sub $8, $9, 2
|
||||
beqz $8, ___ep0_get_string_product
|
||||
nop
|
||||
|
||||
___ep0_get_string_lang_ids:
|
||||
load_addr $20, string_lang_ids // data pointer
|
||||
b _ep0_idle_state_fini
|
||||
li $21, 4 // data length
|
||||
|
||||
___ep0_get_string_manufacture:
|
||||
load_addr $20, string_manufacture // data pointer
|
||||
b _ep0_idle_state_fini
|
||||
li $21, 16 // data length
|
||||
|
||||
___ep0_get_string_product:
|
||||
load_addr $20, string_product // data pointer
|
||||
b _ep0_idle_state_fini
|
||||
li $21, 46 // data length
|
||||
|
||||
_ep0_idle_state_fini:
|
||||
li $9, 0x40 // SVDOUTPKTRDY
|
||||
beqz $23, _ep0_idle_state_fini2
|
||||
nop
|
||||
ori $9, $9, 0x08 // DATAEND
|
||||
_ep0_idle_state_fini2:
|
||||
sb $9, 0x12($27) // CSR0
|
||||
beqz $22, check_intr_ep1in
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 2.2 Handle EP0 TX state interrupt
|
||||
//--------------------------------------------------------------
|
||||
ep0_tx_state:
|
||||
sub $9, $22, 1
|
||||
bnez $9, check_intr_ep1in
|
||||
nop
|
||||
|
||||
sub $9, $21, 64 // max packetsize
|
||||
blez $9, _ep0_tx_state2 // data count <= 64
|
||||
ori $19, $21, 0
|
||||
li $19, 64
|
||||
|
||||
_ep0_tx_state2:
|
||||
beqz $19, _ep0_tx_state3 // send ZLP
|
||||
ori $18, $19, 0 // record bytes to be transferred
|
||||
sub $21, $21, $19 // decrement data count
|
||||
|
||||
_ep0_fifo_write_loop:
|
||||
lbu $9, 0($20) // read data
|
||||
sb $9, 0x20($27) // load FIFO
|
||||
sub $19, $19, 1 // decrement counter
|
||||
bnez $19, _ep0_fifo_write_loop
|
||||
addi $20, $20, 1 // increment data pointer
|
||||
|
||||
sub $9, $18, 64 // max packetsize
|
||||
beqz $9, _ep0_tx_state4
|
||||
nop
|
||||
|
||||
_ep0_tx_state3:
|
||||
// transferred bytes < max packetsize
|
||||
li $9, 0x0a // set INPKTRDY and DATAEND
|
||||
sb $9, 0x12($27) // CSR0
|
||||
li $22, 0 // set EP0 to IDLE state
|
||||
b check_intr_ep1in
|
||||
nop
|
||||
|
||||
_ep0_tx_state4:
|
||||
// transferred bytes == max packetsize
|
||||
li $9, 0x02 // set INPKTRDY
|
||||
sb $9, 0x12($27) // CSR0
|
||||
b check_intr_ep1in
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 3. Check and handle EP1 BULK-IN interrupt
|
||||
//--------------------------------------------------------------
|
||||
check_intr_ep1in:
|
||||
andi $9, $10, 0x2 // check EP1 IN interrupt
|
||||
beqz $9, check_intr_ep1out
|
||||
nop
|
||||
|
||||
handle_epin1_intr:
|
||||
li $9, 1
|
||||
sb $9, 0x0e($27) // set INDEX 1
|
||||
lbu $9, 0x12($27) // read INCSR
|
||||
|
||||
andi $8, $9, 0x2 // check INCSR_FFNOTEMPT
|
||||
bnez $8, _epin1_tx_state4
|
||||
nop
|
||||
|
||||
_epin1_write_fifo:
|
||||
lhu $9, 0x10($27) // get INMAXP
|
||||
sub $8, $21, $9
|
||||
blez $8, _epin1_tx_state1 // bytes left <= INMAXP
|
||||
ori $19, $21, 0
|
||||
ori $19, $9, 0
|
||||
|
||||
_epin1_tx_state1:
|
||||
beqz $19, _epin1_tx_state4 // No data
|
||||
nop
|
||||
|
||||
sub $21, $21, $19 // decrement data count
|
||||
|
||||
srl $5, $19, 2 // # of word
|
||||
andi $6, $19, 0x3 // # of byte
|
||||
beqz $5, _epin1_tx_state2
|
||||
nop
|
||||
|
||||
_epin1_fifo_write_word:
|
||||
lw $9, 0($20) // read data from source address
|
||||
sw $9, 0x24($27) // write FIFO
|
||||
sub $5, $5, 1 // decrement counter
|
||||
bnez $5, _epin1_fifo_write_word
|
||||
addiu $20, $20, 4 // increment dest address
|
||||
|
||||
_epin1_tx_state2:
|
||||
beqz $6, _epin1_tx_state3
|
||||
nop
|
||||
|
||||
_epin1_fifo_write_byte:
|
||||
lbu $9, 0($20) // read data from source address
|
||||
sb $9, 0x24($27) // write FIFO
|
||||
sub $6, $6, 1 // decrement counter
|
||||
bnez $6, _epin1_fifo_write_byte
|
||||
addiu $20, $20, 1 // increment dest address
|
||||
|
||||
_epin1_tx_state3:
|
||||
li $9, 0x1
|
||||
sb $9, 0x12($27) // INCSR, set INPKTRDY
|
||||
|
||||
_epin1_tx_state4:
|
||||
// nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// 4. Check and handle EP1 BULK-OUT interrupt
|
||||
//--------------------------------------------------------------
|
||||
check_intr_ep1out:
|
||||
lhu $9, 0x04($27) // read INTROUT
|
||||
andi $9, 0x2
|
||||
beqz $9, check_status_next
|
||||
nop
|
||||
|
||||
handle_epout1_intr:
|
||||
li $9, 1
|
||||
sb $9, 0x0e($27) // set INDEX 1
|
||||
|
||||
lbu $9, 0x16($27) // read OUTCSR
|
||||
andi $9, 0x1 // check OUTPKTRDY
|
||||
beqz $9, check_status_next
|
||||
nop
|
||||
|
||||
_epout1_read_fifo:
|
||||
lhu $19, 0x18($27) // read OUTCOUNT
|
||||
srl $5, $19, 2 // # of word
|
||||
andi $6, $19, 0x3 // # of byte
|
||||
beqz $5, _epout1_rx_state1
|
||||
nop
|
||||
|
||||
_epout1_fifo_read_word:
|
||||
lw $9, 0x24($27) // read FIFO
|
||||
sw $9, 0($20) // store to dest address
|
||||
sub $5, $5, 1 // decrement counter
|
||||
bnez $5, _epout1_fifo_read_word
|
||||
addiu $20, $20, 4 // increment dest address
|
||||
|
||||
_epout1_rx_state1:
|
||||
beqz $6, _epout1_rx_state2
|
||||
nop
|
||||
|
||||
_epout1_fifo_read_byte:
|
||||
lbu $9, 0x24($27) // read FIFO
|
||||
sb $9, 0($20) // store to dest address
|
||||
sub $6, $6, 1 // decrement counter
|
||||
bnez $6, _epout1_fifo_read_byte
|
||||
addiu $20, $20, 1 // increment dest address
|
||||
|
||||
_epout1_rx_state2:
|
||||
sb $0, 0x16($27) // clear OUTPKTRDY
|
||||
|
||||
check_status_next:
|
||||
b usb_command_loop
|
||||
nop
|
||||
|
||||
//--------------------------------------------------------------
|
||||
// Device/Configuration/Interface/Endpoint/String Descriptors
|
||||
//--------------------------------------------------------------
|
||||
|
||||
.align 2
|
||||
device_desc:
|
||||
.byte 0x12 // bLength
|
||||
.byte 0x01 // bDescriptorType
|
||||
.byte 0x00 // bcdUSB
|
||||
.byte 0x02 // bcdUSB
|
||||
.byte 0x00 // bDeviceClass
|
||||
.byte 0x00 // bDeviceSubClass
|
||||
.byte 0x00 // bDeviceProtocol
|
||||
.byte 0x40 // bMaxPacketSize0
|
||||
.byte 0x1a // idVendor
|
||||
.byte 0x60 // idVendor
|
||||
.byte 0x40 // idProduct
|
||||
.byte 0x47 // idProduct
|
||||
.byte 0x00 // bcdDevice
|
||||
.byte 0x01 // bcdDevice
|
||||
.byte 0x01 // iManufacturer
|
||||
.byte 0x02 // iProduct
|
||||
.byte 0x00 // iSerialNumber
|
||||
.byte 0x01 // bNumConfigurations
|
||||
|
||||
.align 2
|
||||
dev_qualifier:
|
||||
.byte 0x0a // bLength
|
||||
.byte 0x06 // bDescriptorType
|
||||
.byte 0x00 // bcdUSB
|
||||
.byte 0x02 // bcdUSB
|
||||
.byte 0x00 // bDeviceClass
|
||||
.byte 0x00 // bDeviceSubClass
|
||||
.byte 0x00 // bDeviceProtocol
|
||||
.byte 0x40 // bMaxPacketSize0
|
||||
.byte 0x01 // bNumConfigurations
|
||||
.byte 0x00 // bRESERVED
|
||||
|
||||
.align 2
|
||||
config_desc_hs:
|
||||
.byte 0x09 // bLength
|
||||
.byte 0x02 // bDescriptorType
|
||||
.byte 0x20 // wTotalLength
|
||||
.byte 0x00 // wTotalLength
|
||||
.byte 0x01 // bNumInterfaces
|
||||
.byte 0x01 // bConfigurationValue
|
||||
.byte 0x00 // iConfiguration
|
||||
.byte 0xc0 // bmAttributes
|
||||
.byte 0x01 // MaxPower
|
||||
intf_desc_hs:
|
||||
.byte 0x09 // bLength
|
||||
.byte 0x04 // bDescriptorType
|
||||
.byte 0x00 // bInterfaceNumber
|
||||
.byte 0x00 // bAlternateSetting
|
||||
.byte 0x02 // bNumEndpoints
|
||||
.byte 0xff // bInterfaceClass
|
||||
.byte 0x00 // bInterfaceSubClass
|
||||
.byte 0x50 // bInterfaceProtocol
|
||||
.byte 0x00 // iInterface
|
||||
ep1_desc_hs:
|
||||
.byte 0x07 // bLength
|
||||
.byte 0x05 // bDescriptorType
|
||||
.byte 0x01 // bEndpointAddress
|
||||
.byte 0x02 // bmAttributes
|
||||
.byte 0x00 // wMaxPacketSize
|
||||
.byte 0x02 // wMaxPacketSize
|
||||
.byte 0x00 // bInterval
|
||||
ep2_desc_hs:
|
||||
.byte 0x07 // bLength
|
||||
.byte 0x05 // bDescriptorType
|
||||
.byte 0x81 // bEndpointAddress
|
||||
.byte 0x02 // bmAttributes
|
||||
.byte 0x00 // wMaxPacketSize
|
||||
.byte 0x02 // wMaxPacketSize
|
||||
.byte 0x00 // bInterval
|
||||
|
||||
.align 2
|
||||
config_desc_fs:
|
||||
.byte 0x09 // bLength
|
||||
.byte 0x02 // bDescriptorType
|
||||
.byte 0x20 // wTotalLength
|
||||
.byte 0x00 // wTotalLength
|
||||
.byte 0x01 // bNumInterfaces
|
||||
.byte 0x01 // bConfigurationValue
|
||||
.byte 0x00 // iConfiguration
|
||||
.byte 0xc0 // bmAttributes
|
||||
.byte 0x01 // MaxPower
|
||||
intf_desc_fs:
|
||||
.byte 0x09 // bLength
|
||||
.byte 0x04 // bDescriptorType
|
||||
.byte 0x00 // bInterfaceNumber
|
||||
.byte 0x00 // bAlternateSetting
|
||||
.byte 0x02 // bNumEndpoints
|
||||
.byte 0xff // bInterfaceClass
|
||||
.byte 0x00 // bInterfaceSubClass
|
||||
.byte 0x50 // bInterfaceProtocol
|
||||
.byte 0x00 // iInterface
|
||||
ep1_desc_fs:
|
||||
.byte 0x07 // bLength
|
||||
.byte 0x05 // bDescriptorType
|
||||
.byte 0x01 // bEndpointAddress
|
||||
.byte 0x02 // bmAttributes
|
||||
.byte 0x40 // wMaxPacketSize
|
||||
.byte 0x00 // wMaxPacketSize
|
||||
.byte 0x00 // bInterval
|
||||
ep2_desc_fs:
|
||||
.byte 0x07 // bLength
|
||||
.byte 0x05 // bDescriptorType
|
||||
.byte 0x81 // bEndpointAddress
|
||||
.byte 0x02 // bmAttributes
|
||||
.byte 0x40 // wMaxPacketSize
|
||||
.byte 0x00 // wMaxPacketSize
|
||||
.byte 0x00 // bInterval
|
||||
|
||||
.align 2
|
||||
string_lang_ids:
|
||||
.byte 0x04
|
||||
.byte 0x03
|
||||
.byte 0x09
|
||||
.byte 0x04
|
||||
|
||||
.align 2
|
||||
string_manufacture:
|
||||
.byte 0x10
|
||||
.byte 0x03
|
||||
.byte 0x49
|
||||
.byte 0x00
|
||||
.byte 0x6e
|
||||
.byte 0x00
|
||||
.byte 0x67
|
||||
.byte 0x00
|
||||
.byte 0x65
|
||||
.byte 0x00
|
||||
.byte 0x6e
|
||||
.byte 0x00
|
||||
.byte 0x69
|
||||
.byte 0x00
|
||||
.byte 0x63
|
||||
.byte 0x00
|
||||
|
||||
.align 2
|
||||
string_product:
|
||||
.byte 0x2e
|
||||
.byte 0x03
|
||||
.byte 0x4a
|
||||
.byte 0x00
|
||||
.byte 0x5a
|
||||
.byte 0x00
|
||||
.byte 0x34
|
||||
.byte 0x00
|
||||
.byte 0x37
|
||||
.byte 0x00
|
||||
.byte 0x34
|
||||
.byte 0x00
|
||||
.byte 0x30
|
||||
.byte 0x00
|
||||
.byte 0x20
|
||||
.byte 0x00
|
||||
.byte 0x55
|
||||
.byte 0x00
|
||||
.byte 0x53
|
||||
.byte 0x00
|
||||
.byte 0x42
|
||||
.byte 0x00
|
||||
.byte 0x20
|
||||
.byte 0x00
|
||||
.byte 0x42
|
||||
.byte 0x00
|
||||
.byte 0x6f
|
||||
.byte 0x00
|
||||
.byte 0x6f
|
||||
.byte 0x00
|
||||
.byte 0x74
|
||||
.byte 0x00
|
||||
.byte 0x20
|
||||
.byte 0x00
|
||||
.byte 0x44
|
||||
.byte 0x00
|
||||
.byte 0x65
|
||||
.byte 0x00
|
||||
.byte 0x76
|
||||
.byte 0x00
|
||||
.byte 0x69
|
||||
.byte 0x00
|
||||
.byte 0x63
|
||||
.byte 0x00
|
||||
.byte 0x65
|
||||
.byte 0x00
|
||||
|
||||
.align 2
|
||||
cpu_info_data:
|
||||
.byte 0x4a
|
||||
.byte 0x5a
|
||||
.byte 0x34
|
||||
.byte 0x37
|
||||
.byte 0x34
|
||||
.byte 0x30
|
||||
.byte 0x56
|
||||
.byte 0x31
|
||||
usbboot_end:
|
||||
|
||||
.set reorder
|
4882
package/uboot-xburst/files/include/asm-mips/jz4740.h
Normal file
4882
package/uboot-xburst/files/include/asm-mips/jz4740.h
Normal file
File diff suppressed because it is too large
Load Diff
26
package/uboot-xburst/files/include/configs/avt2.h
Normal file
26
package/uboot-xburst/files/include/configs/avt2.h
Normal file
@ -0,0 +1,26 @@
|
||||
#ifndef __CONFIG_AVT2_H
|
||||
#define __CONFIG_AVT2_H
|
||||
|
||||
#include <configs/nanonote.h>
|
||||
|
||||
#define CONFIG_AVT2 1
|
||||
|
||||
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait avt2=1"
|
||||
#define CONFIG_BOOTARGSFROMSD "mem=64M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait avt2=1"
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
|
||||
|
||||
/* SDRAM paramters */
|
||||
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
|
||||
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
|
||||
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
|
||||
#define SDRAM_COL 10 /* Column address: 8 to 12 */
|
||||
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
|
||||
|
||||
/* SDRAM Timings, unit: ns */
|
||||
#define SDRAM_TRAS 45 /* RAS# Active Time */
|
||||
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
|
||||
#define SDRAM_TPC 20 /* RAS# Precharge Time */
|
||||
#define SDRAM_TRWL 7 /* Write Latency Time */
|
||||
#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
|
||||
|
||||
#endif /* __CONFIG_AVT_H */
|
311
package/uboot-xburst/files/include/configs/n516.h
Normal file
311
package/uboot-xburst/files/include/configs/n516.h
Normal file
@ -0,0 +1,311 @@
|
||||
/*
|
||||
* (C) Copyright 2006
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the pavo board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
//#define DEBUG
|
||||
//#define DEBUG_SHELL
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
|
||||
#define CONFIG_JzRISC 1 /* JzRISC core */
|
||||
#define CONFIG_JZSOC 1 /* Jz SoC */
|
||||
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
|
||||
#define CONFIG_PAVO 1 /* PAVO validation board */
|
||||
|
||||
#define CONFIG_BOARD_NAME "n516"
|
||||
#define CONFIG_BOARD_HWREV "1.0"
|
||||
#define CONFIG_FIRMWARE_EPOCH "0"
|
||||
#define CONFIG_UPDATE_TMPBUF 0x80600000
|
||||
#define CONFIG_UPDATE_CHUNKSIZE 0x800000
|
||||
#define CONFIG_UPDATE_FILENAME "update.oifw"
|
||||
#define CONFIG_UPDATE_FILEEXT ".oifw"
|
||||
#define CONFIG_UBI_PARTITION "UBI"
|
||||
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT 1
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
#if 0
|
||||
#define CONFIG_LCD /* LCD support */
|
||||
#define CONFIG_JZLCD_METRONOME_800x600
|
||||
#define LCD_BPP LCD_COLOR8
|
||||
|
||||
#define WFM_DATA_SIZE ( 1 << 14 )
|
||||
#define CONFIG_METRONOME_WF_LEN (64 * (1 << 10))
|
||||
#define CONFIG_METRONOME_WF_NAND_OFFSET (0x100000)
|
||||
#define BMP_LOGO_HEIGHT 0
|
||||
#define CONFIG_UBI_WF_VOLUME "waveforms"
|
||||
#define CONFIG_UBI_BOOTSPLASH_VOLUME "bootsplash"
|
||||
#define CONFIG_METRONOME_BOOTSPLASH_LEN 480000
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#define CONFIG_JZSOC_I2C
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
#define CONFIG_LPC_I2C_ADDR 0x54
|
||||
#endif
|
||||
|
||||
#define JZ4740_NORBOOT_CFG JZ4740_NORBOOT_16BIT /* NOR Boot config code */
|
||||
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3 /* NAND Boot config code */
|
||||
|
||||
#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
|
||||
#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
|
||||
#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL/256) /* incrementer freq */
|
||||
|
||||
#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
|
||||
|
||||
#define CONFIG_BAUDRATE 57600
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_GENERIC_MMC 1
|
||||
#define CONFIG_JZ_MMC 1
|
||||
#define CONFIG_FAT 1
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 ">"
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_BDI /* bdinfo */
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_ECHO /* echo arguments */
|
||||
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
|
||||
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
|
||||
#undef CONFIG_CMD_IMI /* iminfo */
|
||||
#undef CONFIG_CMD_ITEST /* Integer (and string) test */
|
||||
#undef CONFIG_CMD_LOADB /* loadb */
|
||||
#undef CONFIG_CMD_LOADS /* loads */
|
||||
#undef CONFIG_CMD_NFS /* NFS support */
|
||||
#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
||||
#undef CONFIG_CMD_SOURCE /* "source" command support */
|
||||
#undef CONFIG_CMD_XIMG /* Load part of Multi Image */
|
||||
#undef CONFIG_CMD_NET
|
||||
|
||||
//#define CONFIG_CMD_ASKENV
|
||||
//#define CONFIG_CMD_DHCP
|
||||
//#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
/*#define CONFIG_CMD_UBI*/
|
||||
/*#define CONFIG_CMD_MTDPARTS*/
|
||||
//#define CONFIG_CMD_JFFS2
|
||||
//#define CONFIG_JFFS2_NAND
|
||||
//#define CONFIG_JFFS2_CMDLINE
|
||||
#define CONFIG_CMD_UPDATE
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*#define CONFIG_MTD_PARTITIONS*/
|
||||
#define CONFIG_RBTREE
|
||||
|
||||
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAUL )
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#if 0
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
#define CONFIG_BOOTDELAY 0
|
||||
#define CONFIG_BOOTFILE uImage /* file to load */
|
||||
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ip=off rootfstype=ubifs root=ubi:rootfs ubi.mtd=UBI rw panic=5 " MTDPARTS_DEFAULT
|
||||
#define CONFIG_BOOTCOMMAND "check_and_update; setenv bootargs $bootargs $batt_level_param; ubi read 0x80600000 bootsplash && show_image 0x80600000; ubi read 0x80600000 kernel; bootm 0x80600000; ubi read 0x80600000 errorsplash && show_image 0x80600000; while test 0 = 0; do check_and_update; done"
|
||||
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
|
||||
#define CONFIG_IPADDR 192.168.111.1
|
||||
#define CONFIG_SERVERIP 192.168.111.2
|
||||
#define MTDIDS_DEFAULT "nand0=jz4740-nand"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "mtdids=nand0=jz4740-nand\0mtdparts=mtdparts=jz4740-nand:1M@0(uboot)ro,-@1M(UBI)\0" \
|
||||
"stdout=serial\0stderr=lcd\0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
|
||||
#define CONFIG_BOOTDELAY 0
|
||||
#define CONFIG_BOOTFILE "uImage" /* file to load */
|
||||
#define CONFIG_BOOTARGS "mem=64M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
|
||||
|
||||
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
|
||||
/*
|
||||
* Serial download configuration
|
||||
*
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "n516 # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN 1024*1024*2
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x80800000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND FLASH configuration
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE 0xB8000000
|
||||
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
|
||||
/*
|
||||
* IPL (Initial Program Loader, integrated inside CPU)
|
||||
* Will load first 8k from NAND (SPL) into cache and execute it from there.
|
||||
*
|
||||
* SPL (Secondary Program Loader)
|
||||
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
|
||||
* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
|
||||
* controller and the NAND controller so that the special U-Boot image can be
|
||||
* loaded from NAND to SDRAM.
|
||||
*
|
||||
* NUB (NAND U-Boot)
|
||||
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
|
||||
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
|
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
|
||||
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
|
||||
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 63 /* NAND bad block was marked at this page in a block, starting from 0 */
|
||||
#define CONFIG_SYS_NAND_ECC_POS 6
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_NAND
|
||||
//#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_SIZE (128 * 1024)
|
||||
//#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE) /* environment starts here */
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS)
|
||||
//#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NOR FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xa8000000 /* Flash Bank #1 */
|
||||
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
|
||||
#define CONFIG_SYS_SYS_MONITOR_BASE TEXT_BASE /* in pavo/config.mk TEXT_BASE=0x88000000*/
|
||||
#define CONFIG_SYS_MONITOR_LEN (256*1024) /* Reserve 256 kB for Monitor */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_IS_NOWHERE 1
|
||||
#define CONFIG_ENV_ADDR 0xa8040000
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SDRAM Info.
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
// SDRAM paramters
|
||||
#define SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
|
||||
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
|
||||
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
|
||||
#define SDRAM_COL 9 /* Column address: 8 to 12 */
|
||||
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
|
||||
|
||||
// SDRAM Timings, unit: ns
|
||||
#define SDRAM_TRAS 45 /* RAS# Active Time */
|
||||
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
|
||||
#define SDRAM_TPC 20 /* RAS# Precharge Time */
|
||||
#define SDRAM_TRWL 7 /* Write Latency Time */
|
||||
#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* GPIO definition
|
||||
*/
|
||||
#define GPIO_SD_VCC_EN_N 113 /* GPD17 */
|
||||
#define GPIO_SD_CD_N 103 /* GPD7 */
|
||||
#define GPIO_SD_WP 111 /* GPD15 */
|
||||
#define GPIO_USB_DETE 115 /* GPD6 */
|
||||
//#define GPIO_DC_DETE_N 103 /* GPD7 */
|
||||
#define GPIO_CHARG_STAT_N 112 /* GPD15 */
|
||||
#define GPIO_DISP_OFF_N 97 /* GPD1 */
|
||||
#define GPIO_UDC_HOTPLUG 100 /* GPD4 */
|
||||
#define GPIO_LED_EN 124 /* GPD28 */
|
||||
|
||||
#define GPIO_RST_L 50 /* GPB18 LCD_SPL */
|
||||
#define GPIO_LCDRDY 49 /* GPB17 LCD_CLS */
|
||||
#define GPIO_STBY 86 /* GPC22 LCD_PS */
|
||||
#define GPIO_ERR 87 /* GPC23 LCD_REV */
|
||||
|
||||
#endif /* __CONFIG_H */
|
191
package/uboot-xburst/files/include/configs/nanonote.h
Normal file
191
package/uboot-xburst/files/include/configs/nanonote.h
Normal file
@ -0,0 +1,191 @@
|
||||
/*
|
||||
* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 3 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for the NanoNote.
|
||||
*/
|
||||
#ifndef __CONFIG_NANONOTE_H
|
||||
#define __CONFIG_NANONOTE_H
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
|
||||
#define CONFIG_JzRISC 1 /* JzRISC core */
|
||||
#define CONFIG_JZSOC 1 /* Jz SoC */
|
||||
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
|
||||
#define CONFIG_NANONOTE 1
|
||||
|
||||
#define CONFIG_LCD 1 /* LCD support */
|
||||
#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK 1
|
||||
|
||||
#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
|
||||
#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
|
||||
#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
|
||||
|
||||
#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
|
||||
#define CONFIG_BAUDRATE 57600
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_FAT 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT 1
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
|
||||
#define CONFIG_BOOTDELAY 0
|
||||
#define CONFIG_BOOTFILE "uImage" /* file to load */
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_BOOTD /* bootd */
|
||||
#define CONFIG_CMD_CONSOLE /* coninfo */
|
||||
#define CONFIG_CMD_ECHO /* echo arguments */
|
||||
|
||||
#define CONFIG_CMD_LOADB /* loadb */
|
||||
#define CONFIG_CMD_LOADS /* loads */
|
||||
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
|
||||
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
|
||||
#define CONFIG_CMD_RUN /* run command in env variable */
|
||||
#define CONFIG_CMD_SAVEENV /* saveenv */
|
||||
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
||||
#define CONFIG_CMD_SOURCE /* "source" command support */
|
||||
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
/*
|
||||
* Serial download configuration
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "QI# " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN 896 * 1024
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x80800000
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
|
||||
|
||||
/*
|
||||
* NAND FLASH configuration
|
||||
*/
|
||||
/* NAND Boot config code */
|
||||
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
|
||||
|
||||
#define NANONOTE_NAND_SIZE 2 /* if board nand flash is 1GB, set to 1
|
||||
* if board nand flash is 2GB, set to 2
|
||||
* for change the PAGE_SIZE and BLOCK_SIZE
|
||||
* will delete when there is no 1GB flash
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * NANONOTE_NAND_SIZE)
|
||||
/* nand chip block size */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * NANONOTE_NAND_SIZE << 10)
|
||||
/* nand bad block was marked at this page in a block, start from 0 */
|
||||
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
|
||||
/* ECC offset position in oob area, default value is 6 if it isn't defined */
|
||||
#define CONFIG_SYS_NAND_ECC_POS (6 * NANONOTE_NAND_SIZE)
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE 0xB8000000
|
||||
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
|
||||
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
|
||||
|
||||
/*
|
||||
* IPL (Initial Program Loader, integrated inside CPU)
|
||||
* Will load first 8k from NAND (SPL) into cache and execute it from there.
|
||||
*
|
||||
* SPL (Secondary Program Loader)
|
||||
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
|
||||
* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
|
||||
* controller and the NAND controller so that the special U-Boot image can be
|
||||
* loaded from NAND to SDRAM.
|
||||
*
|
||||
* NUB (NAND U-Boot)
|
||||
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
|
||||
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
|
||||
/* Start NUB from this addr*/
|
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
|
||||
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
/* environment starts here */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
|
||||
/* in board/nanonote/config.mk TEXT_BAS = 0x88000000 */
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
|
||||
/*
|
||||
* SDRAM Info.
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/*
|
||||
* GPIO definition
|
||||
*/
|
||||
#define GPIO_LCD_CS (2 * 32 + 21)
|
||||
#define GPIO_DISP_OFF_N (3 * 32 + 21)
|
||||
#define GPIO_PWM (3 * 32 + 27)
|
||||
|
||||
#define GPIO_AMP_EN (3 * 32 + 4)
|
||||
|
||||
#define GPIO_SDPW_EN (3 * 32 + 2)
|
||||
#define GPIO_SD_DETECT (3 * 32 + 0)
|
||||
|
||||
#define GPIO_USB_DETECT (3 * 32 + 27)
|
||||
#define GPIO_BUZZ_PWM (3 * 32 + 28)
|
||||
|
||||
#define GPIO_AUDIO_POP (1 * 32 + 29)
|
||||
#define GPIO_COB_TEST (1 * 32 + 30)
|
||||
|
||||
#define GPIO_KEYOUT_BASE (2 * 32 + 10)
|
||||
#define GPIO_KEYIN_BASE (3 * 32 + 18)
|
||||
#define GPIO_KEYIN_8 (3 * 32 + 26)
|
||||
|
||||
#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
|
||||
#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
|
||||
|
||||
#endif /* __CONFIG_NANONOTE_H */
|
27
package/uboot-xburst/files/include/configs/qi_lb60.h
Normal file
27
package/uboot-xburst/files/include/configs/qi_lb60.h
Normal file
@ -0,0 +1,27 @@
|
||||
#ifndef __CONFIG_QI_LB60_H
|
||||
#define __CONFIG_QI_LB60_H
|
||||
|
||||
#include <configs/nanonote.h>
|
||||
|
||||
#define CONFIG_QI_LB60 1
|
||||
|
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
|
||||
#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p2 rw rootwait"
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
|
||||
#define CONFIG_BOOTCOMMANDFROMSD "mmc init; fatload mmc 0 0x80600000 uImage; bootm"
|
||||
|
||||
/* SDRAM paramters */
|
||||
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
|
||||
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
|
||||
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
|
||||
#define SDRAM_COL 9 /* Column address: 8 to 12 */
|
||||
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
|
||||
|
||||
/* SDRAM Timings, unit: ns */
|
||||
#define SDRAM_TRAS 45 /* RAS# Active Time */
|
||||
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
|
||||
#define SDRAM_TPC 20 /* RAS# Precharge Time */
|
||||
#define SDRAM_TRWL 7 /* Write Latency Time */
|
||||
#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
|
||||
|
||||
#endif
|
200
package/uboot-xburst/files/include/configs/sakc.h
Normal file
200
package/uboot-xburst/files/include/configs/sakc.h
Normal file
@ -0,0 +1,200 @@
|
||||
/*
|
||||
* Authors: Xiangfu Liu <xiangfu.z@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 3 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file contains the configuration parameters for SAKC.
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define DEBUG
|
||||
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
|
||||
#define CONFIG_JzRISC 1 /* JzRISC core */
|
||||
#define CONFIG_JZSOC 1 /* Jz SoC */
|
||||
#define CONFIG_JZ4725 1 /* Jz4725 SoC */
|
||||
#define CONFIG_JZ4740 1 /* Jz4740 SoC */
|
||||
#define CONFIG_SAKC 1 /* SAKC board */
|
||||
|
||||
#define MMC_BUS_WIDTH_1BIT 1 /* 1 for MMC 1Bit Bus Width */
|
||||
|
||||
//#define CONFIG_LCD 1 /* LCD support */
|
||||
//#define LCD_BPP LCD_COLOR32 /*5:18,24,32 bits per pixel */
|
||||
//#define CONFIG_SYS_WHITE_ON_BLACK 1
|
||||
|
||||
#define CONFIG_SYS_CPU_SPEED 336000000 /* CPU clock: 336 MHz */
|
||||
#define CONFIG_SYS_EXTAL 12000000 /* EXTAL freq: 12 MHz */
|
||||
#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 256) /* incrementer freq */
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
|
||||
|
||||
#define CONFIG_SYS_UART_BASE UART0_BASE /* Base of the UART channel */
|
||||
#define CONFIG_BAUDRATE 57600
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CONFIG_MMC 1
|
||||
#define CONFIG_FAT 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT 1
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1
|
||||
#define CONFIG_SYS_NO_FLASH 1
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTFILE "uImage" /* file to load */
|
||||
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS 1
|
||||
#define CONFIG_BOOTARGSFROMSD "mem=32M console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait"
|
||||
#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm"
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_BDI /* bdinfo */
|
||||
#define CONFIG_CMD_BOOTD /* bootd */
|
||||
#define CONFIG_CMD_CONSOLE /* coninfo */
|
||||
#define CONFIG_CMD_ECHO /* echo arguments */
|
||||
#define CONFIG_CMD_IMI /* iminfo */
|
||||
#define CONFIG_CMD_ITEST /* Integer (and string) test */
|
||||
|
||||
#define CONFIG_CMD_LOADB /* loadb */
|
||||
#define CONFIG_CMD_LOADS /* loads */
|
||||
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
|
||||
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
|
||||
#define CONFIG_CMD_RUN /* run command in env variable */
|
||||
#define CONFIG_CMD_SAVEENV /* saveenv */
|
||||
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
|
||||
#define CONFIG_CMD_SOURCE /* "source" command support */
|
||||
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
|
||||
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
/*
|
||||
* Serial download configuration
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "SAKC# " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN 128 * 1024
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 128 * 1024
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80600000 /* default load address */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80100000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x80800000
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
|
||||
|
||||
/*
|
||||
* NAND FLASH configuration
|
||||
*/
|
||||
/* NAND Boot config code */
|
||||
#define JZ4740_NANDBOOT_CFG JZ4740_NANDBOOT_B8R3
|
||||
|
||||
#define SAKC_NAND_SIZE 1 /* if board nand flash is 1GB, set to 1
|
||||
* if board nand flash is 2GB, set to 2
|
||||
* for change the PAGE_SIZE and BLOCK_SIZE
|
||||
* will delete when there is no 1GB flash
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_NAND_PAGE_SIZE (2048 * SAKC_NAND_SIZE)
|
||||
/* nand chip block size */
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * SAKC_NAND_SIZE << 10)
|
||||
/* nand bad block was marked at this page in a block, start from 0 */
|
||||
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 127
|
||||
/* ECC offset position in oob area, default value is 6 if it isn't defined */
|
||||
#define CONFIG_SYS_NAND_ECC_POS (6 * SAKC_NAND_SIZE)
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE 0xB8000000
|
||||
#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl.*/
|
||||
#define CONFIG_SYS_ONENAND_BASE CONFIG_SYS_NAND_BASE
|
||||
|
||||
/*
|
||||
* IPL (Initial Program Loader, integrated inside CPU)
|
||||
* Will load first 8k from NAND (SPL) into cache and execute it from there.
|
||||
*
|
||||
* SPL (Secondary Program Loader)
|
||||
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
|
||||
* has to fit into 8kByte. It sets up the CPU and configures the SDRAM
|
||||
* controller and the NAND controller so that the special U-Boot image can be
|
||||
* loaded from NAND to SDRAM.
|
||||
*
|
||||
* NUB (NAND U-Boot)
|
||||
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
|
||||
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST 0x80100000 /* Load NUB to this addr */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
|
||||
/* Start NUB from this addr*/
|
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
|
||||
*/
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
|
||||
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
/* environment starts here */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
|
||||
/* in qi_lb60.h/config.mk TEXT_BAS = 0x88000000 */
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
|
||||
/*
|
||||
* SDRAM Info.
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
/* SDRAM paramters */
|
||||
#define SDRAM_BW16 1 /* Data bus width: 0-32bit, 1-16bit */
|
||||
#define SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
|
||||
#define SDRAM_ROW 13 /* Row address: 11 to 13 */
|
||||
#define SDRAM_COL 9 /* Column address: 8 to 12 */
|
||||
#define SDRAM_CASL 2 /* CAS latency: 2 or 3 */
|
||||
|
||||
/* SDRAM Timings, unit: ns */
|
||||
#define SDRAM_TRAS 45 /* RAS# Active Time */
|
||||
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
|
||||
#define SDRAM_TPC 20 /* RAS# Precharge Time */
|
||||
#define SDRAM_TRWL 7 /* Write Latency Time */
|
||||
#define SDRAM_TREF 15625 /* Refresh period: 8192 cycles/64ms */
|
||||
|
||||
/*
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
/*
|
||||
* GPIO definition
|
||||
*/
|
||||
#define GPIO_SD_DETECT (2 * 32 + 27)
|
||||
#define GPIO_SD_CD_N GPIO_SD_DETECT /* SD Card insert detect */
|
||||
#define GPIO_SD_VCC_EN_N GPIO_SDPW_EN /* SD Card Power Enable */
|
||||
|
||||
#endif /* __CONFIG_H */
|
104
package/uboot-xburst/files/nand_spl/board/n516/Makefile
Normal file
104
package/uboot-xburst/files/nand_spl/board/n516/Makefile
Normal file
@ -0,0 +1,104 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o usb_boot.o
|
||||
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
|
||||
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
|
||||
cat $< $(nandobj)junk1 > $(nandobj)junk2
|
||||
dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
|
||||
cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
|
||||
dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
|
||||
cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
|
||||
dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
|
||||
rm -f $(nandobj)junk*
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)start.S:
|
||||
@rm -f $(obj)start.S
|
||||
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
|
||||
|
||||
$(obj)usb_boot.S:
|
||||
@rm -f $(obj)usb_boot.S
|
||||
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
|
||||
|
||||
$(obj)cpu.c:
|
||||
@rm -f $(obj)cpu.c
|
||||
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
|
||||
|
||||
$(obj)jz4740.c:
|
||||
@rm -f $(obj)jz4740.c
|
||||
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
|
||||
|
||||
$(obj)jz_serial.c:
|
||||
@rm -f $(obj)jz_serial.c
|
||||
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot_jz4740.c:
|
||||
@rm -f $(obj)nand_boot_jz4740.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
34
package/uboot-xburst/files/nand_spl/board/n516/config.mk
Normal file
34
package/uboot-xburst/files/nand_spl/board/n516/config.mk
Normal file
@ -0,0 +1,34 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# Ingenic JZ4740 Reference Platform
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
|
||||
# in the first 4kBytes of memory space in cache. So we set
|
||||
# TEXT_BASE to starting address in internal cache here.
|
||||
#
|
||||
TEXT_BASE = 0x80000000
|
63
package/uboot-xburst/files/nand_spl/board/n516/u-boot.lds
Normal file
63
package/uboot-xburst/files/nand_spl/board/n516/u-boot.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
104
package/uboot-xburst/files/nand_spl/board/nanonote/Makefile
Normal file
104
package/uboot-xburst/files/nand_spl/board/nanonote/Makefile
Normal file
@ -0,0 +1,104 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o usb_boot.o
|
||||
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
|
||||
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
|
||||
cat $< $(nandobj)junk1 > $(nandobj)junk2
|
||||
dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
|
||||
cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
|
||||
dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
|
||||
cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
|
||||
dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
|
||||
rm -f $(nandobj)junk*
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)start.S:
|
||||
@rm -f $(obj)start.S
|
||||
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
|
||||
|
||||
$(obj)usb_boot.S:
|
||||
@rm -f $(obj)usb_boot.S
|
||||
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
|
||||
|
||||
$(obj)cpu.c:
|
||||
@rm -f $(obj)cpu.c
|
||||
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
|
||||
|
||||
$(obj)jz4740.c:
|
||||
@rm -f $(obj)jz4740.c
|
||||
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
|
||||
|
||||
$(obj)jz_serial.c:
|
||||
@rm -f $(obj)jz_serial.c
|
||||
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot_jz4740.c:
|
||||
@rm -f $(obj)nand_boot_jz4740.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
34
package/uboot-xburst/files/nand_spl/board/nanonote/config.mk
Normal file
34
package/uboot-xburst/files/nand_spl/board/nanonote/config.mk
Normal file
@ -0,0 +1,34 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# Ingenic JZ4740 Reference Platform
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
|
||||
# in the first 4kBytes of memory space in cache. So we set
|
||||
# TEXT_BASE to starting address in internal cache here.
|
||||
#
|
||||
TEXT_BASE = 0x80000000
|
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
104
package/uboot-xburst/files/nand_spl/board/sakc/Makefile
Normal file
104
package/uboot-xburst/files/nand_spl/board/sakc/Makefile
Normal file
@ -0,0 +1,104 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o usb_boot.o
|
||||
COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
|
||||
dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
|
||||
cat $< $(nandobj)junk1 > $(nandobj)junk2
|
||||
dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
|
||||
cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
|
||||
dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
|
||||
cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
|
||||
dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
|
||||
rm -f $(nandobj)junk*
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)start.S:
|
||||
@rm -f $(obj)start.S
|
||||
ln -s $(SRCTREE)/cpu/mips/start.S $(obj)start.S
|
||||
|
||||
$(obj)usb_boot.S:
|
||||
@rm -f $(obj)usb_boot.S
|
||||
ln -s $(SRCTREE)/cpu/mips/usb_boot.S $(obj)usb_boot.S
|
||||
|
||||
$(obj)cpu.c:
|
||||
@rm -f $(obj)cpu.c
|
||||
ln -s $(SRCTREE)/cpu/mips/cpu.c $(obj)cpu.c
|
||||
|
||||
$(obj)jz4740.c:
|
||||
@rm -f $(obj)jz4740.c
|
||||
ln -s $(SRCTREE)/cpu/mips/jz4740.c $(obj)jz4740.c
|
||||
|
||||
$(obj)jz_serial.c:
|
||||
@rm -f $(obj)jz_serial.c
|
||||
ln -s $(SRCTREE)/cpu/mips/jz_serial.c $(obj)jz_serial.c
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot_jz4740.c:
|
||||
@rm -f $(obj)nand_boot_jz4740.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
34
package/uboot-xburst/files/nand_spl/board/sakc/config.mk
Normal file
34
package/uboot-xburst/files/nand_spl/board/sakc/config.mk
Normal file
@ -0,0 +1,34 @@
|
||||
#
|
||||
# (C) Copyright 2006
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# Ingenic JZ4740 Reference Platform
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On JZ4730 platforms the SPL is located at 0x80000000...0x80001000,
|
||||
# in the first 4kBytes of memory space in cache. So we set
|
||||
# TEXT_BASE to starting address in internal cache here.
|
||||
#
|
||||
TEXT_BASE = 0x80000000
|
63
package/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds
Normal file
63
package/uboot-xburst/files/nand_spl/board/sakc/u-boot.lds
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Ingenic Semiconductor, <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
_gp = ALIGN(16);
|
||||
|
||||
__got_start = .;
|
||||
.got : { *(.got) }
|
||||
__got_end = .;
|
||||
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) }
|
||||
uboot_end = .;
|
||||
}
|
429
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
Normal file
429
package/uboot-xburst/files/nand_spl/nand_boot_jz4740.c
Normal file
@ -0,0 +1,429 @@
|
||||
/*
|
||||
* Copyright (C) 2007 Ingenic Semiconductor Inc.
|
||||
* Author: Peter <jlwei@ingenic.cn>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <nand.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/jz4740.h>
|
||||
|
||||
#define KEY_U_OUT (32 * 2 + 16)
|
||||
#define KEY_U_IN (32 * 3 + 19)
|
||||
|
||||
/*
|
||||
* NAND flash definitions
|
||||
*/
|
||||
|
||||
#define NAND_DATAPORT 0xb8000000
|
||||
#define NAND_ADDRPORT 0xb8010000
|
||||
#define NAND_COMMPORT 0xb8008000
|
||||
|
||||
#define ECC_BLOCK 512
|
||||
#define ECC_POS 6
|
||||
#define PAR_SIZE 9
|
||||
|
||||
#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
|
||||
#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
|
||||
#define __nand_ecc_rs_encoding() \
|
||||
(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
|
||||
#define __nand_ecc_rs_decoding() \
|
||||
(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
|
||||
#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
|
||||
#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
|
||||
#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
|
||||
|
||||
static inline void __nand_dev_ready(void)
|
||||
{
|
||||
unsigned int timeout = 10000;
|
||||
while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
|
||||
while (!(REG_GPIO_PXPIN(2) & 0x40000000));
|
||||
}
|
||||
|
||||
#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
|
||||
#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
|
||||
#define __nand_data8() REG8(NAND_DATAPORT)
|
||||
#define __nand_data16() REG16(NAND_DATAPORT)
|
||||
|
||||
#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3)
|
||||
#define NAND_BUS_WIDTH 8
|
||||
#define NAND_ROW_CYCLE 3
|
||||
#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
|
||||
#define NAND_BUS_WIDTH 8
|
||||
#define NAND_ROW_CYCLE 2
|
||||
#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3)
|
||||
#define NAND_BUS_WIDTH 16
|
||||
#define NAND_ROW_CYCLE 3
|
||||
#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
|
||||
#define NAND_BUS_WIDTH 16
|
||||
#define NAND_ROW_CYCLE 2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* NAND flash parameters
|
||||
*/
|
||||
static int page_size = 2048;
|
||||
static int oob_size = 64;
|
||||
static int ecc_count = 4;
|
||||
static int page_per_block = 64;
|
||||
static int bad_block_pos = 0;
|
||||
static int block_size = 131072;
|
||||
|
||||
static unsigned char oob_buf[128] = {0};
|
||||
|
||||
/*
|
||||
* External routines
|
||||
*/
|
||||
extern void flush_cache_all(void);
|
||||
extern int serial_init(void);
|
||||
extern void serial_puts(const char *s);
|
||||
extern void sdram_init(void);
|
||||
extern void pll_init(void);
|
||||
extern void usb_boot();
|
||||
|
||||
/*
|
||||
* NAND flash routines
|
||||
*/
|
||||
#if NAND_BUS_WIDTH == 16
|
||||
static inline void nand_read_buf16(void *buf, int count)
|
||||
{
|
||||
int i;
|
||||
u16 *p = (u16 *)buf;
|
||||
|
||||
for (i = 0; i < count; i += 2)
|
||||
*p++ = __nand_data16();
|
||||
}
|
||||
#define nand_read_buf nand_read_buf16
|
||||
|
||||
#elif NAND_BUS_WIDTH == 8
|
||||
static inline void nand_read_buf8(void *buf, int count)
|
||||
{
|
||||
int i;
|
||||
u8 *p = (u8 *)buf;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
*p++ = __nand_data8();
|
||||
}
|
||||
#define nand_read_buf nand_read_buf8
|
||||
|
||||
#endif
|
||||
|
||||
/* Correct 1~9-bit errors in 512-bytes data */
|
||||
static void rs_correct(unsigned char *dat, int idx, int mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
idx--;
|
||||
|
||||
i = idx + (idx >> 3);
|
||||
if (i >= 512)
|
||||
return;
|
||||
|
||||
mask <<= (idx & 0x7);
|
||||
|
||||
dat[i] ^= mask & 0xff;
|
||||
if (i < 511)
|
||||
dat[i+1] ^= (mask >> 8) & 0xff;
|
||||
}
|
||||
|
||||
static int nand_read_oob(int page_addr, uchar *buf, int size)
|
||||
{
|
||||
int col_addr;
|
||||
if (page_size != 512)
|
||||
col_addr = page_size;
|
||||
else {
|
||||
col_addr = 0;
|
||||
__nand_dev_ready();
|
||||
}
|
||||
|
||||
if (page_size != 512)
|
||||
/* Send READ0 command */
|
||||
__nand_cmd(NAND_CMD_READ0);
|
||||
else
|
||||
/* Send READOOB command */
|
||||
__nand_cmd(NAND_CMD_READOOB);
|
||||
|
||||
/* Send column address */
|
||||
__nand_addr(col_addr & 0xff);
|
||||
if (page_size != 512)
|
||||
__nand_addr((col_addr >> 8) & 0xff);
|
||||
|
||||
/* Send page address */
|
||||
__nand_addr(page_addr & 0xff);
|
||||
__nand_addr((page_addr >> 8) & 0xff);
|
||||
#ifdef NAND_ROW_CYCLE == 3
|
||||
__nand_addr((page_addr >> 16) & 0xff);
|
||||
#endif
|
||||
|
||||
/* Send READSTART command for 2048 or 4096 ps NAND */
|
||||
if (page_size != 512)
|
||||
__nand_cmd(NAND_CMD_READSTART);
|
||||
|
||||
/* Wait for device ready */
|
||||
__nand_dev_ready();
|
||||
|
||||
/* Read oob data */
|
||||
nand_read_buf(buf, size);
|
||||
if (page_size == 512)
|
||||
__nand_dev_ready();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nand_read_page(int page_addr, uchar *dst, uchar *oobbuf)
|
||||
{
|
||||
uchar *databuf = dst, *tmpbuf;
|
||||
int i, j;
|
||||
|
||||
/*
|
||||
* Read oob data
|
||||
*/
|
||||
nand_read_oob(page_addr, oobbuf, oob_size);
|
||||
|
||||
/*
|
||||
* Read page data
|
||||
*/
|
||||
|
||||
/* Send READ0 command */
|
||||
__nand_cmd(NAND_CMD_READ0);
|
||||
|
||||
/* Send column address */
|
||||
__nand_addr(0);
|
||||
if (page_size != 512)
|
||||
__nand_addr(0);
|
||||
|
||||
/* Send page address */
|
||||
__nand_addr(page_addr & 0xff);
|
||||
__nand_addr((page_addr >> 8) & 0xff);
|
||||
#if NAND_ROW_CYCLE == 3
|
||||
__nand_addr((page_addr >> 16) & 0xff);
|
||||
#endif
|
||||
|
||||
/* Send READSTART command for 2048 or 4096 ps NAND */
|
||||
if (page_size != 512)
|
||||
__nand_cmd(NAND_CMD_READSTART);
|
||||
|
||||
/* Wait for device ready */
|
||||
__nand_dev_ready();
|
||||
|
||||
/* Read page data */
|
||||
tmpbuf = databuf;
|
||||
|
||||
for (i = 0; i < ecc_count; i++) {
|
||||
volatile unsigned char *paraddr = (volatile unsigned char *)EMC_NFPAR0;
|
||||
unsigned int stat;
|
||||
|
||||
/* Enable RS decoding */
|
||||
REG_EMC_NFINTS = 0x0;
|
||||
__nand_ecc_rs_decoding();
|
||||
|
||||
/* Read data */
|
||||
nand_read_buf((void *)tmpbuf, ECC_BLOCK);
|
||||
|
||||
/* Set PAR values */
|
||||
for (j = 0; j < PAR_SIZE; j++) {
|
||||
#if defined(CONFIG_SYS_NAND_ECC_POS)
|
||||
*paraddr++ = oobbuf[CONFIG_SYS_NAND_ECC_POS + i*PAR_SIZE + j];
|
||||
#else
|
||||
*paraddr++ = oobbuf[ECC_POS + i*PAR_SIZE + j];
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set PRDY */
|
||||
REG_EMC_NFECR |= EMC_NFECR_PRDY;
|
||||
|
||||
/* Wait for completion */
|
||||
__nand_ecc_decode_sync();
|
||||
|
||||
/* Disable decoding */
|
||||
__nand_ecc_disable();
|
||||
|
||||
/* Check result of decoding */
|
||||
stat = REG_EMC_NFINTS;
|
||||
if (stat & EMC_NFINTS_ERR) {
|
||||
/* Error occurred */
|
||||
/* serial_puts("\n Error occurred\n"); */
|
||||
if (stat & EMC_NFINTS_UNCOR) {
|
||||
/* Uncorrectable error occurred */
|
||||
/* serial_puts("\nUncorrectable error occurred\n"); */
|
||||
}
|
||||
else {
|
||||
unsigned int errcnt, index, mask;
|
||||
|
||||
errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
|
||||
switch (errcnt) {
|
||||
case 4:
|
||||
index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
|
||||
mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
|
||||
rs_correct(tmpbuf, index, mask);
|
||||
/* FALL-THROUGH */
|
||||
case 3:
|
||||
index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
|
||||
mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
|
||||
rs_correct(tmpbuf, index, mask);
|
||||
/* FALL-THROUGH */
|
||||
case 2:
|
||||
index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
|
||||
mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
|
||||
rs_correct(tmpbuf, index, mask);
|
||||
/* FALL-THROUGH */
|
||||
case 1:
|
||||
index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
|
||||
mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
|
||||
rs_correct(tmpbuf, index, mask);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
tmpbuf += ECC_BLOCK;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_NAND_BADBLOCK_PAGE
|
||||
#define CONFIG_SYS_NAND_BADBLOCK_PAGE 0 /* NAND bad block was marked at this page in a block, starting from 0 */
|
||||
#endif
|
||||
|
||||
static void nand_load(int offs, int uboot_size, uchar *dst)
|
||||
{
|
||||
int page;
|
||||
int pagecopy_count;
|
||||
|
||||
__nand_enable();
|
||||
|
||||
page = offs / page_size;
|
||||
pagecopy_count = 0;
|
||||
while (pagecopy_count < (uboot_size / page_size)) {
|
||||
if (page % page_per_block == 0) {
|
||||
nand_read_oob(page + CONFIG_SYS_NAND_BADBLOCK_PAGE, oob_buf, oob_size);
|
||||
if (oob_buf[bad_block_pos] != 0xff) {
|
||||
page += page_per_block;
|
||||
/* Skip bad block */
|
||||
continue;
|
||||
}
|
||||
}
|
||||
/* Load this page to dst, do the ECC */
|
||||
nand_read_page(page, dst, oob_buf);
|
||||
|
||||
dst += page_size;
|
||||
page++;
|
||||
pagecopy_count++;
|
||||
}
|
||||
|
||||
__nand_disable();
|
||||
}
|
||||
|
||||
static void jz_nand_init(void) {
|
||||
|
||||
/* Optimize the timing of nand */
|
||||
REG_EMC_SMCR1 = 0x094c4400;
|
||||
}
|
||||
|
||||
static void gpio_init(void)
|
||||
{
|
||||
/*
|
||||
* Initialize SDRAM pins
|
||||
*/
|
||||
#if defined(CONFIG_JZ4720)
|
||||
__gpio_as_sdram_16bit_4720();
|
||||
#elif defined(CONFIG_JZ4725)
|
||||
__gpio_as_sdram_16bit_4725();
|
||||
#else
|
||||
__gpio_as_sdram_32bit();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize UART0 pins
|
||||
*/
|
||||
__gpio_as_uart0();
|
||||
}
|
||||
|
||||
static int is_usb_boot()
|
||||
{
|
||||
int keyU = 0;
|
||||
|
||||
__gpio_as_input(KEY_U_IN);
|
||||
__gpio_enable_pull(KEY_U_IN);
|
||||
|
||||
__gpio_as_output(KEY_U_OUT);
|
||||
__gpio_clear_pin(KEY_U_OUT);
|
||||
|
||||
keyU = __gpio_get_pin(KEY_U_IN);
|
||||
|
||||
if (keyU)
|
||||
serial_puts("[U] not pressed\n");
|
||||
else
|
||||
serial_puts("[U] pressed\n");
|
||||
|
||||
return !keyU;
|
||||
}
|
||||
|
||||
void nand_boot(void)
|
||||
{
|
||||
void (*uboot)(void);
|
||||
|
||||
/*
|
||||
* Init hardware
|
||||
*/
|
||||
jz_nand_init();
|
||||
gpio_init();
|
||||
serial_init();
|
||||
|
||||
serial_puts("\n\nNAND Secondary Program Loader\n\n");
|
||||
|
||||
pll_init();
|
||||
sdram_init();
|
||||
|
||||
#if defined(CONFIG_NANONOTE)
|
||||
if(is_usb_boot()) {
|
||||
serial_puts("enter USB BOOT mode\n");
|
||||
usb_boot();
|
||||
}
|
||||
#endif
|
||||
|
||||
page_size = CONFIG_SYS_NAND_PAGE_SIZE;
|
||||
block_size = CONFIG_SYS_NAND_BLOCK_SIZE;
|
||||
page_per_block = CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
|
||||
bad_block_pos = (page_size == 512) ? 5 : 0;
|
||||
oob_size = page_size / 32;
|
||||
ecc_count = page_size / ECC_BLOCK;
|
||||
|
||||
/*
|
||||
* Load U-Boot image from NAND into RAM
|
||||
*/
|
||||
nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
|
||||
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
|
||||
|
||||
uboot = (void (*)(void))CONFIG_SYS_NAND_U_BOOT_START;
|
||||
|
||||
serial_puts("Starting U-Boot ...\n");
|
||||
|
||||
/*
|
||||
* Flush caches
|
||||
*/
|
||||
flush_cache_all();
|
||||
|
||||
/*
|
||||
* Jump to U-Boot image
|
||||
*/
|
||||
(*uboot)();
|
||||
}
|
1669
package/uboot-xburst/patches/001-xburst.patch
Normal file
1669
package/uboot-xburst/patches/001-xburst.patch
Normal file
File diff suppressed because it is too large
Load Diff
13
package/uboot-xburst/patches/005-i2c.patch
Normal file
13
package/uboot-xburst/patches/005-i2c.patch
Normal file
@ -0,0 +1,13 @@
|
||||
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
|
||||
index ef32f13..4e234b4 100644
|
||||
--- a/drivers/i2c/Makefile
|
||||
+++ b/drivers/i2c/Makefile
|
||||
@@ -36,6 +36,7 @@ COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
|
||||
COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
|
||||
COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
|
||||
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
|
||||
+COBJS-$(CONFIG_JZSOC_I2C) += jz_i2c.o
|
||||
|
||||
COBJS := $(COBJS-y)
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
|
23
package/uboot-xburst/patches/009-n516.patch
Normal file
23
package/uboot-xburst/patches/009-n516.patch
Normal file
@ -0,0 +1,23 @@
|
||||
diff --git a/Makefile b/Makefile
|
||||
index ed848f5..04cd32e 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -3448,6 +3448,18 @@ pavo_nand_config : unconfig
|
||||
@echo "TEXT_BASE = 0x80100000" > $(obj)board/qi_lb60/config.tmp
|
||||
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
|
||||
+n516_config : unconfig
|
||||
+ @ >include/config.h
|
||||
+ @echo "#define CONFIG_N516 1" >>include/config.h
|
||||
+ @./mkconfig -a n516 mips mips n516
|
||||
+
|
||||
+n516_nand_config : unconfig
|
||||
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
|
||||
+ @echo "Compile NAND boot image for n516"
|
||||
+ @./mkconfig -a n516 mips mips n516
|
||||
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
|
||||
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
+
|
||||
#########################################################################
|
||||
## MIPS64 5Kc
|
||||
#########################################################################
|
32
package/uboot-xburst/patches/010-sakc.patch
Normal file
32
package/uboot-xburst/patches/010-sakc.patch
Normal file
@ -0,0 +1,32 @@
|
||||
diff --git a/Makefile b/Makefile
|
||||
index a318eb4..7d14b8b 100644
|
||||
--- a/Makefile
|
||||
+++ b/Makefile
|
||||
@@ -3448,6 +3448,13 @@ qi_lb60_config : unconfig
|
||||
@echo "TEXT_BASE = 0x80100000" > $(obj)board/n516/config.tmp
|
||||
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
|
||||
+sakc_config : unconfig
|
||||
+ @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
|
||||
+ @echo "Compile NAND boot image for SAKC"
|
||||
+ @$(MKCONFIG) -a sakc mips mips sakc
|
||||
+ @echo "TEXT_BASE = 0x80100000" > $(obj)board/sakc/config.tmp
|
||||
+ @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
+
|
||||
#########################################################################
|
||||
## MIPS64 5Kc
|
||||
#########################################################################
|
||||
diff --git a/cpu/mips/Makefile b/cpu/mips/Makefile
|
||||
index 33afb66..a177653 100644
|
||||
--- a/cpu/mips/Makefile
|
||||
+++ b/cpu/mips/Makefile
|
||||
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_PURPLE) += asc_serial.o
|
||||
COBJS-$(CONFIG_JZSOC) += jz_serial.o jz_i2c.o jz_mmc.o
|
||||
COBJS-$(CONFIG_JZ4740) += jz4740.o jz4740_nand.o
|
||||
COBJS-$(CONFIG_NANONOTE) += nanonote_gpm940b0.o
|
||||
-
|
||||
+COBJS-$(CONFIG_SAKC) += nanonote_gpm940b0.o
|
||||
|
||||
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
|
||||
|
Loading…
Reference in New Issue
Block a user