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uboot-rockchip: add Orange Pi R1 Plus LTS support
Add support for the Xunlong Orange Pi R1 Plus LTS. Manually generated of-platdata files to avoid swig dependency. Tested-by: Volkan Yetik <no3iverson@gmail.com> Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
ab641efe69
commit
37fed89166
@ -52,6 +52,13 @@ define U-Boot/orangepi-r1-plus-rk3328
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xunlong_orangepi-r1-plus
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endef
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define U-Boot/orangepi-r1-plus-lts-rk3328
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$(U-Boot/rk3328/Default)
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NAME:=Orange Pi R1 Plus LTS
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BUILD_DEVICES:= \
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xunlong_orangepi-r1-plus-lts
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endef
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define U-Boot/roc-cc-rk3328
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$(U-Boot/rk3328/Default)
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NAME:=ROC-RK3328-CC
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@ -95,6 +102,7 @@ UBOOT_TARGETS := \
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nanopi-r2c-rk3328 \
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nanopi-r2s-rk3328 \
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orangepi-r1-plus-rk3328 \
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orangepi-r1-plus-lts-rk3328 \
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roc-cc-rk3328
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UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
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@ -0,0 +1,242 @@
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From 7a9326a96098bc63d2b60538f657c3a533415276 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Sat, 20 May 2023 18:52:14 +0800
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Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus LTS
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The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
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the on-board NIC chip changed from rtl8211e to yt8531c, and RAM type
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changed from DDR4 to LPDDR3.
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The device tree is taken from kernel v6.4-rc1.
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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---
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arch/arm/dts/Makefile | 1 +
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.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 46 +++++++
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arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 40 ++++++
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board/rockchip/evb_rk3328/MAINTAINERS | 6 +
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configs/orangepi-r1-plus-lts-rk3328_defconfig | 114 ++++++++++++++++++
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5 files changed, 207 insertions(+)
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create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
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create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -111,6 +111,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
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rk3328-nanopi-r2c.dtb \
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rk3328-nanopi-r2s.dtb \
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rk3328-orangepi-r1-plus.dtb \
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+ rk3328-orangepi-r1-plus-lts.dtb \
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rk3328-roc-cc.dtb \
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rk3328-rock64.dtb \
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rk3328-rock-pi-e.dtb
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
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@@ -0,0 +1,46 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+/*
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+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
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+ * (C) Copyright 2020 David Bauer
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+ */
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+
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+#include "rk3328-u-boot.dtsi"
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+#include "rk3328-sdram-lpddr3-666.dtsi"
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+/ {
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+ chosen {
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+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
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+ };
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+};
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+
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+&gpio0 {
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+ u-boot,dm-spl;
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+};
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+
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+&pinctrl {
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+ u-boot,dm-spl;
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+};
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+
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+&sdmmc0m1_gpio {
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+ u-boot,dm-spl;
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+};
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+
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+&pcfg_pull_up_4ma {
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+ u-boot,dm-spl;
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+};
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+
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+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
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+&vcc_sd {
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+ u-boot,dm-spl;
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+};
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+
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+&gmac2io {
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+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 10000 50000>;
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+};
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+
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+&spi0 {
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+ spi_flash: spiflash@0 {
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+ u-boot,dm-pre-reloc;
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
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@@ -0,0 +1,40 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
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+ * (http://www.orangepi.org)
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+ *
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+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
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+ */
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+
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+/dts-v1/;
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+#include "rk3328-orangepi-r1-plus.dts"
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+
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+/ {
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+ model = "Xunlong Orange Pi R1 Plus LTS";
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+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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+};
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+
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+&gmac2io {
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+ phy-handle = <&yt8531c>;
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+ tx_delay = <0x19>;
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+ rx_delay = <0x05>;
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+
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+ mdio {
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+ /delete-node/ ethernet-phy@1;
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+
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+ yt8531c: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+
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+ motorcomm,clk-out-frequency-hz = <125000000>;
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+ motorcomm,keep-pll-enabled;
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+ motorcomm,auto-sleep-disabled;
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+
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <15000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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--- a/board/rockchip/evb_rk3328/MAINTAINERS
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+++ b/board/rockchip/evb_rk3328/MAINTAINERS
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@@ -24,6 +24,12 @@ S: Maintained
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F: configs/orangepi-r1-plus-rk3328_defconfig
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F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
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+ORANGEPI-R1-PLUS-LTS-RK3328
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+M: Tianling Shen <cnsztl@gmail.com>
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+S: Maintained
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+F: configs/orangepi-r1-plus-lts-rk3328_defconfig
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+F: arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
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+
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ROC-RK3328-CC
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M: Loic Devulder <ldevulder@suse.com>
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M: Chen-Yu Tsai <wens@csie.org>
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--- /dev/null
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+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
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@@ -0,0 +1,98 @@
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+CONFIG_ARM=y
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_SYS_TEXT_BASE=0x00200000
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+CONFIG_SPL_GPIO_SUPPORT=y
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+CONFIG_ENV_OFFSET=0x3F8000
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+CONFIG_ROCKCHIP_RK3328=y
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+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
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+CONFIG_TPL_LIBCOMMON_SUPPORT=y
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+CONFIG_TPL_LIBGENERIC_SUPPORT=y
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+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
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+CONFIG_SPL_STACK_R_ADDR=0x600000
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_DEBUG_UART_BASE=0xFF130000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_SYSINFO=y
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+CONFIG_DEBUG_UART=y
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+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
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+# CONFIG_ANDROID_BOOT_IMAGE is not set
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
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+CONFIG_MISC_INIT_R=y
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
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+CONFIG_SPL_STACK_R=y
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+CONFIG_SPL_I2C_SUPPORT=y
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+CONFIG_SPL_POWER_SUPPORT=y
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+CONFIG_SPL_ATF=y
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+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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+CONFIG_CMD_BOOTZ=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+# CONFIG_CMD_SETEXPR is not set
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+CONFIG_CMD_TIME=y
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_TPL_OF_CONTROL=y
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+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_TPL_OF_PLATDATA=y
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+CONFIG_ENV_IS_IN_MMC=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_NET_RANDOM_ETHADDR=y
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+CONFIG_TPL_DM=y
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+CONFIG_REGMAP=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_TPL_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_TPL_SYSCON=y
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+CONFIG_CLK=y
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+CONFIG_SPL_CLK=y
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+CONFIG_FASTBOOT_BUF_ADDR=0x800800
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+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_SF_DEFAULT_SPEED=20000000
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+CONFIG_DM_ETH=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PINCTRL=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_DM_REGULATOR=y
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+CONFIG_REGULATOR_PWM=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_RAM=y
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+CONFIG_SPL_RAM=y
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+CONFIG_TPL_RAM=y
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+CONFIG_DM_RESET=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYSRESET=y
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+# CONFIG_TPL_SYSRESET is not set
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_XHCI_DWC3=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_DWC2=y
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+CONFIG_USB_DWC3=y
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+# CONFIG_USB_DWC3_GADGET is not set
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+CONFIG_USB_GADGET=y
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+CONFIG_USB_GADGET_DWC2_OTG=y
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+CONFIG_SPL_TINY_MEMSET=y
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+CONFIG_TPL_TINY_MEMSET=y
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+CONFIG_ERRNO_STR=y
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@ -0,0 +1,24 @@
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/*
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* DO NOT MODIFY
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*
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* Declares externs for all device/uclass instances.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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/* driver declarations - these allow DM_DRIVER_GET() to be used */
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extern U_BOOT_DRIVER(rockchip_rk3328_cru);
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extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
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extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
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extern U_BOOT_DRIVER(ns16550_serial);
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extern U_BOOT_DRIVER(rockchip_rk3328_spi);
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extern U_BOOT_DRIVER(rockchip_rk3328_grf);
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/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
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extern UCLASS_DRIVER(clk);
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extern UCLASS_DRIVER(mmc);
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extern UCLASS_DRIVER(ram);
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extern UCLASS_DRIVER(serial);
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extern UCLASS_DRIVER(syscon);
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@ -0,0 +1,170 @@
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/*
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* DO NOT MODIFY
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*
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* Declares the U_BOOT_DRIVER() records and platform data.
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* This was generated by dtoc from a .dtb (device tree binary) file.
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*/
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/* Allow use of U_BOOT_DRVINFO() in this file */
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#define DT_PLAT_C
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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/*
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* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
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*
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* idx driver_info driver
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* --- -------------------- --------------------
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* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
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* 1: dmc rockchip_rk3328_dmc
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* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
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* 3: serial_at_ff130000 ns16550_serial
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* 4: spi_at_ff190000 rockchip_rk3328_spi
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* 5: syscon_at_ff100000 rockchip_rk3328_grf
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* --- -------------------- --------------------
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*/
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/*
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* Node /clock-controller@ff440000 index 0
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* driver rockchip_rk3328_cru parent None
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*/
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static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
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.reg = {0xff440000, 0x1000},
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.rockchip_grf = 0x38,
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};
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U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
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.name = "rockchip_rk3328_cru",
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.plat = &dtv_clock_controller_at_ff440000,
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.plat_size = sizeof(dtv_clock_controller_at_ff440000),
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.parent_idx = -1,
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};
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/*
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* Node /dmc index 1
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* driver rockchip_rk3328_dmc parent None
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*/
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static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
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.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
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0xff720000, 0x1000, 0xff798000, 0x1000},
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.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
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0x10, 0x10, 0x0, 0x8c48a18a, 0x0, 0x21, 0x482, 0x15,
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0x21a, 0xff, 0x14d, 0x6, 0x1, 0x0, 0x0, 0x0,
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0x43041008, 0x64, 0x140023, 0xd0, 0x220002, 0xd4, 0x10000, 0xd8,
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0x703, 0xdc, 0x830004, 0xe0, 0x10000, 0xe4, 0x70003, 0xf4,
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0xf011f, 0x100, 0x6090b07, 0x104, 0x2020b, 0x108, 0x2030506, 0x10c,
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0x505000, 0x110, 0x3020204, 0x114, 0x1010303, 0x118, 0x2020003, 0x120,
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0x303, 0x138, 0x25, 0x180, 0x3c000f, 0x184, 0x900000, 0x190,
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0x7020000, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0x900090c, 0x244,
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0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
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0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0x6, 0x2c,
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0x0, 0x30, 0x3, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
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0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
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0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
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0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
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0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
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0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
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0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
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0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
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0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
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0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
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0x77, 0x77, 0x79, 0x9},
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};
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U_BOOT_DRVINFO(dmc) = {
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.name = "rockchip_rk3328_dmc",
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.plat = &dtv_dmc,
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.plat_size = sizeof(dtv_dmc),
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.parent_idx = -1,
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};
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||||
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_sd_highspeed = true,
|
||||
.clocks = {
|
||||
{0, {317}},
|
||||
{0, {33}},
|
||||
{0, {74}},
|
||||
{0, {78}},},
|
||||
.disable_wp = true,
|
||||
.fifo_depth = 0x100,
|
||||
.interrupts = {0x0, 0xc, 0x4},
|
||||
.max_frequency = 0x8f0d180,
|
||||
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff500000, 0x4000},
|
||||
.u_boot_spl_fifo_mode = true,
|
||||
.vmmc_supply = 0x49,
|
||||
};
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /serial@ff130000 index 3
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
{0, {40}},
|
||||
{0, {212}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
||||
.interrupts = {0x0, 0x39, 0x4},
|
||||
.pinctrl_0 = 0x24,
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff130000, 0x100},
|
||||
.reg_io_width = 0x4,
|
||||
.reg_shift = 0x2,
|
||||
};
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /spi@ff190000 index 4 */
|
||||
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
|
||||
.clocks = {
|
||||
{0, {32}},
|
||||
{0, {209}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x8, 0x10, 0x9},
|
||||
.interrupts = {0x0, 0x31, 0x4},
|
||||
.pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff190000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(spi_at_ff190000) = {
|
||||
.name = "rockchip_rk3328_spi",
|
||||
.plat = &dtv_spi_at_ff190000,
|
||||
.plat_size = sizeof(dtv_spi_at_ff190000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /syscon@ff100000 index 5
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Defines the structs used to hold devicetree data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <linux/libfdt.h>
|
||||
struct dtd_ns16550_serial {
|
||||
fdt32_t clock_frequency;
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0;
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
fdt32_t reg_io_width;
|
||||
fdt32_t reg_shift;
|
||||
};
|
||||
struct dtd_rockchip_rk3288_dw_mshc {
|
||||
fdt32_t bus_width;
|
||||
bool cap_sd_highspeed;
|
||||
struct phandle_1_arg clocks[4];
|
||||
bool disable_wp;
|
||||
fdt32_t fifo_depth;
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t max_frequency;
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
bool u_boot_spl_fifo_mode;
|
||||
fdt32_t vmmc_supply;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_cru {
|
||||
fdt64_t reg[2];
|
||||
fdt32_t rockchip_grf;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_dmc {
|
||||
fdt64_t reg[12];
|
||||
fdt32_t rockchip_sdram_params[196];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_grf {
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_spi {
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user