mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
add 2.6.34 support
SVN-Revision: 22452
This commit is contained in:
parent
3144d90706
commit
2df3583611
239
target/linux/octeon/config-2.6.34
Normal file
239
target/linux/octeon/config-2.6.34
Normal file
@ -0,0 +1,239 @@
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# CONFIG_32BIT is not set
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CONFIG_64BIT=y
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CONFIG_64BIT_PHYS_ADDR=y
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# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
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# CONFIG_AR7 is not set
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
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CONFIG_ARCH_POPULATES_NODE_MAP=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_SUPPORTS_MSI=y
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CONFIG_ARCH_SUPPORTS_OPROFILE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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# CONFIG_ARPD is not set
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# CONFIG_BCM47XX is not set
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# CONFIG_BCM63XX is not set
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CONFIG_BINFMT_ELF32=y
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CONFIG_BITREVERSE=y
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CONFIG_BLOCK_COMPAT=y
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# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
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CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
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# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
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CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
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CONFIG_BSD_PROCESS_ACCT_V3=y
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# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
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CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
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CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
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# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
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CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_CEVT_R4K=y
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CONFIG_CEVT_R4K_LIB=y
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CONFIG_COMPAT=y
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CONFIG_COMPAT_BRK=y
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CONFIG_COMPAT_NETLINK_MESSAGES=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_CAVIUM_OCTEON=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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# CONFIG_CPU_LITTLE_ENDIAN is not set
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# CONFIG_CPU_LOONGSON2E is not set
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# CONFIG_CPU_LOONGSON2F is not set
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# CONFIG_CPU_MIPS32_R1 is not set
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# CONFIG_CPU_MIPS32_R2 is not set
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# CONFIG_CPU_MIPS64_R1 is not set
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# CONFIG_CPU_MIPS64_R2 is not set
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CONFIG_CPU_MIPSR2=y
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# CONFIG_CPU_NEVADA is not set
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# CONFIG_CPU_R10000 is not set
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# CONFIG_CPU_R3000 is not set
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# CONFIG_CPU_R4300 is not set
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# CONFIG_CPU_R4X00 is not set
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# CONFIG_CPU_R5000 is not set
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# CONFIG_CPU_R5432 is not set
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# CONFIG_CPU_R5500 is not set
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# CONFIG_CPU_R6000 is not set
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# CONFIG_CPU_R8000 is not set
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# CONFIG_CPU_RM7000 is not set
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# CONFIG_CPU_RM9000 is not set
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# CONFIG_CPU_SB1 is not set
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CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_HUGEPAGES=y
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# CONFIG_CPU_TX39XX is not set
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# CONFIG_CPU_TX49XX is not set
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# CONFIG_CPU_VR41XX is not set
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CONFIG_CRAMFS=y
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# CONFIG_CRYPTO_PCRYPT is not set
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_KERNEL=y
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CONFIG_DEBUG_SPINLOCK=y
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CONFIG_DEBUG_SPINLOCK_SLEEP=y
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CONFIG_DECOMPRESS_LZMA=y
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CONFIG_DETECT_HUNG_TASK=y
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CONFIG_DETECT_SOFTLOCKUP=y
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CONFIG_DEVKMEM=y
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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CONFIG_DMA_COHERENT=y
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CONFIG_DNOTIFY=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_ELF_CORE=y
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CONFIG_ENABLE_MUST_CHECK=y
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# CONFIG_FLATMEM_MANUAL is not set
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CONFIG_FRAME_WARN=2048
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# CONFIG_FW_LOADER is not set
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_FIND_LAST_BIT=y
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
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# CONFIG_HAMRADIO is not set
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAVE_ARCH_KGDB=y
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CONFIG_HAVE_DYNAMIC_FTRACE=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
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CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_MEMORY_PRESENT=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_SYSCALL_WRAPPERS=y
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# CONFIG_HIGH_RES_TIMERS is not set
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# CONFIG_HUGETLBFS is not set
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CONFIG_HW_HAS_PCI=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_OCTEON=y
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CONFIG_HZ=250
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# CONFIG_HZ_100 is not set
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CONFIG_HZ_250=y
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CONFIG_INITRAMFS_SOURCE=""
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# CONFIG_INLINE_READ_UNLOCK is not set
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# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
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# CONFIG_INLINE_SPIN_UNLOCK is not set
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# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
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# CONFIG_INLINE_WRITE_UNLOCK is not set
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# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
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CONFIG_INOTIFY=y
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CONFIG_INOTIFY_USER=y
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CONFIG_IRQ_CPU=y
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CONFIG_IRQ_CPU_OCTEON=y
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CONFIG_IRQ_PER_CPU=y
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CONFIG_KALLSYMS=y
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CONFIG_KEXEC=y
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CONFIG_LEGACY_PTYS=y
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CONFIG_LEGACY_PTY_COUNT=256
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CONFIG_LOCK_KERNEL=y
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CONFIG_LOONGSON_UART_BASE=y
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# CONFIG_MACH_ALCHEMY is not set
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# CONFIG_MACH_DECSTATION is not set
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# CONFIG_MACH_JAZZ is not set
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# CONFIG_MACH_LOONGSON is not set
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# CONFIG_MACH_TX39XX is not set
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# CONFIG_MACH_TX49XX is not set
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# CONFIG_MACH_VR41XX is not set
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_MDIO_OCTEON=y
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# CONFIG_MIKROTIK_RB532 is not set
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CONFIG_MIPS=y
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CONFIG_MIPS32_COMPAT=y
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CONFIG_MIPS32_N32=y
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CONFIG_MIPS32_O32=y
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# CONFIG_MIPS_COBALT is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=7
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# CONFIG_MIPS_MACHINE is not set
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# CONFIG_MIPS_MALTA is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_MT_SMP is not set
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# CONFIG_MIPS_MT_SMTC is not set
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CONFIG_MIPS_PGD_C0_CONTEXT=y
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# CONFIG_MIPS_SIM is not set
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# CONFIG_MISC_DEVICES is not set
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# CONFIG_MTD_CFI_INTELEXT is not set
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# CONFIG_MTD_COMPLEX_MAPPINGS is not set
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MUTEX_SPIN_ON_OWNER=y
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# CONFIG_NETWORK_FILESYSTEMS is not set
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# CONFIG_NO_IOPORT is not set
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CONFIG_NR_CPUS=16
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CONFIG_NR_CPUS_DEFAULT_16=y
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# CONFIG_NXP_STB220 is not set
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# CONFIG_NXP_STB225 is not set
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CONFIG_OCTEON_ETHERNET=y
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CONFIG_OCTEON_MGMT_ETHERNET=y
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CONFIG_PAGEFLAGS_EXTENDED=y
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# CONFIG_PARTITION_ADVANCED is not set
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CONFIG_PCI=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PHYLIB=y
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CONFIG_PHYS_ADDR_T_64BIT=y
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# CONFIG_PMC_MSP is not set
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_STB810 is not set
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CONFIG_POSIX_MQUEUE=y
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CONFIG_POSIX_MQUEUE_SYSCTL=y
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# CONFIG_POWERTV is not set
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CONFIG_PROC_PAGE_MONITOR=y
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CONFIG_RELAY=y
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CONFIG_SCHED_DEBUG=y
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CONFIG_SCHED_OMIT_FRAME_POINTER=y
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# CONFIG_SCSI_DMA is not set
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CONFIG_SCSI_MOD=y
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CONFIG_SECCOMP=y
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# CONFIG_SERIAL_8250_EXTENDED is not set
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# CONFIG_SGI_IP22 is not set
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# CONFIG_SGI_IP27 is not set
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# CONFIG_SGI_IP28 is not set
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# CONFIG_SGI_IP32 is not set
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# CONFIG_SIBYTE_BIGSUR is not set
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# CONFIG_SIBYTE_CARMEL is not set
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# CONFIG_SIBYTE_CRHINE is not set
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# CONFIG_SIBYTE_CRHONE is not set
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# CONFIG_SIBYTE_LITTLESUR is not set
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# CONFIG_SIBYTE_RHONE is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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CONFIG_SMP=y
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CONFIG_SPARSEMEM=y
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CONFIG_SPARSEMEM_MANUAL=y
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CONFIG_SPARSEMEM_STATIC=y
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CONFIG_SPLIT_PTLOCK_CPUS=999999
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CONFIG_STOP_MACHINE=y
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CONFIG_SWAP_IO_SPACE=y
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CONFIG_SYSFS_DEPRECATED=y
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CONFIG_SYSFS_DEPRECATED_V2=y
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CONFIG_SYSVIPC_COMPAT=y
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CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
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CONFIG_SYS_SUPPORTS_HIGHMEM=y
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CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
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CONFIG_SYS_SUPPORTS_HUGETLBFS=y
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CONFIG_SYS_SUPPORTS_SMP=y
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# CONFIG_TC35815 is not set
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# CONFIG_TINY_RCU is not set
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CONFIG_TREE_RCU=y
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CONFIG_USB_SUPPORT=y
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CONFIG_USE_GENERIC_SMP_HELPERS=y
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# CONFIG_VLAN_8021Q is not set
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CONFIG_VM_EVENT_COUNTERS=y
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CONFIG_WEAK_ORDERING=y
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CONFIG_ZONE_DMA_FLAG=0
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77
target/linux/octeon/patches-2.6.34/001-wndap330_hacks.patch
Normal file
77
target/linux/octeon/patches-2.6.34/001-wndap330_hacks.patch
Normal file
@ -0,0 +1,77 @@
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--- a/drivers/staging/octeon/cvmx-helper-board.c
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+++ b/drivers/staging/octeon/cvmx-helper-board.c
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@@ -90,7 +90,7 @@ int cvmx_helper_board_get_mii_address(in
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case CVMX_BOARD_TYPE_KODAMA:
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case CVMX_BOARD_TYPE_EBH3100:
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case CVMX_BOARD_TYPE_HIKARI:
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- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
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/*
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@@ -103,6 +103,12 @@ int cvmx_helper_board_get_mii_address(in
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return 9;
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else
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return -1;
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+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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+ /* We have only one port, using GMII */
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+ if (ipd_port == 0)
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+ return 9;
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+ else
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+ return -1;
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case CVMX_BOARD_TYPE_NAC38:
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/* Board has 8 RGMII ports PHYs are 0-7 */
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if ((ipd_port >= 0) && (ipd_port < 4))
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@@ -213,7 +219,7 @@ cvmx_helper_link_info_t __cvmx_helper_bo
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result.s.speed = 1000;
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return result;
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case CVMX_BOARD_TYPE_EBH3100:
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- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
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/* Port 1 on these boards is always Gigabit */
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@@ -225,6 +231,9 @@ cvmx_helper_link_info_t __cvmx_helper_bo
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}
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/* Fall through to the generic code below */
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break;
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+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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+ is_broadcom_phy = 1;
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+ break;
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case CVMX_BOARD_TYPE_CUST_NB5:
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/* Port 1 on these boards is always Gigabit */
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if (ipd_port == 1) {
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--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
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+++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
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@@ -66,13 +66,15 @@ int __cvmx_helper_rgmii_probe(int interf
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cvmx_dprintf("ERROR: RGMII initialize called in "
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"SPI interface\n");
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} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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- || OCTEON_IS_MODEL(OCTEON_CN30XX)
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+ //|| OCTEON_IS_MODEL(OCTEON_CN30XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
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/*
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* On these chips "type" says we're in
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* GMII/MII mode. This limits us to 2 ports
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*/
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num_ports = 2;
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+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
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+ num_ports = 1;
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} else {
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cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
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__func__);
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--- a/arch/mips/pci/pci-octeon.c
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+++ b/arch/mips/pci/pci-octeon.c
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@@ -210,9 +210,11 @@ const char *octeon_get_pci_interrupts(vo
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/* This is really the NAC38 */
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return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
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case CVMX_BOARD_TYPE_EBH3100:
|
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- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
|
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+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
|
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return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
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+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
|
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+ return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
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case CVMX_BOARD_TYPE_BBGW_REF:
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return "AABCD";
|
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case CVMX_BOARD_TYPE_THUNDER:
|
21
target/linux/octeon/patches-2.6.34/002-nb5_fixup.patch
Normal file
21
target/linux/octeon/patches-2.6.34/002-nb5_fixup.patch
Normal file
@ -0,0 +1,21 @@
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--- a/arch/mips/pci/pci-octeon.c
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+++ b/arch/mips/pci/pci-octeon.c
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@@ -217,6 +217,8 @@ const char *octeon_get_pci_interrupts(vo
|
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return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
|
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case CVMX_BOARD_TYPE_BBGW_REF:
|
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return "AABCD";
|
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+ case CVMX_BOARD_TYPE_CUST_NB5:
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+ return "ABDABAAAAAAAAAAAAAAAAAAAAAAAAAAA";
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case CVMX_BOARD_TYPE_THUNDER:
|
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case CVMX_BOARD_TYPE_EBH3000:
|
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default:
|
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--- a/drivers/staging/octeon/cvmx-helper-board.c
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+++ b/drivers/staging/octeon/cvmx-helper-board.c
|
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@@ -707,6 +707,7 @@ cvmx_helper_board_usb_clock_types_t __cv
|
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{
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switch (cvmx_sysinfo_get()->board_type) {
|
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case CVMX_BOARD_TYPE_BBGW_REF:
|
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+ case CVMX_BOARD_TYPE_CUST_NB5:
|
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return USB_CLOCK_TYPE_CRYSTAL_12;
|
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}
|
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return USB_CLOCK_TYPE_REF_48;
|
@ -0,0 +1,40 @@
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When building with a toolchain that is configured to produce 32-bits executable
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by default, we will produce __lshrti3 in sched_clock() which is never resolved
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so the kernel fails to link. Unconditionally use the inline assemble version
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as suggested by David Daney, which works around the issue.
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|
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CC: David Daney <ddaney@caviumnetworks.com>
|
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
|
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---
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arch/mips/cavium-octeon/csrc-octeon.c | 8 --------
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1 files changed, 0 insertions(+), 8 deletions(-)
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diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
|
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index 0bf4bbe..36400d2 100644
|
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--- a/arch/mips/cavium-octeon/csrc-octeon.c
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+++ b/arch/mips/cavium-octeon/csrc-octeon.c
|
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@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
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unsigned long long notrace sched_clock(void)
|
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{
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||||
/* 64-bit arithmatic can overflow, so use 128-bit. */
|
||||
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
|
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u64 t1, t2, t3;
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unsigned long long rv;
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u64 mult = clocksource_mips.mult;
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@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
|
||||
: [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
|
||||
: "hi", "lo");
|
||||
return rv;
|
||||
-#else
|
||||
- /* GCC > 4.3 do it the easy way. */
|
||||
- unsigned int __attribute__((mode(TI))) t;
|
||||
- t = read_c0_cvmcount();
|
||||
- t = t * clocksource_mips.mult;
|
||||
- return (unsigned long long)(t >> clocksource_mips.shift);
|
||||
-#endif
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
--
|
||||
1.7.1
|
||||
|
Loading…
Reference in New Issue
Block a user