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atheros: v3.18: relocate PCI host DMA base definition

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Put AR2315_PCI_HOST_SDRAM_BASEADDR macro to DMA header, since this is
arbitrary value and not some hw specific constant. Also this relocation
decouples dma from HW specific header.

Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com>

SVN-Revision: 44716
This commit is contained in:
Felix Fietkau 2015-03-13 02:59:43 +00:00
parent f458d11655
commit 2c463148d1
1 changed files with 9 additions and 10 deletions
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19
target/linux/atheros/patches-3.18/100-board.patch
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@ -497,7 +497,7 @@
+#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */ +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
--- /dev/null --- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
@@ -0,0 +1,76 @@ @@ -0,0 +1,82 @@
+/* +/*
+ * This file is subject to the terms and conditions of the GNU General Public + * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive + * License. See the file "COPYING" in the main directory of this archive
@ -511,7 +511,13 @@
+#define __ASM_MACH_ATH25_DMA_COHERENCE_H +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
+ +
+#include <linux/device.h> +#include <linux/device.h>
+#include <ar2315_regs.h> +
+/*
+ * We need some arbitrary non-zero value to be programmed to the BAR1 register
+ * of PCI host controller to enable DMA. The same value should be used as the
+ * offset to calculate the physical address of DMA buffer for PCI devices.
+ */
+#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
+ +
+static inline dma_addr_t ath25_dev_offset(struct device *dev) +static inline dma_addr_t ath25_dev_offset(struct device *dev)
+{ +{
@ -623,7 +629,7 @@
+#endif /* __ASM_MACH_ATH25_WAR_H */ +#endif /* __ASM_MACH_ATH25_WAR_H */
--- /dev/null --- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h +++ b/arch/mips/include/asm/mach-ath25/ar2315_regs.h
@@ -0,0 +1,608 @@ @@ -0,0 +1,601 @@
+/* +/*
+ * Register definitions for AR2315+ + * Register definitions for AR2315+
+ * + *
@ -1217,13 +1223,6 @@
+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
+ +
+/*
+ * We need some arbitrary non-zero value to be programmed to the BAR1 register
+ * of PCI host controller to enable DMA. The same value should be used as the
+ * offset to calculate the physical address of DMA buffer for PCI devices.
+ */
+#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
+
+/* ??? access BAR */ +/* ??? access BAR */
+#define AR2315_PCI_HOST_MBAR0 0x10000000 +#define AR2315_PCI_HOST_MBAR0 0x10000000
+/* RAM access BAR */ +/* RAM access BAR */