From 2bbd43d065dabbd3b8824680a793db8464cf0a2e Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Wed, 11 Dec 2013 10:56:09 +0000 Subject: [PATCH] imx6: add flexcan support backport upstream changes to 3.10: - 0060-flexcan.patch: - add flexcan pinctrl and devicetree config - 0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch - fix a clock issue - 0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch - fix a clock issue Signed-off-by: Tim Harvey SVN-Revision: 39033 --- .../imx6/patches-3.10/0060-flexcan.patch | 92 +++++++++++++++++++ ...correct-clock-as-base-for-bit-rate-c.patch | 37 ++++++++ ...x-the-wrong-parent-of-can_root-clock.patch | 25 +++++ 3 files changed, 154 insertions(+) create mode 100644 target/linux/imx6/patches-3.10/0060-flexcan.patch create mode 100644 target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch create mode 100644 target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch diff --git a/target/linux/imx6/patches-3.10/0060-flexcan.patch b/target/linux/imx6/patches-3.10/0060-flexcan.patch new file mode 100644 index 00000000000..11a66c538ab --- /dev/null +++ b/target/linux/imx6/patches-3.10/0060-flexcan.patch @@ -0,0 +1,92 @@ +--- a/arch/arm/boot/dts/imx6q.dtsi ++++ b/arch/arm/boot/dts/imx6q.dtsi +@@ -163,6 +163,31 @@ + }; + }; + ++ flexcan1 { ++ pinctrl_flexcan1_1: flexcan1grp-1 { ++ fsl,pins = < ++ MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 ++ MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 ++ >; ++ }; ++ ++ pinctrl_flexcan1_2: flexcan1grp-2 { ++ fsl,pins = < ++ MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 ++ MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 ++ >; ++ }; ++ }; ++ ++ flexcan2 { ++ pinctrl_flexcan2_1: flexcan2grp-1 { ++ fsl,pins = < ++ MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 ++ MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 ++ >; ++ }; ++ }; ++ + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -292,13 +292,21 @@ + }; + + can1: flexcan@02090000 { ++ compatible = "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = <0 110 0x04>; ++ clocks = <&clks 108>, <&clks 109>; ++ clock-names = "ipg", "per"; ++ status = "disabled"; + }; + + can2: flexcan@02094000 { ++ compatible = "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = <0 111 0x04>; ++ clocks = <&clks 110>, <&clks 111>; ++ clock-names = "ipg", "per"; ++ status = "disabled"; + }; + + gpt: gpt@02098000 { +--- a/arch/arm/boot/dts/imx6dl.dtsi ++++ b/arch/arm/boot/dts/imx6dl.dtsi +@@ -80,6 +80,31 @@ + }; + }; + ++ flexcan1 { ++ pinctrl_flexcan1_1: flexcan1grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 ++ MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 ++ >; ++ }; ++ ++ pinctrl_flexcan1_2: flexcan1grp-2 { ++ fsl,pins = < ++ MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000 ++ MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 ++ >; ++ }; ++ }; ++ ++ flexcan2 { ++ pinctrl_flexcan2_1: flexcan2grp-1 { ++ fsl,pins = < ++ MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000 ++ MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000 ++ >; ++ }; ++ }; ++ + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < diff --git a/target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch b/target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch new file mode 100644 index 00000000000..c35d7c90c26 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0061-can-flexcan-use-correct-clock-as-base-for-bit-rate-c.patch @@ -0,0 +1,37 @@ +From 1a3e5173f5e72cbf7f0c8927b33082e361c16d72 Mon Sep 17 00:00:00 2001 +From: Marc Kleine-Budde +Date: Mon, 25 Nov 2013 22:15:20 +0100 +Subject: [PATCH] can: flexcan: use correct clock as base for bit rate + calculation + +The flexcan IP core uses the peripheral clock ("per") as basic clock for the +bit timing calculation. However the driver uses the the wrong clock ("ipg"). +This leads to wrong bit rates if the rates on both clock are different. + +This patch fixes the problem by using the correct clock for the bit rate +calculation. + +Cc: linux-stable +Signed-off-by: Marc Kleine-Budde +--- + drivers/net/can/flexcan.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/can/flexcan.c ++++ b/drivers/net/can/flexcan.c +@@ -1025,7 +1025,6 @@ static int flexcan_probe(struct platform + err = PTR_ERR(clk_ipg); + goto failed_clock; + } +- clock_freq = clk_get_rate(clk_ipg); + + clk_per = devm_clk_get(&pdev->dev, "per"); + if (IS_ERR(clk_per)) { +@@ -1033,6 +1032,7 @@ static int flexcan_probe(struct platform + err = PTR_ERR(clk_per); + goto failed_clock; + } ++ clock_freq = clk_get_rate(clk_per); + } + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch new file mode 100644 index 00000000000..8ea02f6dc64 --- /dev/null +++ b/target/linux/imx6/patches-3.10/0062-ARM-i.MX6q-fix-the-wrong-parent-of-can_root-clock.patch @@ -0,0 +1,25 @@ +From 9b3d423707c3b1f6633be1be7e959623e10c596b Mon Sep 17 00:00:00 2001 +From: Jiada Wang +Date: Wed, 30 Oct 2013 04:25:51 -0700 +Subject: [PATCH] ARM: i.MX6q: fix the wrong parent of can_root clock + +instead of pll3_usb_otg the parent of can_root clock +should be pll3_60m. + +Signed-off-by: Jiada Wang +Signed-off-by: Shawn Guo +--- + arch/arm/mach-imx/clk-imx6q.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -442,7 +442,7 @@ int __init mx6q_clocks_init(void) + clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); + clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); + clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); +- clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6); ++ clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); + clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); + clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); + clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);