ExternalVendorCode/openwrt
1
0
Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2024-12-19 05:38:00 +00:00
Code Issues Actions 4 Packages Projects Releases Wiki Activity

mvebu: LS421DE: improve pin configuration

Browse Source 
The CLK125 output pin at the ethernet PHY is connected via capacitor to
GND and nowhere else. Disable it. Also tune the LED masks.

The MPP56 and MPP60 pins at the SoC are conected to the μPD720202 USB3.0
chip:
  - MPP56: wired to PCIe CLKREQ# (out)
  - MPP60: wired to PCIe RESET# (in)
Configure the pcie pinmux for these pins.

Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
This commit is contained in:
Daniel González Cabanelas 2021-04-27 10:58:15 +02:00 committed by Hauke Mehrtens
parent d7956c5728
commit 26a5aea9bc
1 changed files with 12 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
target/linux/mvebu/files/arch/arm/boot/dts/armada-370-buffalo-ls421de.dts
View File

@ -266,15 +266,19 @@
ethphy0: ethernet-phy@0 { /* Marvell 88E1518 */
reg = <0>;
marvell,reg-init = <0x3 0x10 0x1 0x1991>, /* LED function */
<0x3 0x11 0x1 0x4401>, /* LED polarity */
<0x3 0x12 0x1 0x4905>; /* LED timer */
marvell,reg-init = <0x2 0x10 0xffff 0x0006>, /* disable CLK125 */
<0x3 0x10 0x0000 0x1991>, /* LED function */
<0x3 0x11 0x0000 0x4401>, /* LED polarity */
<0x3 0x12 0x0000 0x4905>; /* LED timer */
#thermal-sensor-cells = <0>;
};
};
&pciec {
status = "okay";
pinctrl-0 = <&pmx_pcie>;
pinctrl-names = "default";
/* Connected to uPD720202 USB 3.0 Host */
pcie@1,0 {
status = "okay";
@ -436,4 +440,9 @@
marvell,pins = "mpp55", "mpp57", "mpp62";
marvell,function = "gpio";
};
pmx_pcie: pmx-pcie {
marvell,pins = "mpp56", "mpp60";
marvell,function = "pcie";
};
};