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lantiq: dts: vr9: Add missing properties to the CPU port on the switch

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The CPU port should define the phy-mode and and a PHY phandle or
fixed-link to indicate how the CPU port is connected to the SoC's
Ethernet controller. On xRX200 this is all internal connection, so use
phy-mode = "internal" along with a fixed-link that matches the
definition inside &eth0.

Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net:
dsa: make phylink-related OF properties mandatory on DSA and CPU
ports"). when these properties are missing. Adding the properties
before OpenWrt is updated to Linux 6.0 is harmless.

Suggested-by: Martin Schiller <ms@dev.tdt.de>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This commit is contained in:
Martin Blumenstingl 2022-10-10 17:48:49 +02:00
parent ffd29a55c3
commit 2683cca592
1 changed files with 6 additions and 0 deletions
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6
target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi
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@ -448,7 +448,13 @@
port@6 {
reg = <0x6>;
label = "cpu";
phy-mode = "internal";
ethernet = <&eth0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};