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qualcommax: replace SPI NAND with latest series
Replace the existing SPI NAND controller patches with the latest v14 set that is pending upstream, and include Ansuels patch that fixes it. Bindings patch is removed as there is no point carrying it in OpenWrt. Link: https://github.com/openwrt/openwrt/pull/17908 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Robert Marko
parent
05138fe898
commit
24db75d242
@ -1,97 +0,0 @@
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Date: Sun, 22 Sep 2024 17:03:44 +0530
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Subject: [PATCH] spi: dt-bindings: Introduce qcom,spi-qpic-snand
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Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs.
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It can work both in serial and parallel mode and supports typical
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SPI-NAND page cache operations.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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---
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
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@@ -0,0 +1,83 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm QPIC NAND controller
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+
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+maintainers:
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+ - Md sadre Alam <quic_mdalam@quicinc.com>
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+
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+description:
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+ The QCOM QPIC-SPI-NAND flash controller is an extended version of
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+ the QCOM QPIC NAND flash controller. It can work both in serial
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+ and parallel mode. It supports typical SPI-NAND page cache
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+ operations in single, dual or quad IO mode with pipelined ECC
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+ encoding/decoding using the QPIC ECC HW engine.
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+
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+allOf:
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+ - $ref: /schemas/spi/spi-controller.yaml#
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,spi-qpic-snand
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 3
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+
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+ clock-names:
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+ items:
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+ - const: core
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+ - const: aon
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+ - const: iom
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+
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+ dmas:
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+ items:
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+ - description: tx DMA channel
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+ - description: rx DMA channel
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+ - description: cmd DMA channel
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+
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+ dma-names:
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+ items:
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+ - const: tx
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+ - const: rx
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+ - const: cmd
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+ spi@79b0000 {
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+ compatible = "qcom,spi-qpic-snand";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>,
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+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
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+ clock-names = "core", "aon", "iom";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-engine = <&qpic_nand>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ };
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+ };
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@ -1,6 +1,188 @@
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Date: Sun, 22 Sep 2024 17:03:49 +0530
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Subject: [PATCH] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
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To: <broonie@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
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Subject: [PATCH v14 6/8] spi: spi-qpic: add driver for QCOM SPI NAND flash
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Interface
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Date: Wed, 20 Nov 2024 14:45:04 +0530
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Content preview: This driver implements support for the SPI-NAND mode of
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||||
QCOM
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NAND Flash Interface as a SPI-MEM controller with pipelined ECC
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capability.
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Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Signed-off-by:
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Sricharan Ramabadhran <quic_srichara@quicinc.com> Co-developed-by:
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Varadarajan
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This driver implements support for the SPI-NAND mode of QCOM NAND Flash
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||||
Interface as a SPI-MEM controller with pipelined ECC capability.
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@ -11,6 +193,192 @@ Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
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||||
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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||||
---
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||||
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||||
Change in [v14]
|
||||
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||||
* No Change
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||||
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||||
Change in [v13]
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||||
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||||
* Changed return type of qcom_spi_cmd_mapping() from u32 to
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||||
int to fix the kernel test bot warning
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||||
* Changed type of variable cmd in qcom_spi_write_page() from u32
|
||||
to int
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||||
* Removed unused variable s_op from qcom_spi_write_page()
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||||
* Updated return value variable type from u32 to int in
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||||
qcom_spi_send_cmdaddr()
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||||
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Change in [v12]
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||||
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||||
* Added obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o in Makefile
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||||
to build qpic_common.c based on CONFIG_SPI_QPIC_SNAND
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||||
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||||
Change in [v11]
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||||
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||||
* Fixed build error reported by kernel test bot
|
||||
* Changed "depends on MTD" to "select MTD" in
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||||
drivers/spi/Kconfig file
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||||
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||||
Change in [v10]
|
||||
|
||||
* Fixed compilation warnings reported by kernel test robot.
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||||
* Added depends on CONFIG_MTD
|
||||
* removed extra bracket from statement if (i == (num_cw - 1)) in
|
||||
qcom_spi_program_raw() api.
|
||||
|
||||
Change in [v9]
|
||||
|
||||
* Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand
|
||||
structure
|
||||
* In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix
|
||||
compilation warning
|
||||
* In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix
|
||||
compilation warning
|
||||
* In qcom_spi_init() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables
|
||||
reqs, user, step_size, strength and added cpu_to_le32() macro as well
|
||||
to fix compilation warning
|
||||
* In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
* In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation
|
||||
warning
|
||||
|
||||
Change in [v8]
|
||||
|
||||
* Included "bitfield.h" file to /spi-qpic-snand.c
|
||||
to fix compilation warning reported by kernel test robot
|
||||
* Removed unused variable "steps" in
|
||||
qcom_spi_ecc_init_ctx_pipelined() to fix compilation warning
|
||||
|
||||
Change in [v7]
|
||||
|
||||
* Added read_oob() and write_oob() api
|
||||
|
||||
* Handled offset value for oob layout
|
||||
|
||||
* Made CONFIG_SPI_QPIC_SNAND as bool
|
||||
|
||||
* Added macro ecceng_to_qspi()
|
||||
|
||||
* Added FIELD_PREP() Macro in spi init
|
||||
|
||||
* Added else condition in
|
||||
qcom_spi_ecc_finish_io_req_pipelined()
|
||||
for corrected ecc
|
||||
|
||||
* Handled multiple error condition for api
|
||||
qcom_spi_cmd_mapping()
|
||||
|
||||
* Fix typo for printing debug message
|
||||
|
||||
Change in [v6]
|
||||
|
||||
* Added separate qpic_spi_nand{...} struct
|
||||
|
||||
* moved qpic_ecc and qcom_ecc_stats struct to
|
||||
spi-qpic-snand.c file, since its spi nand
|
||||
specific
|
||||
|
||||
* Added FIELD_PREP() and GENMASK() macro
|
||||
|
||||
* Removed rawnand.h and partition.h from
|
||||
spi-qpic-snand.c
|
||||
|
||||
* Removed oob_buff assignment form
|
||||
qcom_spi_write_page_cache
|
||||
|
||||
* Added qcom_nand_unalloc() in remove() path
|
||||
|
||||
* Fixes all all comments
|
||||
|
||||
Change in [v5]
|
||||
|
||||
* Added raw_read() and raw_write() api
|
||||
|
||||
* Updated commit message
|
||||
|
||||
* Removed register indirection
|
||||
|
||||
* Added qcom_spi_ prefix to all the api
|
||||
|
||||
* Removed snand_set_reg() api.
|
||||
|
||||
* Fixed nandbiterr issue
|
||||
|
||||
* Removed hardcoded num_cw and made it variable
|
||||
|
||||
* Removed hardcoded value for mtd pagesize
|
||||
|
||||
* Added -ENOSUPPORT in cmd mapping for unsupported
|
||||
commands
|
||||
|
||||
* Replace if..else with switch..case statement
|
||||
|
||||
Change in [v4]
|
||||
|
||||
* No change
|
||||
|
||||
Change in [v3]
|
||||
|
||||
* Set SPI_QPIC_SNAND to n and added COMPILE_TEST in Kconfig
|
||||
|
||||
* Made driver name sorted in Make file
|
||||
|
||||
* Made comment like c++
|
||||
|
||||
* Changed macro to functions, snandc_set_read_loc_last()
|
||||
and snandc_set_read_loc_first()
|
||||
|
||||
* Added error handling in snandc_set_reg()
|
||||
|
||||
* Changed into normal conditional statement for
|
||||
return snandc->ecc_stats.failed ? -EBADMSG :
|
||||
snandc->ecc_stats.bitflips;
|
||||
|
||||
* Remove cast of wbuf in qpic_snand_program_execute()
|
||||
function
|
||||
|
||||
* Made num_cw variable instead hardcoded value
|
||||
|
||||
* changed if..else condition of function qpic_snand_io_op()
|
||||
to switch..case statement
|
||||
|
||||
* Added __devm_spi_alloc_controller() api instead of
|
||||
devm_spi_alloc_master()
|
||||
|
||||
* Disabling clock in remove path
|
||||
|
||||
Change in [v2]
|
||||
|
||||
* Added initial support for SPI-NAND driver
|
||||
|
||||
Change in [v1]
|
||||
|
||||
* Added RFC patch for design review
|
||||
|
||||
drivers/mtd/nand/Makefile | 4 +
|
||||
drivers/spi/Kconfig | 9 +
|
||||
drivers/spi/Makefile | 1 +
|
||||
drivers/spi/spi-qpic-snand.c | 1633 ++++++++++++++++++++++++++
|
||||
include/linux/mtd/nand-qpic-common.h | 7 +
|
||||
5 files changed, 1654 insertions(+)
|
||||
create mode 100644 drivers/spi/spi-qpic-snand.c
|
||||
|
||||
--- a/drivers/mtd/nand/Makefile
|
||||
+++ b/drivers/mtd/nand/Makefile
|
||||
@@ -4,7 +4,11 @@ nandcore-objs := core.o bbt.o
|
||||
@ -27,13 +395,14 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
obj-y += spi/
|
||||
--- a/drivers/spi/Kconfig
|
||||
+++ b/drivers/spi/Kconfig
|
||||
@@ -870,6 +870,14 @@ config SPI_QCOM_QSPI
|
||||
@@ -870,6 +870,15 @@ config SPI_QCOM_QSPI
|
||||
help
|
||||
QSPI(Quad SPI) driver for Qualcomm QSPI controller.
|
||||
|
||||
+config SPI_QPIC_SNAND
|
||||
+ bool "QPIC SNAND controller"
|
||||
+ depends on ARCH_QCOM || COMPILE_TEST
|
||||
+ select MTD
|
||||
+ help
|
||||
+ QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
|
||||
+ QPIC controller supports both parallel nand and serial nand.
|
||||
@ -54,7 +423,7 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -0,0 +1,1634 @@
|
||||
@@ -0,0 +1,1633 @@
|
||||
+/*
|
||||
+ * SPDX-License-Identifier: GPL-2.0
|
||||
+ *
|
||||
@ -1072,7 +1441,7 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
+ data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
|
||||
+ oob_size1 = ecc_cfg->bbm_size;
|
||||
+
|
||||
+ if ((i == (num_cw - 1))) {
|
||||
+ if (i == (num_cw - 1)) {
|
||||
+ data_size2 = NANDC_STEP_SIZE - data_size1 -
|
||||
+ ((num_cw - 1) << 2);
|
||||
+ oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
|
||||
@ -1257,9 +1626,9 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
|
||||
+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
|
||||
+{
|
||||
+ u32 cmd = 0x0;
|
||||
+ int cmd = 0x0;
|
||||
+
|
||||
+ switch (opcode) {
|
||||
+ case SPINAND_RESET:
|
||||
@ -1310,15 +1679,12 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
+static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
|
||||
+ const struct spi_mem_op *op)
|
||||
+{
|
||||
+ struct qpic_snand_op s_op = {};
|
||||
+ u32 cmd;
|
||||
+ int cmd;
|
||||
+
|
||||
+ cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
|
||||
+ if (cmd < 0)
|
||||
+ return cmd;
|
||||
+
|
||||
+ s_op.cmd_reg = cmd;
|
||||
+
|
||||
+ if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
|
||||
+ snandc->qspi->data_buf = (u8 *)op->data.buf.out;
|
||||
+
|
||||
@ -1332,9 +1698,11 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
+ u32 cmd;
|
||||
+ int ret, opcode;
|
||||
+
|
||||
+ cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
|
||||
+ if (cmd < 0)
|
||||
+ return cmd;
|
||||
+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ cmd = ret;
|
||||
+
|
||||
+ s_op.cmd_reg = cmd;
|
||||
+ s_op.addr1_reg = op->addr.val;
|
||||
@ -1668,7 +2036,7 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
+
|
||||
+static const struct of_device_id qcom_snandc_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "qcom,spi-qpic-snand",
|
||||
+ .compatible = "qcom,ipq9574-snand",
|
||||
+ .data = &ipq9574_snandc_props,
|
||||
+ },
|
||||
+ {}
|
||||
@ -1681,7 +2049,7 @@ Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
|
||||
+ .of_match_table = qcom_snandc_of_match,
|
||||
+ },
|
||||
+ .probe = qcom_spi_probe,
|
||||
+ .remove = qcom_spi_remove,
|
||||
+ .remove_new = qcom_spi_remove,
|
||||
+};
|
||||
+module_platform_driver(qcom_spi_driver);
|
||||
+
|
||||
@ -0,0 +1,125 @@
|
||||
From 8716f3c03d9f71ed0bd12a26f6e9d1e85cff0d12 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Marangi <ansuelsmth@gmail.com>
|
||||
Date: Thu, 30 Jan 2025 00:27:22 +0100
|
||||
Subject: [PATCH 1/2] spi: spi-qpic: fix broken driver with SPINAND_SET_FEATURE
|
||||
command
|
||||
|
||||
The driver always return probe error with SPINAND_SET_FEATURE command:
|
||||
|
||||
spi-nand: probe of spi0.0 failed with error -1207959538
|
||||
|
||||
The error doesn't match any expected negative error but instead seems to
|
||||
be an u32 converted to an int. Investigating the entire codeflow I
|
||||
reached the culprit: qcom_spi_cmd_mapping.
|
||||
|
||||
Such function can return -EOPNOTSUPP or the cmd to run. Problem is that
|
||||
in the specific context of SPINAND_SET_FEATURE, BIT(31) is set that in
|
||||
the context of an integer, it gets treated as a negative value.
|
||||
|
||||
To correctly handle this, rework the function to return 0 or a "correct"
|
||||
negative error and pass a pointer to store the cmd.
|
||||
|
||||
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
||||
---
|
||||
drivers/spi/spi-qpic-snand.c | 40 +++++++++++++++++-------------------
|
||||
1 file changed, 19 insertions(+), 21 deletions(-)
|
||||
|
||||
--- a/drivers/spi/spi-qpic-snand.c
|
||||
+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -1200,64 +1200,64 @@ static int qcom_spi_program_execute(stru
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
|
||||
+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
|
||||
+ u32 *cmd)
|
||||
{
|
||||
- int cmd = 0x0;
|
||||
-
|
||||
switch (opcode) {
|
||||
case SPINAND_RESET:
|
||||
- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
|
||||
+ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
|
||||
break;
|
||||
case SPINAND_READID:
|
||||
- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
|
||||
+ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
|
||||
break;
|
||||
case SPINAND_GET_FEATURE:
|
||||
- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
|
||||
+ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
|
||||
break;
|
||||
case SPINAND_SET_FEATURE:
|
||||
- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
|
||||
+ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
|
||||
QPIC_SET_FEATURE);
|
||||
break;
|
||||
case SPINAND_READ:
|
||||
if (snandc->qspi->raw_rw) {
|
||||
- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
|
||||
+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
|
||||
SPI_WP | SPI_HOLD | OP_PAGE_READ);
|
||||
} else {
|
||||
- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
|
||||
+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
|
||||
SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
|
||||
}
|
||||
|
||||
break;
|
||||
case SPINAND_ERASE:
|
||||
- cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
|
||||
+ *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
|
||||
SPI_HOLD | SPI_TRANSFER_MODE_x1;
|
||||
break;
|
||||
case SPINAND_WRITE_EN:
|
||||
- cmd = SPINAND_WRITE_EN;
|
||||
+ *cmd = SPINAND_WRITE_EN;
|
||||
break;
|
||||
case SPINAND_PROGRAM_EXECUTE:
|
||||
- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
|
||||
+ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
|
||||
SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
|
||||
break;
|
||||
case SPINAND_PROGRAM_LOAD:
|
||||
- cmd = SPINAND_PROGRAM_LOAD;
|
||||
+ *cmd = SPINAND_PROGRAM_LOAD;
|
||||
break;
|
||||
default:
|
||||
dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
- return cmd;
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
|
||||
const struct spi_mem_op *op)
|
||||
{
|
||||
- int cmd;
|
||||
+ u32 cmd;
|
||||
+ int ret;
|
||||
|
||||
- cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
|
||||
- if (cmd < 0)
|
||||
- return cmd;
|
||||
+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
|
||||
if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
|
||||
snandc->qspi->data_buf = (u8 *)op->data.buf.out;
|
||||
@@ -1272,12 +1272,10 @@ static int qcom_spi_send_cmdaddr(struct
|
||||
u32 cmd;
|
||||
int ret, opcode;
|
||||
|
||||
- ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
|
||||
+ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
- cmd = ret;
|
||||
-
|
||||
s_op.cmd_reg = cmd;
|
||||
s_op.addr1_reg = op->addr.val;
|
||||
s_op.addr2_reg = 0;
|
||||
@ -29,7 +29,7 @@ Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
||||
+ };
|
||||
+
|
||||
+ qpic_nand: qpic-nand@79b0000 {
|
||||
+ compatible = "qcom,spi-qpic-snand";
|
||||
+ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand";
|
||||
+ reg = <0x079b0000 0x10000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user