mirror of
https://github.com/openwrt/openwrt.git
synced 2025-01-19 03:06:35 +00:00
rockchip: remove kernel 5.15 patches and config
As we switched to kernel 6.1, these files can go. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
48c9a4b47c
commit
22a9c4b67d
@ -1,635 +0,0 @@
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CONFIG_64BIT=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
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CONFIG_ARCH_MMAP_RND_BITS=18
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CONFIG_ARCH_MMAP_RND_BITS_MAX=33
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CONFIG_ARCH_MMAP_RND_BITS_MIN=18
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
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CONFIG_ARCH_PROC_KCORE_TEXT=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_STACKWALK=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_WANTS_NO_INSTR=y
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CONFIG_ARC_EMAC_CORE=y
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CONFIG_ARM64=y
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CONFIG_ARM64_4K_PAGES=y
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CONFIG_ARM64_CNP=y
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CONFIG_ARM64_CRYPTO=y
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CONFIG_ARM64_EPAN=y
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CONFIG_ARM64_ERRATUM_819472=y
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CONFIG_ARM64_ERRATUM_824069=y
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CONFIG_ARM64_ERRATUM_826319=y
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CONFIG_ARM64_ERRATUM_827319=y
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CONFIG_ARM64_ERRATUM_832075=y
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CONFIG_ARM64_ERRATUM_843419=y
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CONFIG_ARM64_ERRATUM_858921=y
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CONFIG_ARM64_HW_AFDBM=y
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CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
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CONFIG_ARM64_PAGE_SHIFT=12
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CONFIG_ARM64_PAN=y
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CONFIG_ARM64_PA_BITS=48
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CONFIG_ARM64_PA_BITS_48=y
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CONFIG_ARM64_PTR_AUTH=y
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CONFIG_ARM64_PTR_AUTH_KERNEL=y
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CONFIG_ARM64_RAS_EXTN=y
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CONFIG_ARM64_SVE=y
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CONFIG_ARM64_TAGGED_ADDR_ABI=y
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CONFIG_ARM64_VA_BITS=48
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# CONFIG_ARM64_VA_BITS_39 is not set
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CONFIG_ARM64_VA_BITS_48=y
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CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_GIC_V2M=y
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_GIC_V3_ITS_PCI=y
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CONFIG_ARM_MHU=y
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CONFIG_ARM_MHU_V2=y
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CONFIG_ARM_PSCI_CPUIDLE=y
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CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
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CONFIG_ARM_PSCI_FW=y
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# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
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CONFIG_ARM_SCPI_CPUFREQ=y
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CONFIG_ARM_SCPI_POWER_DOMAIN=y
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CONFIG_ARM_SCPI_PROTOCOL=y
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CONFIG_ARM_SMMU=y
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CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
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# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
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CONFIG_ARM_SMMU_V3=y
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# CONFIG_ARM_SMMU_V3_SVA is not set
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CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
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CONFIG_BACKLIGHT_CLASS_DEVICE=y
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CONFIG_BACKLIGHT_GPIO=y
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CONFIG_BACKLIGHT_PWM=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_BSGLIB=y
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CONFIG_BLK_DEV_BSG_COMMON=y
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# CONFIG_BLK_DEV_INITRD is not set
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CONFIG_BLK_DEV_INTEGRITY=y
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CONFIG_BLK_DEV_INTEGRITY_T10=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_NVME=y
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CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_PM=y
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BSD_PROCESS_ACCT=y
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CONFIG_BSD_PROCESS_ACCT_V3=y
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CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
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CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
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CONFIG_CHARGER_GPIO=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLK_PX30=y
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CONFIG_CLK_RK3308=y
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CONFIG_CLK_RK3328=y
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CONFIG_CLK_RK3368=y
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CONFIG_CLK_RK3399=y
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CONFIG_CLK_RK3568=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=5
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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# CONFIG_CMA_SYSFS is not set
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CONFIG_COMMON_CLK=y
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CONFIG_COMMON_CLK_RK808=y
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CONFIG_COMMON_CLK_ROCKCHIP=y
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CONFIG_COMMON_CLK_SCPI=y
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CONFIGFS_FS=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTIG_ALLOC=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_FREQ=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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CONFIG_CPU_FREQ_GOV_POWERSAVE=y
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_ISOLATION=y
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CONFIG_CPU_LITTLE_ENDIAN=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRASH_DUMP=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CRC_T10DIF=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_AES_ARM64=y
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CONFIG_CRYPTO_AES_ARM64_CE=y
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CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
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CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_CRCT10DIF=y
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CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
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CONFIG_CRYPTO_CRYPTD=y
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# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
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CONFIG_CRYPTO_GHASH_ARM64_CE=y
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CONFIG_CRYPTO_HW=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_RNG2=y
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CONFIG_CRYPTO_SIMD=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_BUGVERBOSE=y
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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CONFIG_DEVFREQ_GOV_PERFORMANCE=y
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CONFIG_DEVFREQ_GOV_POWERSAVE=y
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CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
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CONFIG_DEVFREQ_GOV_USERSPACE=y
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVMEM=y
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# CONFIG_DEVPORT is not set
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CONFIG_DMADEVICES=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_DIRECT_REMAP=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_OPS=y
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CONFIG_DMA_REMAP=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_DWMAC_DWC_QOS_ETH=y
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CONFIG_DWMAC_GENERIC=y
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CONFIG_DWMAC_ROCKCHIP=y
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CONFIG_DW_WATCHDOG=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EMAC_ROCKCHIP=y
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CONFIG_ENERGY_MODEL=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXTCON=y
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CONFIG_F2FS_FS=y
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CONFIG_FANOTIFY=y
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CONFIG_FHANDLE=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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# CONFIG_FORTIFY_SOURCE is not set
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CONFIG_FRAME_POINTER=y
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_CPU_VULNERABILITIES=y
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CONFIG_GENERIC_CSUM=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_FIND_FIRST_BIT=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_MIGRATION=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GPIOLIB_IRQCHIP=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_DWAPB=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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CONFIG_GPIO_ROCKCHIP=y
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CONFIG_GPIO_SYSCON=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HID=y
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CONFIG_HID_GENERIC=y
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CONFIG_HOTPLUG_CPU=y
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CONFIG_HOTPLUG_PCI=y
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# CONFIG_HOTPLUG_PCI_PCIE is not set
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CONFIG_HUGETLBFS=y
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CONFIG_HUGETLB_PAGE=y
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CONFIG_HWMON=y
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CONFIG_HWSPINLOCK=y
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CONFIG_HW_CONSOLE=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_COMPAT=y
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CONFIG_I2C_HELPER_AUTO=y
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CONFIG_I2C_RK3X=y
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CONFIG_IIO=y
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CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
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CONFIG_INDIRECT_PIO=y
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CONFIG_INPUT=y
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CONFIG_INPUT_EVDEV=y
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CONFIG_INPUT_FF_MEMLESS=y
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CONFIG_INPUT_KEYBOARD=y
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CONFIG_INPUT_LEDS=y
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CONFIG_INPUT_MATRIXKMAP=y
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# CONFIG_INPUT_RK805_PWRKEY is not set
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CONFIG_IOMMU_API=y
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# CONFIG_IOMMU_DEBUGFS is not set
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CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
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CONFIG_IOMMU_DMA=y
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CONFIG_IOMMU_IOVA=y
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CONFIG_IOMMU_IO_PGTABLE=y
|
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# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
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CONFIG_IOMMU_IO_PGTABLE_LPAE=y
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# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
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CONFIG_IOMMU_SUPPORT=y
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# CONFIG_IO_STRICT_DEVMEM is not set
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_DOMAIN_HIERARCHY=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_MSI_IOMMU=y
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CONFIG_IRQ_TIME_ACCOUNTING=y
|
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CONFIG_IRQ_WORK=y
|
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CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
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CONFIG_KALLSYMS=y
|
||||
CONFIG_KCMP=y
|
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CONFIG_KEXEC_CORE=y
|
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CONFIG_KEXEC_FILE=y
|
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CONFIG_KSM=y
|
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# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
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CONFIG_LEDS_GPIO=y
|
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CONFIG_LEDS_PWM=y
|
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CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
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CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
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CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_ROCKCHIP_EFUSE=y
|
||||
# CONFIG_NVMEM_ROCKCHIP_OTP is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_RK805=y
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_SARADC is not set
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
# CONFIG_SPI_ROCKCHIP_SFC is not set
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UACCE is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
@ -1,31 +0,0 @@
|
||||
From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Mon, 7 Jun 2021 15:45:37 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
|
||||
|
||||
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
|
||||
stores the MAC address.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -68,6 +68,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&i2c2 {
|
||||
+ eeprom@51 {
|
||||
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||
+ reg = <0x51>;
|
||||
+ pagesize = <16>;
|
||||
+ read-only; /* This holds our MAC */
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1,70 +0,0 @@
|
||||
From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 25 Mar 2023 15:40:20 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
|
||||
|
||||
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
|
||||
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++
|
||||
2 files changed, 41 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C";
|
||||
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8521s>;
|
||||
+ tx_delay = <0x22>;
|
||||
+ rx_delay = <0x12>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8521s: ethernet-phy@3 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <3>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,407 +0,0 @@
|
||||
From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Sat, 3 Dec 2022 15:41:49 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
|
||||
|
||||
Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
|
||||
|
||||
This device is similar to the NanoPi R2S, and has a 16MB
|
||||
SPI NOR (mx25l12805d). The reset button is changed to
|
||||
directly reset the power supply, another detail is that
|
||||
both network ports have independent MAC addresses.
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
|
||||
2 files changed, 374 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -0,0 +1,373 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Based on rk3328-nanopi-r2s.dts, which is:
|
||||
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include "rk3328.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus";
|
||||
+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet1 = &rtl8153;
|
||||
+ mmc0 = &sdmmc;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac_clk: gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ led-0 {
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-1 {
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+
|
||||
+ led-2 {
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: sdmmc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&sdmmc0m1_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_io>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v_lan: vdd-5v-lan-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&lan_vdd_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vdd_5v_lan";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&display_subsystem {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc_io>;
|
||||
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ snps,aal;
|
||||
+ rx_delay = <0x18>;
|
||||
+ tx_delay = <0x24>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk805: pmic@18 {
|
||||
+ compatible = "rockchip,rk805";
|
||||
+ reg = <0x18>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc_sys>;
|
||||
+ vcc2-supply = <&vcc_sys>;
|
||||
+ vcc3-supply = <&vcc_sys>;
|
||||
+ vcc4-supply = <&vcc_sys>;
|
||||
+ vcc5-supply = <&vcc_io>;
|
||||
+ vcc6-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_log: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io>;
|
||||
+ vccio1-supply = <&vcc_io>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io>;
|
||||
+ vccio4-supply = <&vcc_io>;
|
||||
+ vccio5-supply = <&vcc_io>;
|
||||
+ vccio6-supply = <&vcc_io>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac2io {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ sys_led_pin: sys-led-pin {
|
||||
+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ lan {
|
||||
+ lan_vdd_pin: lan-vdd-pin {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&spi0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ flash@0 {
|
||||
+ compatible = "jedec,spi-nor";
|
||||
+ reg = <0>;
|
||||
+ spi-max-frequency = <50000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /* Second port is for USB 3.0 */
|
||||
+ rtl8153: device@2 {
|
||||
+ compatible = "usbbda,8153";
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,71 +0,0 @@
|
||||
From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 25 Mar 2023 15:40:22 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
|
||||
|
||||
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
|
||||
the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
|
||||
identical to OrangePi R1 Plus.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++
|
||||
2 files changed, 41 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
|
||||
+ * (http://www.orangepi.org)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8531c>;
|
||||
+ tx_delay = <0x19>;
|
||||
+ rx_delay = <0x05>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8531c: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <15000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,65 +0,0 @@
|
||||
From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Fri, 10 Jul 2020 21:38:20 +0200
|
||||
Subject: [PATCH] rockchip: use system LED for OpenWrt
|
||||
|
||||
Use the SYS LED on the casing for showing system status.
|
||||
|
||||
This patch is kept separate from the NanoPi R2S support patch, as i plan
|
||||
on submitting the device support upstream.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -16,6 +16,11 @@
|
||||
aliases {
|
||||
ethernet1 = &rtl8153;
|
||||
mmc0 = &sdmmc;
|
||||
+
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -49,18 +54,18 @@
|
||||
|
||||
lan_led: led-0 {
|
||||
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:green:lan";
|
||||
+ label = "green:lan";
|
||||
};
|
||||
|
||||
sys_led: led-1 {
|
||||
gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:red:sys";
|
||||
+ label = "red:sys";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
wan_led: led-2 {
|
||||
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
- label = "nanopi-r2s:green:wan";
|
||||
+ label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -13,6 +13,11 @@
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &emmc;
|
||||
+
|
||||
+ led-boot = &power_led;
|
||||
+ led-failsafe = &power_led;
|
||||
+ led-running = &power_led;
|
||||
+ led-upgrade = &power_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@ -1,24 +0,0 @@
|
||||
From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Sun, 26 Jul 2020 13:32:59 +0200
|
||||
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
|
||||
|
||||
This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
|
||||
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
|
||||
register to match the blink behavior of the other port on the device.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
|
||||
1 file changed, 1 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -402,6 +402,7 @@
|
||||
rtl8153: device@2 {
|
||||
compatible = "usbbda,8153";
|
||||
reg = <2>;
|
||||
+ realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,36 +0,0 @@
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
|
||||
|
||||
The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
|
||||
while U-Boot requires the card to be in 3.3V mode.
|
||||
|
||||
Remove UHS support from the SD controller so the card remains in 3.3V
|
||||
mode. This reduces transfer speeds but ensures a reboot whether from
|
||||
userspace or following a kernel panic is always working.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
|
||||
@@ -335,7 +335,6 @@
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
- sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -121,6 +121,11 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&sdmmc {
|
||||
+ /delete-property/ sd-uhs-sdr104;
|
||||
+ cap-sd-highspeed;
|
||||
+};
|
||||
+
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vdd_5v>;
|
||||
};
|
||||
@ -1,16 +0,0 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -19,6 +19,13 @@
|
||||
model = "FriendlyElec NanoPi R4S";
|
||||
compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &sys_led;
|
||||
+ led-failsafe = &sys_led;
|
||||
+ led-running = &sys_led;
|
||||
+ led-upgrade = &sys_led;
|
||||
+ };
|
||||
+
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
gpio-leds {
|
||||
@ -1,56 +0,0 @@
|
||||
From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 19 May 2023 12:10:52 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1
|
||||
Plus
|
||||
|
||||
Add OpenWrt's LED aliases for showing system status.
|
||||
Also replace function/color with legacy label as OpenWrt relys on it
|
||||
to update LED settings.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
.../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++--------
|
||||
1 file changed, 9 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -17,6 +17,11 @@
|
||||
aliases {
|
||||
ethernet1 = &rtl8153;
|
||||
mmc0 = &sdmmc;
|
||||
+
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -36,22 +41,18 @@
|
||||
pinctrl-names = "default";
|
||||
|
||||
led-0 {
|
||||
- function = LED_FUNCTION_LAN;
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:lan";
|
||||
};
|
||||
|
||||
- led-1 {
|
||||
- function = LED_FUNCTION_STATUS;
|
||||
- color = <LED_COLOR_ID_RED>;
|
||||
+ status_led: led-1 {
|
||||
gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
- linux,default-trigger = "heartbeat";
|
||||
+ label = "red:status";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
- function = LED_FUNCTION_WAN;
|
||||
- color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Fri, 19 May 2023 12:38:04 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1
|
||||
Plus
|
||||
|
||||
Add the correct value for the RTL8153 LED configuration register to
|
||||
match the blink behavior of the other port on the device.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
|
||||
@@ -362,6 +362,7 @@
|
||||
rtl8153: device@2 {
|
||||
compatible = "usbbda,8153";
|
||||
reg = <2>;
|
||||
+ realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
|
||||
@@ -15,6 +15,13 @@
|
||||
model = "FriendlyElec NanoPC-T4";
|
||||
compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
|
||||
|
||||
+ aliases {
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
+ };
|
||||
+
|
||||
vcc12v0_sys: vcc12v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
Loading…
Reference in New Issue
Block a user