kernel/ipq40xx: Restore kernel files for v6.1

This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. See: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html for the original discussion. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-01-18 18:56:37 +00:00 · 2024-03-20 11:09:07 +01:00 · 2024-03-20 11:09:07 +01:00 · 2265413bbf
commit 2265413bbf
parent 9309cfe37a
27 changed files with 5641 additions and 0 deletions
--- a/target/linux/ipq40xx/config-6.1
+++ b/target/linux/ipq40xx/config-6.1
@ -0,0 +1,540 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IPQ40XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8909 is not set
+# CONFIG_ARCH_MSM8916 is not set
+# CONFIG_ARCH_MSM8960 is not set
+# CONFIG_ARCH_MSM8974 is not set
+# CONFIG_ARCH_MSM8X60 is not set
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_CPUIDLE=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
+# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT803X_PHY=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BCH=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC8=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_AES_ARM_BS=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_QCE=y
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
+# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
+CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
+CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MISC=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXTCON=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_74X164=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_WATCHDOG=y
+CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OPTEE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_QCOM_CCI is not set
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IPQ_APSS_PLL is not set
+CONFIG_IPQ_GCC_4019=y
+# CONFIG_IPQ_GCC_6018 is not set
+# CONFIG_IPQ_GCC_806X is not set
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+# CONFIG_KPSS_XCC is not set
+# CONFIG_KRAITCC is not set
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_LEDS_LP5523=y
+CONFIG_LEDS_LP5562=y
+CONFIG_LEDS_LP55XX_COMMON=y
+CONFIG_LEDS_TLC591XX=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ4019=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_HI6421_SPMI is not set
+# CONFIG_MFD_QCOM_RPM is not set
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MSM_GCC_8660 is not set
+# CONFIG_MSM_GCC_8909 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8939 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8976 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_GPUCC_8998 is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+# CONFIG_MSM_MMCC_8998 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_BCH=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_QCOM=y
+# CONFIG_MTD_QCOMSMEM_PARTS is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_QCA8K_IPQ4019=y
+CONFIG_NET_DSA_TAG_OOB=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_QCOM_QFPROM=y
+# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OPTEE=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_EDP is not set
+CONFIG_PHY_QCOM_IPQ4019_USB=y
+# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
+# CONFIG_PHY_QCOM_IPQ806X_USB is not set
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_USB_HS_28NM is not set
+# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
+# CONFIG_PHY_QCOM_USB_SS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+CONFIG_PINCTRL_IPQ4019=y
+# CONFIG_PINCTRL_IPQ8064 is not set
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8226 is not set
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8909 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PINCTRL_SDX65 is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCA807X_PHY=y
+# CONFIG_QCM_DISPCC_2290 is not set
+# CONFIG_QCM_GCC_2290 is not set
+CONFIG_QCOM_A53PLL=y
+# CONFIG_QCOM_ADM is not set
+CONFIG_QCOM_BAM_DMA=y
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_CPR is not set
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GENI_SE is not set
+# CONFIG_QCOM_GSBI is not set
+# CONFIG_QCOM_HFPLL is not set
+# CONFIG_QCOM_ICC_BWMON is not set
+# CONFIG_QCOM_IOMMU is not set
+CONFIG_QCOM_IPQ4019_ESS_EDMA=y
+# CONFIG_QCOM_LLCC is not set
+# CONFIG_QCOM_OCMEM is not set
+# CONFIG_QCOM_PDC is not set
+# CONFIG_QCOM_RMTFS_MEM is not set
+# CONFIG_QCOM_RPMH is not set
+CONFIG_QCOM_SCM=y
+# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMSM is not set
+# CONFIG_QCOM_SOCINFO is not set
+# CONFIG_QCOM_SPM is not set
+# CONFIG_QCOM_STATS is not set
+CONFIG_QCOM_TCSR=y
+# CONFIG_QCOM_TSENS is not set
+CONFIG_QCOM_WDT=y
+# CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_Q6SSTOP_404 is not set
+# CONFIG_QCS_TURING_404 is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+CONFIG_REGULATOR_VCTRL=y
+CONFIG_REGULATOR_VQMMC_IPQ4019=y
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_OPTEE is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SC_CAMCC_7280 is not set
+# CONFIG_SC_DISPCC_7180 is not set
+# CONFIG_SC_GCC_7180 is not set
+# CONFIG_SC_GCC_8280XP is not set
+# CONFIG_SC_GPUCC_7180 is not set
+# CONFIG_SC_LPASSCC_7280 is not set
+# CONFIG_SC_LPASS_CORECC_7180 is not set
+# CONFIG_SC_LPASS_CORECC_7280 is not set
+# CONFIG_SC_MSS_7180 is not set
+# CONFIG_SC_VIDEOCC_7180 is not set
+# CONFIG_SDM_CAMCC_845 is not set
+# CONFIG_SDM_DISPCC_845 is not set
+# CONFIG_SDM_GCC_660 is not set
+# CONFIG_SDM_GCC_845 is not set
+# CONFIG_SDM_GPUCC_845 is not set
+# CONFIG_SDM_LPASSCC_845 is not set
+# CONFIG_SDM_VIDEOCC_845 is not set
+# CONFIG_SDX_GCC_65 is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SKB_EXTENSIONS=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+# CONFIG_SM_CAMCC_8450 is not set
+# CONFIG_SM_GCC_8150 is not set
+# CONFIG_SM_GCC_8250 is not set
+# CONFIG_SM_GCC_8450 is not set
+# CONFIG_SM_GPUCC_6350 is not set
+# CONFIG_SM_GPUCC_8150 is not set
+# CONFIG_SM_GPUCC_8250 is not set
+# CONFIG_SM_GPUCC_8350 is not set
+# CONFIG_SM_VIDEOCC_8150 is not set
+# CONFIG_SM_VIDEOCC_8250 is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_PMIC_CLKDIV is not set
+CONFIG_SRCU=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_TEE=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- a/target/linux/ipq40xx/patches-6.1/001-v6.6-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch
+++ b/target/linux/ipq40xx/patches-6.1/001-v6.6-dt-bindings-clock-qcom-ipq4019-add-missing-networkin.patch
@ -0,0 +1,30 @@
+From be59072c6eeb7535bf9a339fb9d5a8bfae17ac22 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 14 Aug 2023 12:40:23 +0200
+Subject: [PATCH] dt-bindings: clock: qcom: ipq4019: add missing networking
+ resets
+
+Add bindings for the missing networking resets found in IPQ4019 GCC.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+@@ -165,5 +165,11 @@
+ #define GCC_QDSS_BCR					69
+ #define GCC_MPM_BCR					70
+ #define GCC_SPDM_BCR					71
+#define ESS_MAC1_ARES					72
+#define ESS_MAC2_ARES					73
+#define ESS_MAC3_ARES					74
+#define ESS_MAC4_ARES					75
+#define ESS_MAC5_ARES					76
+#define ESS_PSGMII_ARES					77
+ 
+ #endif
--- a/target/linux/ipq40xx/patches-6.1/002-v6.6-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch
+++ b/target/linux/ipq40xx/patches-6.1/002-v6.6-clk-qcom-gcc-ipq4019-add-missing-networking-resets.patch
@ -0,0 +1,30 @@
+From 20014461691efc9e274c3870357152db7f091820 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 14 Aug 2023 12:40:24 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq4019: add missing networking resets
+
+IPQ4019 has more networking related resets that will be required for future
+wired networking support, so lets add them.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1707,6 +1707,12 @@ static const struct qcom_reset_map gcc_i
+ 	[GCC_TCSR_BCR] = {0x22000, 0},
+ 	[GCC_MPM_BCR] = {0x24000, 0},
+ 	[GCC_SPDM_BCR] = {0x25000, 0},
+	[ESS_MAC1_ARES] = {0x1200C, 0},
+	[ESS_MAC2_ARES] = {0x1200C, 1},
+	[ESS_MAC3_ARES] = {0x1200C, 2},
+	[ESS_MAC4_ARES] = {0x1200C, 3},
+	[ESS_MAC5_ARES] = {0x1200C, 4},
+	[ESS_PSGMII_ARES] = {0x1200C, 5},
+ };
+ 
+ static const struct regmap_config gcc_ipq4019_regmap_config = {
--- a/target/linux/ipq40xx/patches-6.1/004-v6.7-firmware-qcom_scm-disable-SDI-if-required.patch
+++ b/target/linux/ipq40xx/patches-6.1/004-v6.7-firmware-qcom_scm-disable-SDI-if-required.patch
@ -0,0 +1,83 @@
+From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 16 Aug 2023 18:45:39 +0200
+Subject: [PATCH] firmware: qcom_scm: disable SDI if required
+
+IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that
+means that WDT being asserted or just trying to reboot will hang the board
+in the debug mode and only pulling the power and repowering will help.
+Some IPQ4019 boards like Google WiFI have it enabled as well.
+
+Luckily, SDI can be disabled via an SCM call.
+
+So, lets use the boolean DT property to identify boards that have SDI
+enabled by default and use the SCM call to disable SDI during SCM probe.
+It is important to disable it as soon as possible as we might have a WDT
+assertion at any time which would then leave the board in debug mode,
+thus disabling it during SCM removal is not enough.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
+Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++
+ drivers/firmware/qcom_scm.h |  1 +
+ 2 files changed, 31 insertions(+)
+
+--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
+@@ -407,6 +407,29 @@ int qcom_scm_set_remote_state(u32 state,
+ }
+ EXPORT_SYMBOL(qcom_scm_set_remote_state);
+ 
+static int qcom_scm_disable_sdi(void)
+{
+	int ret;
+	struct qcom_scm_desc desc = {
+		.svc = QCOM_SCM_SVC_BOOT,
+		.cmd = QCOM_SCM_BOOT_SDI_CONFIG,
+		.args[0] = 1, /* Disable watchdog debug */
+		.args[1] = 0, /* Disable SDI */
+		.arginfo = QCOM_SCM_ARGS(2),
+		.owner = ARM_SMCCC_OWNER_SIP,
+	};
+	struct qcom_scm_res res;
+
+	ret = qcom_scm_clk_enable();
+	if (ret)
+		return ret;
+	ret = qcom_scm_call(__scm->dev, &desc, &res);
+
+	qcom_scm_clk_disable();
+
+	return ret ? : res.result[0];
+}
+
+ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
+ {
+ 	struct qcom_scm_desc desc = {
+@@ -1411,6 +1434,13 @@ static int qcom_scm_probe(struct platfor
+ 
+ 	__get_convention();
+ 
+
+	/*
+	 * Disable SDI if indicated by DT that it is enabled by default.
+	 */
+	if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled"))
+		qcom_scm_disable_sdi();
+
+ 	/*
+ 	 * If requested enable "download mode", from this point on warmboot
+ 	 * will cause the boot stages to enter download mode, unless
+--- a/drivers/firmware/qcom_scm.h
+++ b/drivers/firmware/qcom_scm.h
+@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
+ #define QCOM_SCM_SVC_BOOT		0x01
+ #define QCOM_SCM_BOOT_SET_ADDR		0x01
+ #define QCOM_SCM_BOOT_TERMINATE_PC	0x02
+#define QCOM_SCM_BOOT_SDI_CONFIG	0x09
+ #define QCOM_SCM_BOOT_SET_DLOAD_MODE	0x10
+ #define QCOM_SCM_BOOT_SET_ADDR_MC	0x11
+ #define QCOM_SCM_BOOT_SET_REMOTE_STATE	0x0a
--- a/target/linux/ipq40xx/patches-6.1/100-ARM-dts-qcom-ipq4019-add-label-to-SCM.patch
+++ b/target/linux/ipq40xx/patches-6.1/100-ARM-dts-qcom-ipq4019-add-label-to-SCM.patch
@ -0,0 +1,24 @@
+From ea9fba16d972becc84cd2a82d25030975dc609a5 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 30 Sep 2023 13:09:27 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add label to SCM
+
+Some IPQ4019 boards require SDI to be disabled by adding a property to the
+SCM node, so lets make that easy by adding a label to the SCM node.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -155,7 +155,7 @@
+ 	};
+ 
+ 	firmware {
+-		scm {
+		scm: scm {
+ 			compatible = "qcom,scm-ipq4019", "qcom,scm";
+ 		};
+ 	};
--- a/target/linux/ipq40xx/patches-6.1/104-clk-fix-apss-cpu-overclocking.patch
+++ b/target/linux/ipq40xx/patches-6.1/104-clk-fix-apss-cpu-overclocking.patch
@ -0,0 +1,115 @@
+From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
+From: Christian Lamparter <chunkeey@googlemail.com>
+Date: Sun, 11 Mar 2018 14:41:31 +0100
+Subject: [PATCH 2/2] clk: fix apss cpu overclocking
+
+There's an interaction issue between the clk changes:"
+clk: qcom: ipq4019: Add the apss cpu pll divider clock node
+clk: qcom: ipq4019: remove fixed clocks and add pll clocks
+" and the cpufreq-dt.
+
+cpufreq-dt is now spamming the kernel-log with the following:
+
+[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
+for freq 761142857 (-34)
+
+This only happens on certain devices like the Compex WPJ428
+and AVM FritzBox!4040. However, other devices like the Asus
+RT-AC58U and Meraki MR33 work just fine.
+
+The issue stem from the fact that all higher CPU-Clocks
+are achieved by switching the clock-parent to the P_DDRPLLAPSS
+(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
+as part of the DDR calibration.
+
+For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
+at round 533 MHz (ddrpllsdcc = 190285714 Hz).
+
+whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
+clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
+
+This patch attempts to fix the issue by modifying
+clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
+to use a new qcom_find_freq_close() function, which returns the closest
+matching frequency, instead of the next higher. This way, the SoC in
+the FB4040 (with its max clock speed of 710.4 MHz) will no longer
+try to overclock to 761 MHz.
+
+Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
+Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
+ 1 file changed, 31 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
+@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
+ 	.reg = 0x2f020,
+ };
+ 
+
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
+					     unsigned long rate)
+{
+	const struct freq_tbl *last = NULL;
+
+	for ( ; f->freq; f++) {
+		if (rate == f->freq)
+			return f;
+
+		if (f->freq > rate) {
+			if (!last ||
+			   (f->freq - rate) < (rate - last->freq))
+				return f;
+			else
+				return last;
+		}
+		last = f;
+	}
+
+	return last;
+}
+
+ /*
+  * Round rate function for APSS CPU PLL Clock divider.
+  * It looks up the frequency table and returns the next higher frequency
+@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
+ 	struct clk_hw *p_hw;
+ 	const struct freq_tbl *f;
+ 
+-	f = qcom_find_freq(pll->freq_tbl, rate);
+	f = qcom_find_freq_close(pll->freq_tbl, rate);
+ 	if (!f)
+ 		return -EINVAL;
+ 
+@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c
+ 	const struct freq_tbl *f;
+ 	u32 mask;
+ 
+-	f = qcom_find_freq(pll->freq_tbl, rate);
+	f = qcom_find_freq_close(pll->freq_tbl, rate);
+ 	if (!f)
+ 		return -EINVAL;
+ 
+@@ -1304,6 +1327,7 @@ static unsigned long
+ clk_cpu_div_recalc_rate(struct clk_hw *hw,
+ 			unsigned long parent_rate)
+ {
+	const struct freq_tbl *f;
+ 	struct clk_fepll *pll = to_clk_fepll(hw);
+ 	u32 cdiv, pre_div;
+ 	u64 rate;
+@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
+ 	rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
+ 	do_div(rate, pre_div);
+ 
+-	return rate;
+	f = qcom_find_freq_close(pll->freq_tbl, rate);
+	if (!f)
+		return rate;
+
+	return f->freq;
+ };
+ 
+ static const struct clk_ops clk_regmap_cpu_div_ops = {
--- a/target/linux/ipq40xx/patches-6.1/301-arm-compressed-add-appended-DTB-section.patch
+++ b/target/linux/ipq40xx/patches-6.1/301-arm-compressed-add-appended-DTB-section.patch
@ -0,0 +1,48 @@
+From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 30 Oct 2020 13:36:31 +0100
+Subject: [PATCH] arm: compressed: add appended DTB section
+
+This adds a appended_dtb section to the ARM decompressor
+linker script.
+
+This allows using the existing ARM zImage appended DTB support for
+appending a DTB to the raw ELF kernel.
+
+Its size is set to 1MB max to match the zImage appended DTB size limit.
+
+To use it to pass the DTB to the kernel, objcopy is used:
+
+objcopy --set-section-flags=.appended_dtb=alloc,contents \
+	--update-section=.appended_dtb=<target>.dtb vmlinux
+
+This is based off the following patch:
+https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
+@@ -103,6 +103,13 @@ SECTIONS
+ 
+   _edata = .;
+ 
+  .appended_dtb : {
+    /* leave space for appended DTB */
+    . += 0x100000;
+  }
+
+  _edata_dtb = .;
+
+   /*
+    * The image_end section appears after any additional loadable sections
+    * that the linker may decide to insert in the binary image.  Having
+@@ -140,4 +147,4 @@ SECTIONS
+ 
+   ARM_ASSERTS
+ }
+-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
--- a/target/linux/ipq40xx/patches-6.1/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch
+++ b/target/linux/ipq40xx/patches-6.1/302-arm-compressed-set-ipq40xx-watchdog-to-allow-boot.patch
@ -0,0 +1,66 @@
+From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
+From: John Thomson <git@johnthomson.fastmail.com.au>
+Date: Fri, 23 Oct 2020 19:42:36 +1000
+Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
+
+For IPQ40XX systems where the SoC watchdog is activated before linux,
+the watchdog timer may be too small for linux to finish uncompress,
+boot, and watchdog management start.
+If the watchdog is enabled, set the timeout for it to 30 seconds.
+The functionality and offsets were copied from:
+drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
+The watchdog memory address was taken from:
+arch/arm/boot/dts/qcom-ipq4019.dtsi
+
+This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
+RouterBoot bootloader.
+
+Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
+---
+ arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
+@@ -620,6 +620,41 @@ not_relocated:	mov	r0, #0
+ 		bic	r4, r4, #1
+ 		blne	cache_on
+ 
+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
+ * if it is enabled, so that there is time for kernel
+ * to decompress, boot, and take over the watchdog.
+ * data and functionality from drivers/watchdog/qcom-wdt.c
+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
+ */
+#ifdef CONFIG_ARCH_IPQ40XX
+watchdog_set:
+		/* offsets:
+		 * 0x04 reset	(=1 resets countdown)
+		 * 0x08 enable	(=0 disables)
+		 * 0x0c status	(=1 when SoC was reset by watchdog)
+		 * 0x10 bark	(=timeout warning in ticks)
+		 * 0x14 bite	(=timeout reset in ticks)
+		 * clock rate is 1<<15 hertz
+		 */
+		.equ watchdog, 0x0b017000	@Store watchdog base address
+		movw r0, #:lower16:watchdog
+		movt r0, #:upper16:watchdog
+		ldr r1, [r0, #0x08]	@Get enabled?
+		cmp r1, #1		@If not enabled, do not change
+		bne watchdog_finished
+		mov r1, #0
+		str r1, [r0, #0x08]	@Disable the watchdog
+		mov r1, #1
+		str r1, [r0, #0x04]	@Pet the watchdog
+		mov r1, #30		@30 seconds timeout
+		lsl r1, r1, #15		@converted to ticks
+		str r1, [r0, #0x10]	@Set the bark timeout
+		str r1, [r0, #0x14]	@Set the bite timeout
+		mov r1, #1
+		str r1, [r0, #0x08]	@Enable the watchdog
+watchdog_finished:
+#endif /* CONFIG_ARCH_IPQ40XX */
+
+ /*
+  * The C runtime environment should now be setup sufficiently.
+  * Set up some pointers, and start decompressing.
--- a/target/linux/ipq40xx/patches-6.1/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch
+++ b/target/linux/ipq40xx/patches-6.1/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch
@ -0,0 +1,24 @@
+From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 14 Dec 2020 13:35:35 +0100
+Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
+
+When using sdhci_msm_set_clock clock setting will fail, so lets
+use the generic sdhci_set_clock.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ drivers/mmc/host/sdhci-msm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
+@@ -2451,7 +2451,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
+ 
+ static const struct sdhci_ops sdhci_msm_ops = {
+ 	.reset = sdhci_msm_reset,
+-	.set_clock = sdhci_msm_set_clock,
+	.set_clock = sdhci_set_clock,
+ 	.get_min_clock = sdhci_msm_get_min_clock,
+ 	.get_max_clock = sdhci_msm_get_max_clock,
+ 	.set_bus_width = sdhci_set_bus_width,
--- a/target/linux/ipq40xx/patches-6.1/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch
+++ b/target/linux/ipq40xx/patches-6.1/401-mmc-sdhci-msm-comment-unused-sdhci_msm_set_clock.patch
@ -0,0 +1,108 @@
+From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 9 May 2023 01:57:17 +0200
+Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
+
+comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
+current problem, we are forced to use sdhci_set_clock.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
+ 1 file changed, 43 insertions(+), 43 deletions(-)
+
+--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
+@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl
+ 	return SDHCI_MSM_MIN_CLOCK;
+ }
+ 
+-/*
+- * __sdhci_msm_set_clock - sdhci_msm clock control.
+- *
+- * Description:
+- * MSM controller does not use internal divider and
+- * instead directly control the GCC clock as per
+- * HW recommendation.
+- **/
+-static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+-{
+-	u16 clk;
+-
+-	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+-
+-	if (clock == 0)
+-		return;
+-
+-	/*
+-	 * MSM controller do not use clock divider.
+-	 * Thus read SDHCI_CLOCK_CONTROL and only enable
+-	 * clock with no divider value programmed.
+-	 */
+-	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+-	sdhci_enable_clk(host, clk);
+-}
+-
+-/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
+-static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+-{
+-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+-	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+-
+-	if (!clock) {
+-		host->mmc->actual_clock = msm_host->clk_rate = 0;
+-		goto out;
+-	}
+-
+-	sdhci_msm_hc_select_mode(host);
+-
+-	msm_set_clock_rate_for_bus_mode(host, clock);
+-out:
+-	__sdhci_msm_set_clock(host, clock);
+-}
+// /*
+//  * __sdhci_msm_set_clock - sdhci_msm clock control.
+//  *
+//  * Description:
+//  * MSM controller does not use internal divider and
+//  * instead directly control the GCC clock as per
+//  * HW recommendation.
+//  **/
+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+// {
+// 	u16 clk;
+
+// 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+// 	if (clock == 0)
+// 		return;
+
+// 	/*
+// 	 * MSM controller do not use clock divider.
+// 	 * Thus read SDHCI_CLOCK_CONTROL and only enable
+// 	 * clock with no divider value programmed.
+// 	 */
+// 	clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+// 	sdhci_enable_clk(host, clk);
+// }
+
+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
+// {
+// 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+// 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
+
+// 	if (!clock) {
+// 		host->mmc->actual_clock = msm_host->clk_rate = 0;
+// 		goto out;
+// 	}
+
+// 	sdhci_msm_hc_select_mode(host);
+
+// 	msm_set_clock_rate_for_bus_mode(host, clock);
+// out:
+// 	__sdhci_msm_set_clock(host, clock);
+// }
+ 
+ /*****************************************************************************\
+  *                                                                           *
--- a/target/linux/ipq40xx/patches-6.1/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch
+++ b/target/linux/ipq40xx/patches-6.1/422-firmware-qcom-scm-fix-SCM-cold-boot-address.patch
@ -0,0 +1,138 @@
+From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
+From: Brian Norris <computersforpeace@gmail.com>
+Date: Fri, 28 Jul 2023 12:06:23 +0200
+Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
+
+This effectively reverts upstream Linux commit 13e77747800e ("firmware:
+qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
+firmwares don't support the atomic variant.
+
+This fixes SMP support for Google WiFi.
+
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+---
+ drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
+ drivers/firmware/qcom_scm.c        | 11 ++++++
+ 2 files changed, 63 insertions(+), 10 deletions(-)
+
+--- a/drivers/firmware/qcom_scm-legacy.c
+++ b/drivers/firmware/qcom_scm-legacy.c
+@@ -13,6 +13,9 @@
+ #include <linux/arm-smccc.h>
+ #include <linux/dma-mapping.h>
+ 
+#include <asm/cacheflush.h>
+#include <asm/outercache.h>
+
+ #include "qcom_scm.h"
+ 
+ static DEFINE_MUTEX(qcom_scm_lock);
+@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
+ 	} while (res->a0 == QCOM_SCM_INTERRUPTED);
+ }
+ 
+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
+{
+	u32 cacheline_size, ctr;
+
+	asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
+	cacheline_size = 4 << ((ctr >> 16) & 0xf);
+
+	start = round_down(start, cacheline_size);
+	end = round_up(end, cacheline_size);
+	outer_inv_range(start, end);
+	while (start < end) {
+		asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
+		     : "memory");
+		start += cacheline_size;
+	}
+	dsb();
+	isb();
+}
+
+ /**
+  * scm_legacy_call() - Sends a command to the SCM and waits for the command to
+  * finish processing.
+@@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
+ 
+ 	rsp = scm_legacy_command_to_response(cmd);
+ 
+-	cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
+-	if (dma_mapping_error(dev, cmd_phys)) {
+-		kfree(cmd);
+-		return -ENOMEM;
+	if (dev) {
+		cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
+		if (dma_mapping_error(dev, cmd_phys)) {
+			kfree(cmd);
+			return -ENOMEM;
+		}
+	} else {
+		cmd_phys = virt_to_phys(cmd);
+		__cpuc_flush_dcache_area(cmd, alloc_len);
+		outer_flush_range(cmd_phys, cmd_phys + alloc_len);
+ 	}
+ 
+ 	smc.args[0] = 1;
+@@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
+ 		goto out;
+ 
+ 	do {
+-		dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
+-					sizeof(*rsp), DMA_FROM_DEVICE);
+		if (dev) {
+			dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
+						cmd_len, sizeof(*rsp),
+						DMA_FROM_DEVICE);
+		} else {
+			unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
+					      cmd_len;
+			qcom_scm_inv_range(start, start + sizeof(*rsp));
+		}
+ 	} while (!rsp->is_complete);
+ 
+-	dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
+-				le32_to_cpu(rsp->buf_offset),
+-				resp_len, DMA_FROM_DEVICE);
+	if (dev) {
+		dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
+					le32_to_cpu(rsp->buf_offset),
+					resp_len, DMA_FROM_DEVICE);
+	} else {
+		unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
+				      le32_to_cpu(rsp->buf_offset);
+		qcom_scm_inv_range(start, start + resp_len);
+	}
+ 
+ 	if (res) {
+ 		res_buf = scm_legacy_get_response_buffer(rsp);
+@@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
+ 			res->result[i] = le32_to_cpu(res_buf[i]);
+ 	}
+ out:
+-	dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
+	if (dev)
+		dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
+ 	kfree(cmd);
+ 	return ret;
+ }
+--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
+@@ -312,6 +312,17 @@ static int qcom_scm_set_boot_addr(void *
+ 	desc.args[0] = flags;
+ 	desc.args[1] = virt_to_phys(entry);
+ 
+	/*
+	 * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
+	 * require ugly DMA invalidation support that was dropped upstream a
+	 * while ago. For more info, see:
+	 *
+	 *  [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
+	 *  https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
+	 */
+	if (of_machine_is_compatible("google,wifi"))
+		return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
+
+ 	return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
+ }
+ 
--- a/target/linux/ipq40xx/patches-6.1/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch
+++ b/target/linux/ipq40xx/patches-6.1/444-mtd-nand-rawnand-add-support-for-Toshiba-TC58NVG0S3H.patch
@ -0,0 +1,29 @@
+From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
+Date: Wed, 20 Apr 2022 12:08:38 +0200
+Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
+ NAND flash
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
+has 128 bytes OOB. This adds a static NAND ID entry to correct this.
+
+Tested on FRITZ!Box 7530 flashed with OpenWrt.
+
+Signed-off-by: Andreas Böhler <dev@aboehler.at>
+(changed id_len to 8, added comment about possible counterfeits)
+---
+--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
+@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
+ 	{"TC58NVG0S3E 1G 3.3V 8-bit",
+ 		{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
+ 		  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
+	{"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
+		{ .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
+		  SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
+ 	{"TC58NVG2S0F 4G 3.3V 8-bit",
+ 		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
+ 		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
--- a/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
+++ b/target/linux/ipq40xx/patches-6.1/700-net-ipqess-introduce-the-Qualcomm-IPQESS-driver.patch
--- a/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
+++ b/target/linux/ipq40xx/patches-6.1/701-net-dsa-add-out-of-band-tagging-protocol.patch
@ -0,0 +1,238 @@
+From a32e16b3c2fc1954ad6e09737439f60e5890278e Mon Sep 17 00:00:00 2001
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Date: Fri, 4 Nov 2022 18:41:49 +0100
+Subject: [PATCH] net: dsa: add out-of-band tagging protocol
+
+This tagging protocol is designed for the situation where the link
+between the MAC and the Switch is designed such that the Destination
+Port, which is usually embedded in some part of the Ethernet Header, is
+sent out-of-band, and isn't present at all in the Ethernet frame.
+
+This can happen when the MAC and Switch are tightly integrated on an
+SoC, as is the case with the Qualcomm IPQ4019 for example, where the DSA
+tag is inserted directly into the DMA descriptors. In that case,
+the MAC driver is responsible for sending the tag to the switch using
+the out-of-band medium. To do so, the MAC driver needs to have the
+information of the destination port for that skb.
+
+Add a new tagging protocol based on SKB extensions to convey the
+information about the destination port to the MAC driver
+
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+---
+ Documentation/networking/dsa/dsa.rst | 13 +++++++-
+ MAINTAINERS                          |  1 +
+ include/linux/dsa/oob.h              | 16 +++++++++
+ include/linux/skbuff.h               |  3 ++
+ include/net/dsa.h                    |  2 ++
+ net/core/skbuff.c                    | 10 ++++++
+ net/dsa/Kconfig                      |  9 +++++
+ net/dsa/Makefile                     |  1 +
+ net/dsa/tag_oob.c                    | 49 ++++++++++++++++++++++++++++
+ 9 files changed, 103 insertions(+), 1 deletion(-)
+ create mode 100644 include/linux/dsa/oob.h
+ create mode 100644 net/dsa/tag_oob.c
+
+--- a/Documentation/networking/dsa/dsa.rst
+++ b/Documentation/networking/dsa/dsa.rst
+@@ -66,7 +66,8 @@ Switch tagging protocols
+ ------------------------
+ 
+ DSA supports many vendor-specific tagging protocols, one software-defined
+-tagging protocol, and a tag-less mode as well (``DSA_TAG_PROTO_NONE``).
+tagging protocol, a tag-less mode as well (``DSA_TAG_PROTO_NONE``) and an
+out-of-band tagging protocol (``DSA_TAG_PROTO_OOB``).
+ 
+ The exact format of the tag protocol is vendor specific, but in general, they
+ all contain something which:
+@@ -217,6 +218,16 @@ receive all frames regardless of the val
+ setting the ``promisc_on_master`` property of the ``struct dsa_device_ops``.
+ Note that this assumes a DSA-unaware master driver, which is the norm.
+ 
+Some SoCs have a tight integration between the conduit network interface and the
+embedded switch, such that the DSA tag isn't transmitted in the packet data,
+but through another media, using so-called out-of-band tagging. In that case,
+the host MAC driver is in charge of transmitting the tag to the switch.
+An example is the IPQ4019 SoC, that transmits the tag between the ipqess
+ethernet controller and the qca8k switch using the DMA descriptor. In that
+configuration, tag-chaining is permitted, but the OOB tag will always be the
+top-most switch in the tree. The tagger (``DSA_TAG_PROTO_OOB``) uses skb
+extensions to transmit the tag to and from the MAC driver.
+
+ Master network devices
+ ----------------------
+ 
+--- a/MAINTAINERS
+++ b/MAINTAINERS
+@@ -17081,6 +17081,7 @@ L:	netdev@vger.kernel.org
+ S:	Maintained
+ F:	Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
+ F:	drivers/net/ethernet/qualcomm/ipqess/
+F:	net/dsa/tag_oob.c
+ 
+ QUALCOMM ETHQOS ETHERNET DRIVER
+ M:	Vinod Koul <vkoul@kernel.org>
+--- /dev/null
+++ b/include/linux/dsa/oob.h
+@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only
+ * Copyright (C) 2022 Maxime Chevallier <maxime.chevallier@bootlin.com>
+ */
+
+#ifndef _NET_DSA_OOB_H
+#define _NET_DSA_OOB_H
+
+#include <linux/skbuff.h>
+
+struct dsa_oob_tag_info {
+	u16 port;
+};
+
+int dsa_oob_tag_push(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
+int dsa_oob_tag_pop(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
+#endif
+--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
+@@ -4588,6 +4588,9 @@ enum skb_ext_id {
+ #if IS_ENABLED(CONFIG_MCTP_FLOWS)
+ 	SKB_EXT_MCTP,
+ #endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
+	SKB_EXT_DSA_OOB,
+#endif
+ 	SKB_EXT_NUM, /* must be last */
+ };
+ 
+--- a/include/net/dsa.h
+++ b/include/net/dsa.h
+@@ -55,6 +55,7 @@ struct phylink_link_state;
+ #define DSA_TAG_PROTO_RTL8_4T_VALUE		25
+ #define DSA_TAG_PROTO_RZN1_A5PSW_VALUE		26
+ #define DSA_TAG_PROTO_LAN937X_VALUE		27
+#define DSA_TAG_PROTO_OOB_VALUE			28
+ 
+ enum dsa_tag_protocol {
+ 	DSA_TAG_PROTO_NONE		= DSA_TAG_PROTO_NONE_VALUE,
+@@ -85,6 +86,7 @@ enum dsa_tag_protocol {
+ 	DSA_TAG_PROTO_RTL8_4T		= DSA_TAG_PROTO_RTL8_4T_VALUE,
+ 	DSA_TAG_PROTO_RZN1_A5PSW	= DSA_TAG_PROTO_RZN1_A5PSW_VALUE,
+ 	DSA_TAG_PROTO_LAN937X		= DSA_TAG_PROTO_LAN937X_VALUE,
+	DSA_TAG_PROTO_OOB		= DSA_TAG_PROTO_OOB_VALUE,
+ };
+ 
+ struct dsa_switch;
+--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
+@@ -62,8 +62,12 @@
+ #include <linux/mpls.h>
+ #include <linux/kcov.h>
+ #include <linux/if.h>
+#ifdef CONFIG_NET_DSA_TAG_OOB
+#include <linux/dsa/oob.h>
+#endif
+ 
+ #include <net/protocol.h>
+#include <net/dsa.h>
+ #include <net/dst.h>
+ #include <net/sock.h>
+ #include <net/checksum.h>
+@@ -4517,6 +4521,9 @@ static const u8 skb_ext_type_len[] = {
+ #if IS_ENABLED(CONFIG_MCTP_FLOWS)
+ 	[SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
+ #endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
+	[SKB_EXT_DSA_OOB] = SKB_EXT_CHUNKSIZEOF(struct dsa_oob_tag_info),
+#endif
+ };
+ 
+ static __always_inline unsigned int skb_ext_total_length(void)
+@@ -4537,6 +4544,9 @@ static __always_inline unsigned int skb_
+ #if IS_ENABLED(CONFIG_MCTP_FLOWS)
+ 		skb_ext_type_len[SKB_EXT_MCTP] +
+ #endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
+		skb_ext_type_len[SKB_EXT_DSA_OOB] +
+#endif
+ 		0;
+ }
+ 
+--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
+@@ -113,6 +113,15 @@ config NET_DSA_TAG_OCELOT_8021Q
+ 	  this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
+ 	  use with tc-flower.
+ 
+config NET_DSA_TAG_OOB
+	select SKB_EXTENSIONS
+	tristate "Tag driver for Out-of-band tagging drivers"
+	help
+	  Say Y or M if you want to enable support for pairs of embedded
+	  switches and host MAC drivers which perform demultiplexing and
+	  packet steering to ports using out of band metadata processed
+	  by the DSA master, rather than tags present in the packets.
+
+ config NET_DSA_TAG_QCA
+ 	tristate "Tag driver for Qualcomm Atheros QCA8K switches"
+ 	help
+--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
+@@ -22,6 +22,7 @@ obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag
+ obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+ obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
+ obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
+obj-$(CONFIG_NET_DSA_TAG_OOB) += tag_oob.o
+ obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
+ obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
+ obj-$(CONFIG_NET_DSA_TAG_RTL8_4) += tag_rtl8_4.o
+--- /dev/null
+++ b/net/dsa/tag_oob.c
+@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/* Copyright (c) 2022, Maxime Chevallier <maxime.chevallier@bootlin.com> */
+
+#include <linux/bitfield.h>
+#include <linux/dsa/oob.h>
+#include <linux/skbuff.h>
+
+#include "dsa_priv.h"
+
+static struct sk_buff *oob_tag_xmit(struct sk_buff *skb,
+				    struct net_device *dev)
+{
+	struct dsa_oob_tag_info *tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
+	struct dsa_port *dp = dsa_slave_to_port(dev);
+
+	tag_info->port = dp->index;
+
+	return skb;
+}
+
+static struct sk_buff *oob_tag_rcv(struct sk_buff *skb,
+				   struct net_device *dev)
+{
+	struct dsa_oob_tag_info *tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
+
+	if (!tag_info)
+		return NULL;
+
+	skb->dev = dsa_master_find_slave(dev, 0, tag_info->port);
+	if (!skb->dev)
+		return NULL;
+
+	return skb;
+}
+
+static const struct dsa_device_ops oob_tag_dsa_ops = {
+	.name	= "oob",
+	.proto	= DSA_TAG_PROTO_OOB,
+	.xmit	= oob_tag_xmit,
+	.rcv	= oob_tag_rcv,
+};
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("DSA tag driver for out-of-band tagging");
+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_OOB);
+
+module_dsa_tag_driver(oob_tag_dsa_ops);
--- a/target/linux/ipq40xx/patches-6.1/702-net-ipqess-Add-out-of-band-DSA-tagging-support.patch
+++ b/target/linux/ipq40xx/patches-6.1/702-net-ipqess-Add-out-of-band-DSA-tagging-support.patch
@ -0,0 +1,173 @@
+From 4975e2b3f1d37bba04f262784cef0d5b7e0a30a4 Mon Sep 17 00:00:00 2001
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Date: Fri, 4 Nov 2022 18:41:50 +0100
+Subject: [PATCH] net: ipqess: Add out-of-band DSA tagging support
+
+On the IPQ4019, there's an 5 ports switch connected to the CPU through
+the IPQESS Ethernet controller. The way the DSA tag is sent-out to that
+switch is through the DMA descriptor, due to how tightly it is
+integrated with the switch.
+
+We use the out-of-band tagging protocol by getting the source
+port from the descriptor, push it into the skb extensions, and have the
+tagger pull it to infer the destination netdev. The reverse process is
+done on the TX side, where the driver pulls the tag from the skb and
+builds the descriptor accordingly.
+
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+---
+ drivers/net/ethernet/qualcomm/Kconfig         |  1 +
+ drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 64 ++++++++++++++++++-
+ drivers/net/ethernet/qualcomm/ipqess/ipqess.h |  4 ++
+ 3 files changed, 68 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
+@@ -64,6 +64,7 @@ config QCOM_IPQ4019_ESS_EDMA
+ 	tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
+ 	depends on (OF && ARCH_QCOM) || COMPILE_TEST
+ 	select PHYLINK
+	select NET_DSA_TAG_OOB
+ 	help
+ 	  This driver supports the Qualcomm Atheros IPQ40xx built-in
+ 	  ESS EDMA ethernet controller.
+--- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+@@ -9,6 +9,7 @@
+ 
+ #include <linux/bitfield.h>
+ #include <linux/clk.h>
+#include <linux/dsa/oob.h>
+ #include <linux/if_vlan.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+@@ -22,6 +23,7 @@
+ #include <linux/skbuff.h>
+ #include <linux/vmalloc.h>
+ #include <net/checksum.h>
+#include <net/dsa.h>
+ #include <net/ip6_checksum.h>
+ 
+ #include "ipqess.h"
+@@ -327,6 +329,7 @@ static int ipqess_rx_poll(struct ipqess_
+ 	tail &= IPQESS_RFD_CONS_IDX_MASK;
+ 
+ 	while (done < budget) {
+		struct dsa_oob_tag_info *tag_info;
+ 		struct ipqess_rx_desc *rd;
+ 		struct sk_buff *skb;
+ 
+@@ -406,6 +409,12 @@ static int ipqess_rx_poll(struct ipqess_
+ 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
+ 					       le16_to_cpu(rd->rrd4));
+ 
+		if (likely(rx_ring->ess->dsa_ports)) {
+			tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
+			tag_info->port = FIELD_GET(IPQESS_RRD_PORT_ID_MASK,
+						   le16_to_cpu(rd->rrd1));
+		}
+
+ 		napi_gro_receive(&rx_ring->napi_rx, skb);
+ 
+ 		rx_ring->ess->stats.rx_packets++;
+@@ -706,6 +715,23 @@ static void ipqess_rollback_tx(struct ip
+ 	tx_ring->head = start_index;
+ }
+ 
+static void ipqess_process_dsa_tag_sh(struct ipqess *ess, struct sk_buff *skb,
+				      u32 *word3)
+{
+	struct dsa_oob_tag_info *tag_info;
+
+	if (unlikely(!ess->dsa_ports))
+		return;
+
+	tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
+	if (!tag_info)
+		return;
+
+	*word3 |= tag_info->port << IPQESS_TPD_PORT_BITMAP_SHIFT;
+	*word3 |= BIT(IPQESS_TPD_FROM_CPU_SHIFT);
+	*word3 |= 0x3e << IPQESS_TPD_PORT_BITMAP_SHIFT;
+}
+
+ static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
+ 				  struct sk_buff *skb)
+ {
+@@ -716,6 +742,8 @@ static int ipqess_tx_map_and_fill(struct
+ 	u16 len;
+ 	int i;
+ 
+	ipqess_process_dsa_tag_sh(tx_ring->ess, skb, &word3);
+
+ 	if (skb_is_gso(skb)) {
+ 		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
+ 			lso_word1 |= IPQESS_TPD_IPV4_EN;
+@@ -917,6 +945,33 @@ static const struct net_device_ops ipqes
+ 	.ndo_tx_timeout		= ipqess_tx_timeout,
+ };
+ 
+static int ipqess_netdevice_event(struct notifier_block *nb,
+				  unsigned long event, void *ptr)
+{
+	struct ipqess *ess = container_of(nb, struct ipqess, netdev_notifier);
+	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
+	struct netdev_notifier_changeupper_info *info;
+
+	if (dev != ess->netdev)
+		return NOTIFY_DONE;
+
+	switch (event) {
+	case NETDEV_CHANGEUPPER:
+		info = ptr;
+
+		if (!dsa_slave_dev_check(info->upper_dev))
+			return NOTIFY_DONE;
+
+		if (info->linking)
+			ess->dsa_ports++;
+		else
+			ess->dsa_ports--;
+
+		return NOTIFY_DONE;
+	}
+	return NOTIFY_OK;
+}
+
+ static void ipqess_hw_stop(struct ipqess *ess)
+ {
+ 	int i;
+@@ -1184,12 +1239,19 @@ static int ipqess_axi_probe(struct platf
+ 		netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
+ 	}
+ 
+-	err = register_netdev(netdev);
+	ess->netdev_notifier.notifier_call = ipqess_netdevice_event;
+	err = register_netdevice_notifier(&ess->netdev_notifier);
+ 	if (err)
+ 		goto err_hw_stop;
+ 
+	err = register_netdev(netdev);
+	if (err)
+		goto err_notifier_unregister;
+
+ 	return 0;
+ 
+err_notifier_unregister:
+	unregister_netdevice_notifier(&ess->netdev_notifier);
+ err_hw_stop:
+ 	ipqess_hw_stop(ess);
+ 
+--- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
+@@ -171,6 +171,10 @@ struct ipqess {
+ 	struct platform_device *pdev;
+ 	struct phylink *phylink;
+ 	struct phylink_config phylink_config;
+
+	struct notifier_block netdev_notifier;
+	int dsa_ports;
+
+ 	struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
+ 
+ 	struct ipqess_statistics ipqess_stats;
--- a/target/linux/ipq40xx/patches-6.1/703-net-qualcomm-ipqess-release-IRQ-s-on-network-device-.patch
+++ b/target/linux/ipq40xx/patches-6.1/703-net-qualcomm-ipqess-release-IRQ-s-on-network-device-.patch
@ -0,0 +1,75 @@
+From 5f15f7f170c76220dfd36cb9037d7848d1fc4aaf Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 15 Aug 2023 14:30:50 +0200
+Subject: [PATCH] net: qualcomm: ipqess: release IRQ-s on network device stop
+
+Currently, IPQESS driver is obtaining the IRQ-s during ndo_open, but they
+are never freed as they are device managed.
+
+However, it is not enough for them to be released when device is removed
+as the same network device can be stopped and started multiple times which
+on the second start would lead to IRQ request to fail with -EBUSY as they
+have already been requested before and are not of the shared type with:
+[   34.480769] ipqess-edma c080000.ethernet eth0: Link is Down
+[   34.488070] ipqess-edma c080000.ethernet eth0: ipqess_open
+[   34.488131] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
+[   34.494527] ipqess-edma c080000.ethernet eth0: ipqess_open
+[   34.502892] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
+[   34.508137] qca8k-ipq4019 c000000.switch lan1: failed to open master eth0
+[   34.518966] br-lan: port 1(lan1) entered blocking state
+[   34.525165] br-lan: port 1(lan1) entered disabled state
+[   34.530633] device lan1 entered promiscuous mode
+[   34.548598] ipqess-edma c080000.ethernet eth0: ipqess_open
+[   34.548660] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
+[   34.553111] qca8k-ipq4019 c000000.switch lan2: failed to open master eth0
+[   34.563841] br-lan: port 2(lan2) entered blocking state
+[   34.570083] br-lan: port 2(lan2) entered disabled state
+[   34.575530] device lan2 entered promiscuous mode
+[   34.587067] ipqess-edma c080000.ethernet eth0: ipqess_open
+[   34.587132] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
+[   34.591579] qca8k-ipq4019 c000000.switch lan3: failed to open master eth0
+[   34.602451] br-lan: port 3(lan3) entered blocking state
+[   34.608496] br-lan: port 3(lan3) entered disabled state
+[   34.614084] device lan3 entered promiscuous mode
+[   34.626405] ipqess-edma c080000.ethernet eth0: ipqess_open
+[   34.626468] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
+[   34.630871] qca8k-ipq4019 c000000.switch lan4: failed to open master eth0
+[   34.641689] br-lan: port 4(lan4) entered blocking state
+[   34.647834] br-lan: port 4(lan4) entered disabled state
+[   34.653455] device lan4 entered promiscuous mode
+[   34.667282] ipqess-edma c080000.ethernet eth0: ipqess_open
+[   34.667364] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
+[   34.671830] qca8k-ipq4019 c000000.switch wan: failed to open master eth0
+
+So, lets free the IRQ-s on ndo_stop after stopping NAPI and HW IRQ-s.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+@@ -636,9 +636,22 @@ static int ipqess_stop(struct net_device
+ 	netif_tx_stop_all_queues(netdev);
+ 	phylink_stop(ess->phylink);
+ 	ipqess_irq_disable(ess);
+
+ 	for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
+		int qid;
+
+ 		napi_disable(&ess->tx_ring[i].napi_tx);
+ 		napi_disable(&ess->rx_ring[i].napi_rx);
+
+		qid = ess->tx_ring[i].idx;
+		devm_free_irq(&netdev->dev,
+			      ess->tx_irq[qid],
+			      &ess->tx_ring[i]);
+
+		qid = ess->rx_ring[i].idx;
+		devm_free_irq(&netdev->dev,
+			      ess->rx_irq[qid],
+			      &ess->rx_ring[i]);
+ 	}
+ 
+ 	return 0;
--- a/target/linux/ipq40xx/patches-6.1/704-net-qualcomm-ipqess-enable-threaded-NAPI-by-default.patch
+++ b/target/linux/ipq40xx/patches-6.1/704-net-qualcomm-ipqess-enable-threaded-NAPI-by-default.patch
@ -0,0 +1,49 @@
+From 9fa4a57a65e270e4d579cace4de5c438f46c7d12 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 15 Aug 2023 14:38:44 +0200
+Subject: [PATCH] net: qualcomm: ipqess: enable threaded NAPI by default
+
+Threaded NAPI provides a nice performance boost, so lets enable it by
+default.
+
+We do however need to move the __napi_schedule() after HW IRQ has been
+cleared in order to avoid concurency issues.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+@@ -530,9 +530,9 @@ static irqreturn_t ipqess_interrupt_tx(i
+ 	struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
+ 
+ 	if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
+-		__napi_schedule(&tx_ring->napi_tx);
+ 		ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
+ 			   0x0);
+		__napi_schedule(&tx_ring->napi_tx);
+ 	}
+ 
+ 	return IRQ_HANDLED;
+@@ -543,9 +543,9 @@ static irqreturn_t ipqess_interrupt_rx(i
+ 	struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
+ 
+ 	if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
+-		__napi_schedule(&rx_ring->napi_rx);
+ 		ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
+ 			   0x0);
+		__napi_schedule(&rx_ring->napi_rx);
+ 	}
+ 
+ 	return IRQ_HANDLED;
+@@ -1261,6 +1261,8 @@ static int ipqess_axi_probe(struct platf
+ 	if (err)
+ 		goto err_notifier_unregister;
+ 
+	dev_set_threaded(netdev, true);
+
+ 	return 0;
+ 
+ err_notifier_unregister:
--- a/target/linux/ipq40xx/patches-6.1/705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch
+++ b/target/linux/ipq40xx/patches-6.1/705-ARM-dts-qcom-ipq4019-Add-description-for-the-IPQESS-.patch
@ -0,0 +1,78 @@
+From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Date: Fri, 4 Nov 2022 18:41:51 +0100
+Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
+ Ethernet controller
+
+The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
+connected to the CPU through the internal IPQESS Ethernet controller.
+
+Add support for this internal interface, which is internally connected to a
+modified version of the QCA8K Ethernet switch.
+
+This Ethernet controller only support a specific internal interface mode
+for connection to the switch.
+
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -594,6 +594,54 @@
+ 			status = "disabled";
+ 		};
+ 
+		gmac: ethernet@c080000 {
+			compatible = "qcom,ipq4019-ess-edma";
+			reg = <0xc080000 0x8000>;
+			resets = <&gcc ESS_RESET>;
+			reset-names = "ess";
+			clocks = <&gcc GCC_ESS_CLK>;
+			clock-names = "ess";
+			interrupts = <GIC_SPI  65 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  66 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  67 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  68 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  69 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  70 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  71 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  72 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  73 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  74 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  75 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  76 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  77 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  78 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  79 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI  80 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
+			phy-mode = "internal";
+			status = "disabled";
+			fixed-link {
+				speed = <1000>;
+				full-duplex;
+				pause;
+			};
+		};
+
+ 		mdio: mdio@90000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
--- a/target/linux/ipq40xx/patches-6.1/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
+++ b/target/linux/ipq40xx/patches-6.1/706-net-dsa-qca8k-add-IPQ4019-built-in-switch-support.patch
--- a/target/linux/ipq40xx/patches-6.1/707-arm-dts-ipq4019-add-switch-node.patch
+++ b/target/linux/ipq40xx/patches-6.1/707-arm-dts-ipq4019-add-switch-node.patch
@ -0,0 +1,98 @@
+From 19c507c3fe4a6fc60317dcae2c55de452aecb7d5 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Mon, 1 Nov 2021 18:15:04 +0100
+Subject: [PATCH] arm: dts: ipq4019: add switch node
+
+Since the built-in IPQ40xx switch now has a driver, add the required node
+for it to work.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 76 +++++++++++++++++++++++++++++
+ 1 file changed, 76 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -594,6 +594,82 @@
+ 			status = "disabled";
+ 		};
+ 
+		switch: switch@c000000 {
+			compatible = "qca,ipq4019-qca8337n";
+			reg = <0xc000000 0x80000>, <0x98000 0x800>;
+			reg-names = "base", "psgmii_phy";
+			resets = <&gcc ESS_PSGMII_ARES>;
+			reset-names = "psgmii_rst";
+			mdio = <&mdio>;
+			psgmii-ethphy = <&psgmiiphy>;
+
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 { /* MAC0 */
+					reg = <0>;
+					label = "cpu";
+					ethernet = <&gmac>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+						pause;
+						asym-pause;
+					};
+				};
+
+				swport1: port@1 { /* MAC1 */
+					reg = <1>;
+					label = "lan1";
+					phy-handle = <&ethphy0>;
+					phy-mode = "psgmii";
+
+					status = "disabled";
+				};
+
+				swport2: port@2 { /* MAC2 */
+					reg = <2>;
+					label = "lan2";
+					phy-handle = <&ethphy1>;
+					phy-mode = "psgmii";
+
+					status = "disabled";
+				};
+
+				swport3: port@3 { /* MAC3 */
+					reg = <3>;
+					label = "lan3";
+					phy-handle = <&ethphy2>;
+					phy-mode = "psgmii";
+
+					status = "disabled";
+				};
+
+				swport4: port@4 { /* MAC4 */
+					reg = <4>;
+					label = "lan4";
+					phy-handle = <&ethphy3>;
+					phy-mode = "psgmii";
+
+					status = "disabled";
+				};
+
+				swport5: port@5 { /* MAC5 */
+					reg = <5>;
+					label = "wan";
+					phy-handle = <&ethphy4>;
+					phy-mode = "psgmii";
+
+					status = "disabled";
+				};
+			};
+		};
+
+ 		gmac: ethernet@c080000 {
+ 			compatible = "qcom,ipq4019-ess-edma";
+ 			reg = <0xc080000 0x8000>;
--- a/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
+++ b/target/linux/ipq40xx/patches-6.1/709-ARM-dts-qcom-ipq4019-add-QCA8075-PHY-Package-nodes.patch
@ -0,0 +1,67 @@
+From 5ac078c8fe18f3e8318547b8ed0ed782730c5039 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 10 Feb 2024 22:28:27 +0100
+Subject: [PATCH] ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
+
+Add QCA8075 PHY Package nodes. The PHY nodes that were previously
+defined never worked and actually never had a driver to correctly setup
+these PHY. Now that we have a correct driver, correctly add the PHY
+Package node and set the default value of 300mw for tx driver strength
+following specification of ipq4019 SoC.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/boot/dts//qcom-ipq4019.dtsi | 35 +++++++++++++++---------
+ 1 file changed, 22 insertions(+), 13 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -725,24 +725,33 @@
+ 			reg = <0x90000 0x64>;
+ 			status = "disabled";
+ 
+-			ethphy0: ethernet-phy@0 {
+			ethernet-phy-package@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "qcom,qca8075-package";
+ 				reg = <0>;
+-			};
+-
+-			ethphy1: ethernet-phy@1 {
+-				reg = <1>;
+-			};
+ 
+-			ethphy2: ethernet-phy@2 {
+-				reg = <2>;
+-			};
+-
+-			ethphy3: ethernet-phy@3 {
+-				reg = <3>;
+-			};
+				qcom,tx-drive-strength-milliwatt = <300>;
+ 
+-			ethphy4: ethernet-phy@4 {
+-				reg = <4>;
+				ethphy0: ethernet-phy@0 {
+					reg = <0>;
+				};
+
+				ethphy1: ethernet-phy@1 {
+					reg = <1>;
+				};
+
+				ethphy2: ethernet-phy@2 {
+					reg = <2>;
+				};
+
+				ethphy3: ethernet-phy@3 {
+					reg = <3>;
+				};
+
+				ethphy4: ethernet-phy@4 {
+					reg = <4>;
+				};
+ 			};
+ 		};
+ 
--- a/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
+++ b/target/linux/ipq40xx/patches-6.1/710-arm-dts-ipq4019-QCA807x-properties.patch
@ -0,0 +1,25 @@
+From 79b38b9f85da868ca59b66715c20aa55104b640b Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Fri, 2 Oct 2020 10:43:26 +0200
+Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
+
+This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
+
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+---
+ arch/arm/boot/dts/qcom-ipq4019.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
+@@ -752,6 +752,10 @@
+ 				ethphy4: ethernet-phy@4 {
+ 					reg = <4>;
+ 				};
+
+				psgmiiphy: psgmii-phy@5 {
+					reg = <5>;
+				};
+ 			};
+ 		};
+ 
--- a/target/linux/ipq40xx/patches-6.1/711-net-qualcomm-ipqess-fix-TX-timeout-errors.patch
+++ b/target/linux/ipq40xx/patches-6.1/711-net-qualcomm-ipqess-fix-TX-timeout-errors.patch
@ -0,0 +1,64 @@
+From d0055b03d9c8d48ad2b971821989b09ba95c39f8 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sun, 17 Sep 2023 20:18:31 +0200
+Subject: [PATCH] net: qualcomm: ipqess: fix TX timeout errors
+
+Currently logic to handle napi tx completion is flawed and on the long
+run on loaded condition cause TX timeout error with the queue not being
+able to handle any new packet.
+
+There are 2 main cause of this:
+- incrementing the packet done value wrongly
+- handling 2 times the tx_ring tail
+
+ipqess_tx_unmap_and_free may return 2 kind values:
+- 0: we are handling first and middle descriptor for the packet
+- packet len: we are at the last descriptor for the packet
+
+Done value was wrongly incremented also for first and intermediate
+descriptor for the packet resulting causing panic and TX timeouts by
+comunicating to the kernel an inconsistent value of packet handling not
+matching the expected ones.
+
+Tx_ring tail was handled twice for ipqess_tx_complete run resulting in
+again done value incremented wrongly and also problem with idx handling
+by actually skipping descriptor for some packets.
+
+Rework the loop logic to fix these 2 problem and also add some comments
+to make sure ipqess_tx_unmap_and_free ret value is better
+understandable.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
+@@ -453,13 +453,22 @@ static int ipqess_tx_complete(struct ipq
+ 	tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
+ 	tail &= IPQESS_TPD_CONS_IDX_MASK;
+ 
+-	do {
+	while ((tx_ring->tail != tail) && (done < budget)) {
+ 		ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
+ 					       &tx_ring->buf[tx_ring->tail]);
+-		tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
+		/* ipqess_tx_unmap_and_free may return 2 kind values:
+		 * - 0: we are handling first and middle descriptor for the packet
+		 * - packet len: we are at the last descriptor for the packet
+		 * Increment total bytes handled and packet done only if we are
+		 * handling the last descriptor for the packet.
+		 */
+		if (ret) {
+			total += ret;
+			done++;
+		}
+ 
+-		total += ret;
+-	} while ((++done < budget) && (tx_ring->tail != tail));
+		tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
+	};
+ 
+ 	ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
+ 		   tx_ring->tail);
--- a/target/linux/ipq40xx/patches-6.1/850-soc-add-qualcomm-syscon.patch
+++ b/target/linux/ipq40xx/patches-6.1/850-soc-add-qualcomm-syscon.patch
@ -0,0 +1,175 @@
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: SoC: add qualcomm syscon
+--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
+@@ -248,4 +248,11 @@ config QCOM_ICC_BWMON
+ 	  the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high
+ 	  memory throughput even with lower CPU frequencies.
+ 
+config QCOM_TCSR
+	tristate "QCOM Top Control and Status Registers"
+	depends on ARCH_QCOM
+	help
+	  Say y here to enable TCSR support.  The TCSR provides control
+	  functions for various peripherals.
+
+ endmenu
+--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
+@@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
+ obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
+ obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) +=	kryo-l2-accessors.o
+ obj-$(CONFIG_QCOM_ICC_BWMON)	+= icc-bwmon.o
+obj-$(CONFIG_QCOM_TCSR)		+= qcom_tcsr.o
+--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
+@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#define TCSR_USB_PORT_SEL	0xb0
+#define TCSR_USB_HSPHY_CONFIG	0xC
+
+#define TCSR_ESS_INTERFACE_SEL_OFFSET   0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK     0xf
+
+#define TCSR_WIFI0_GLB_CFG_OFFSET	0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET	0x4
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2	0x4
+
+static int tcsr_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	const struct device_node *node = pdev->dev.of_node;
+	void __iomem *base;
+	u32 val;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
+		dev_err(&pdev->dev, "setting usb port select = %d\n", val);
+		writel(val, base + TCSR_USB_PORT_SEL);
+	}
+
+	if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
+		dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
+		writel(val, base + TCSR_USB_HSPHY_CONFIG);
+	}
+
+	if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
+		u32 tmp = 0;
+		dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
+		tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+		tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
+		tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
+		writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+        }
+
+	if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
+		dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
+		writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
+		writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
+	}
+
+	if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
+		dev_info(&pdev->dev,
+			"setting wifi_noc_memtype_m0_m2 = %x\n", val);
+		writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
+	}
+
+	return 0;
+}
+
+static const struct of_device_id tcsr_dt_match[] = {
+	{ .compatible = "qcom,tcsr", },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
+
+static struct platform_driver tcsr_driver = {
+	.driver = {
+		.name		= "tcsr",
+		.owner		= THIS_MODULE,
+		.of_match_table	= tcsr_dt_match,
+	},
+	.probe = tcsr_probe,
+};
+
+module_platform_driver(tcsr_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
+--- /dev/null
+++ b/include/dt-bindings/soc/qcom,tcsr.h
+@@ -0,0 +1,48 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
+#define __DT_BINDINGS_QCOM_TCSR_H
+
+#define TCSR_USB_SELECT_USB3_P0		0x1
+#define TCSR_USB_SELECT_USB3_P1		0x2
+#define TCSR_USB_SELECT_USB3_DUAL	0x3
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_HOST_MODE	0x00E700E7
+#define TCSR_USB_HSPHY_DEVICE_MODE	0x00C700E7
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_PSGMII              0
+#define TCSR_ESS_PSGMII_RGMII5       1
+#define TCSR_ESS_PSGMII_RMII0        2
+#define TCSR_ESS_PSGMII_RMII1        4
+#define TCSR_ESS_PSGMII_RMII0_RMII1  6
+#define TCSR_ESS_PSGMII_RGMII4       9
+
+/*
+ * IPQ40xx WiFi Global Config
+ * Bit 30:AXID_EN
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
+ * Bit 24: Use locally generated socslv_wxi_bvalid
+ * 1:  use locally generate socslv_wxi_bvalid for performance.
+ * 0:  use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG		0x41000000
+
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2	0x02222222
+
+/* TCSR A/B REG */
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
+
+#endif
--- a/target/linux/ipq40xx/patches-6.1/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch
+++ b/target/linux/ipq40xx/patches-6.1/910-Revert-firmware-qcom_scm-Clear-download-bit-during-r.patch
@ -0,0 +1,27 @@
+From c668fd2c4d9ad4a510fd214a2da83bd9b67a2508 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sun, 13 Aug 2023 18:13:08 +0200
+Subject: [PATCH] Revert "firmware: qcom_scm: Clear download bit during reboot"
+
+This reverts commit a3ea89b5978dbcd0fa55f675c5a1e04611093709.
+
+It is breaking reboot on IPQ4019 boards, so revert until a proper fix
+is found.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/firmware/qcom_scm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
+@@ -1466,7 +1466,8 @@ static int qcom_scm_probe(struct platfor
+ static void qcom_scm_shutdown(struct platform_device *pdev)
+ {
+ 	/* Clean shutdown, disable download mode to allow normal restart */
+-	qcom_scm_set_download_mode(false);
+	if (download_mode)
+		qcom_scm_set_download_mode(false);
+ }
+ 
+ static const struct of_device_id qcom_scm_dt_match[] = {
--- a/target/linux/ipq40xx/patches-6.1/998-lantiq-atm-hacks.patch
+++ b/target/linux/ipq40xx/patches-6.1/998-lantiq-atm-hacks.patch
@ -0,0 +1,43 @@
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 3 Aug 2012 10:27:25 +0200
+Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+--- a/include/uapi/linux/atm.h
+++ b/include/uapi/linux/atm.h
+@@ -131,8 +131,14 @@
+ #define ATM_ABR		4
+ #define ATM_ANYCLASS	5		/* compatible with everything */
+ 
+#define ATM_VBR_NRT     ATM_VBR
+#define ATM_VBR_RT      6
+#define ATM_UBR_PLUS    7
+#define ATM_GFR         8
+
+ #define ATM_MAX_PCR	-1		/* maximum available PCR */
+ 
+
+ struct atm_trafprm {
+ 	unsigned char	traffic_class;	/* traffic class (ATM_UBR, ...) */
+ 	int		max_pcr;	/* maximum PCR in cells per second */
+@@ -155,6 +161,9 @@ struct atm_trafprm {
+ 	unsigned int adtf      :10;     /* ACR Decrease Time Factor (10-bit) */
+ 	unsigned int cdf       :3;      /* Cutoff Decrease Factor (3-bit) */
+         unsigned int spare     :9;      /* spare bits */ 
+	int		scr;		/* sustained rate in cells per second */
+	int		mbs;		/* maximum burst size (MBS) in cells */
+	int		cdv;		/* Cell delay variation */
+ };
+ 
+ struct atm_qos {
+--- a/net/atm/proc.c
+++ b/net/atm/proc.c
+@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
+ static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
+ {
+ 	static const char *const class_name[] = {
+-		"off", "UBR", "CBR", "VBR", "ABR"};
+		"off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
+ 	static const char *const aal_name[] = {
+ 		"---",	"1",	"2",	"3/4",	/*  0- 3 */
+ 		"???",	"5",	"???",	"???",	/*  4- 7 */
--- a/target/linux/ipq40xx/patches-6.1/999-atm-mpoa-intel-dsl-phy-support.patch
+++ b/target/linux/ipq40xx/patches-6.1/999-atm-mpoa-intel-dsl-phy-support.patch
@ -0,0 +1,137 @@
+From: Subhra Banerjee <subhrax.banerjee@intel.com>
+Date: Fri, 31 Aug 2018 12:01:19 +0530
+Subject: [PATCH] UGW_SW-29163: ATM oam support
+
+--- a/drivers/net/ppp/ppp_generic.c
+++ b/drivers/net/ppp/ppp_generic.c
+@@ -2953,6 +2953,22 @@ char *ppp_dev_name(struct ppp_channel *c
+ 	return name;
+ }
+ 
+/*
+ * Return the PPP device interface pointer
+ */
+struct net_device *ppp_device(struct ppp_channel *chan)
+{
+	struct channel *pch = chan->ppp;
+	struct net_device *dev = NULL;
+
+	if (pch) {
+		read_lock_bh(&pch->upl);
+		if (pch->ppp && pch->ppp->dev)
+			dev = pch->ppp->dev;
+		read_unlock_bh(&pch->upl);
+	}
+	return dev;
+}
+ 
+ /*
+  * Disconnect a channel from the generic layer.
+@@ -3599,6 +3615,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
+ EXPORT_SYMBOL(ppp_channel_index);
+ EXPORT_SYMBOL(ppp_unit_number);
+ EXPORT_SYMBOL(ppp_dev_name);
+EXPORT_SYMBOL(ppp_device);
+ EXPORT_SYMBOL(ppp_input);
+ EXPORT_SYMBOL(ppp_input_error);
+ EXPORT_SYMBOL(ppp_output_wakeup);
+--- a/include/linux/ppp_channel.h
+++ b/include/linux/ppp_channel.h
+@@ -76,6 +76,9 @@ extern int ppp_unit_number(struct ppp_ch
+ /* Get the device name associated with a channel, or NULL if none */
+ extern char *ppp_dev_name(struct ppp_channel *);
+ 
+/* Get the device pointer associated with a channel, or NULL if none */
+extern struct net_device *ppp_device(struct ppp_channel *);
+
+ /*
+  * SMP locking notes:
+  * The channel code must ensure that when it calls ppp_unregister_channel,
+--- a/net/atm/Kconfig
+++ b/net/atm/Kconfig
+@@ -56,6 +56,12 @@ config ATM_MPOA
+ 	  subnetwork boundaries. These shortcut connections bypass routers
+ 	  enhancing overall network performance.
+ 
+config ATM_MPOA_INTEL_DSL_PHY_SUPPORT
+	bool "Intel DSL Phy MPOA support"
+	depends on ATM && INET && ATM_MPOA!=n
+	help
+	  Add support for Intel DSL Phy ATM MPOA
+
+ config ATM_BR2684
+ 	tristate "RFC1483/2684 Bridged protocols"
+ 	depends on ATM && INET
+--- a/net/atm/br2684.c
+++ b/net/atm/br2684.c
+@@ -598,6 +598,11 @@ static int br2684_regvcc(struct atm_vcc
+ 	atmvcc->push = br2684_push;
+ 	atmvcc->pop = br2684_pop;
+ 	atmvcc->release_cb = br2684_release_cb;
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+	if (atm_hook_mpoa_setup) /* IPoA or EoA w/o FCS */
+		atm_hook_mpoa_setup(atmvcc, brdev->payload == p_routed ? 3 : 0,
+			brvcc->encaps == BR2684_ENCAPS_LLC ? 1 : 0, net_dev);
+#endif
+ 	atmvcc->owner = THIS_MODULE;
+ 
+ 	/* initialize netdev carrier state */
+--- a/net/atm/common.c
+++ b/net/atm/common.c
+@@ -137,6 +137,11 @@ static struct proto vcc_proto = {
+ 	.release_cb = vcc_release_cb,
+ };
+ 
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *) = NULL;
+EXPORT_SYMBOL(atm_hook_mpoa_setup);
+#endif
+
+ int vcc_create(struct net *net, struct socket *sock, int protocol, int family, int kern)
+ {
+ 	struct sock *sk;
+--- a/net/atm/common.h
+++ b/net/atm/common.h
+@@ -53,4 +53,6 @@ int svc_change_qos(struct atm_vcc *vcc,s
+ 
+ void atm_dev_release_vccs(struct atm_dev *dev);
+ 
+extern void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *);
+
+ #endif
+--- a/net/atm/mpc.c
+++ b/net/atm/mpc.c
+@@ -31,6 +31,7 @@
+ /* Modular too */
+ #include <linux/module.h>
+ 
+#include "common.h"
+ #include "lec.h"
+ #include "mpc.h"
+ #include "resources.h"
+@@ -645,6 +646,10 @@ static int atm_mpoa_vcc_attach(struct at
+ 	vcc->proto_data = mpc->dev;
+ 	vcc->push = mpc_push;
+ 
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+	if (atm_hook_mpoa_setup) /* IPoA, LLC */
+		atm_hook_mpoa_setup(vcc, 3, 1, mpc->dev);
+#endif
+ 	return 0;
+ }
+ 
+--- a/net/atm/pppoatm.c
+++ b/net/atm/pppoatm.c
+@@ -422,6 +422,12 @@ static int pppoatm_assign_vcc(struct atm
+ 	atmvcc->user_back = pvcc;
+ 	atmvcc->push = pppoatm_push;
+ 	atmvcc->pop = pppoatm_pop;
+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
+	if (atm_hook_mpoa_setup) /* PPPoA */
+		atm_hook_mpoa_setup(atmvcc, 2,
+			pvcc->encaps == e_llc ? 1 : 0,
+			ppp_device(&pvcc->chan));
+#endif
+ 	atmvcc->release_cb = pppoatm_release_cb;
+ 	__module_get(THIS_MODULE);
+ 	atmvcc->owner = THIS_MODULE;