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generic: 6.1: backport qca8k fixes for big endian and MDIO
Backport qca8k fixes for big endian system (to make them working again) and a patch fixing MDIO conflicts if other PHY are connected and mgmt eth is used to control the switch. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
parent
b0048b3146
commit
20d74c6811
@ -0,0 +1,61 @@
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From 5652d1741574eb89cc02576e50ee3e348bd6dd77 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
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Date: Wed, 4 Oct 2023 11:19:03 +0200
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Subject: [PATCH 1/2] net: dsa: qca8k: fix regmap bulk read/write methods on
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big endian systems
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Commit c766e077d927 ("net: dsa: qca8k: convert to regmap read/write
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API") introduced bulk read/write methods to qca8k's regmap.
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The regmap bulk read/write methods get the register address in a buffer
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passed as a void pointer parameter (the same buffer contains also the
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read/written values). The register address occupies only as many bytes
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as it requires at the beginning of this buffer. For example if the
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.reg_bits member in regmap_config is 16 (as is the case for this
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driver), the register address occupies only the first 2 bytes in this
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buffer, so it can be cast to u16.
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But the original commit implementing these bulk read/write methods cast
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the buffer to u32:
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u32 reg = *(u32 *)reg_buf & U16_MAX;
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taking the first 4 bytes. This works on little endian systems where the
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first 2 bytes of the buffer correspond to the low 16-bits, but it
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obviously cannot work on big endian systems.
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Fix this by casting the beginning of the buffer to u16 as
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u32 reg = *(u16 *)reg_buf;
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Fixes: c766e077d927 ("net: dsa: qca8k: convert to regmap read/write API")
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Signed-off-by: Marek Behún <kabel@kernel.org>
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Tested-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -504,8 +504,8 @@ qca8k_bulk_read(void *ctx, const void *r
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void *val_buf, size_t val_len)
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{
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int i, count = val_len / sizeof(u32), ret;
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- u32 reg = *(u32 *)reg_buf & U16_MAX;
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struct qca8k_priv *priv = ctx;
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+ u32 reg = *(u16 *)reg_buf;
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if (priv->mgmt_master &&
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!qca8k_read_eth(priv, reg, val_buf, val_len))
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@@ -526,8 +526,8 @@ qca8k_bulk_gather_write(void *ctx, const
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const void *val_buf, size_t val_len)
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{
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int i, count = val_len / sizeof(u32), ret;
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- u32 reg = *(u32 *)reg_buf & U16_MAX;
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struct qca8k_priv *priv = ctx;
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+ u32 reg = *(u16 *)reg_buf;
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u32 *val = (u32 *)val_buf;
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if (priv->mgmt_master &&
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@ -0,0 +1,106 @@
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From 526c8ee04bdbd4d8d19a583b1f3b06700229a815 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
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Date: Wed, 4 Oct 2023 11:19:04 +0200
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Subject: [PATCH 2/2] net: dsa: qca8k: fix potential MDIO bus conflict when
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accessing internal PHYs via management frames
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Besides the QCA8337 switch the Turris 1.x device has on it's MDIO bus
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also Micron ethernet PHY (dedicated to the WAN port).
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We've been experiencing a strange behavior of the WAN ethernet
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interface, wherein the WAN PHY started timing out the MDIO accesses, for
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example when the interface was brought down and then back up.
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Bisecting led to commit 2cd548566384 ("net: dsa: qca8k: add support for
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phy read/write with mgmt Ethernet"), which added support to access the
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QCA8337 switch's internal PHYs via management ethernet frames.
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Connecting the MDIO bus pins onto an oscilloscope, I was able to see
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that the MDIO bus was active whenever a request to read/write an
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internal PHY register was done via an management ethernet frame.
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My theory is that when the switch core always communicates with the
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internal PHYs via the MDIO bus, even when externally we request the
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access via ethernet. This MDIO bus is the same one via which the switch
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and internal PHYs are accessible to the board, and the board may have
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other devices connected on this bus. An ASCII illustration may give more
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insight:
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+---------+
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+----| |
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| | WAN PHY |
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| +--| |
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| | +---------+
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| |
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| | +----------------------------------+
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| | | QCA8337 |
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MDC | | | +-------+ |
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------o-+--|--------o------------o--| | |
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MDIO | | | | | PHY 1 |-|--to RJ45
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--------o--|---o----+---------o--+--| | |
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| | | | | +-------+ |
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| +-------------+ | o--| | |
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| | MDIO MDC | | | | PHY 2 |-|--to RJ45
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eth1 | | | o--+--| | |
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-----------|-|port0 | | | +-------+ |
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| | | | o--| | |
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| | switch core | | | | PHY 3 |-|--to RJ45
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| +-------------+ o--+--| | |
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| | | +-------+ |
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| | o--| ... | |
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+----------------------------------+
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When we send a request to read an internal PHY register via an ethernet
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management frame via eth1, the switch core receives the ethernet frame
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on port 0 and then communicates with the internal PHY via MDIO. At this
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time, other potential devices, such as the WAN PHY on Turris 1.x, cannot
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use the MDIO bus, since it may cause a bus conflict.
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Fix this issue by locking the MDIO bus even when we are accessing the
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PHY registers via ethernet management frames.
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Fixes: 2cd548566384 ("net: dsa: qca8k: add support for phy read/write with mgmt Ethernet")
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Signed-off-by: Marek Behún <kabel@kernel.org>
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Reviewed-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca/qca8k-8xxx.c | 11 +++++++++++
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1 file changed, 11 insertions(+)
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -665,6 +665,15 @@ qca8k_phy_eth_command(struct qca8k_priv
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goto err_read_skb;
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}
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+ /* It seems that accessing the switch's internal PHYs via management
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+ * packets still uses the MDIO bus within the switch internally, and
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+ * these accesses can conflict with external MDIO accesses to other
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+ * devices on the MDIO bus.
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+ * We therefore need to lock the MDIO bus onto which the switch is
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+ * connected.
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+ */
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+ mutex_lock(&priv->bus->mdio_lock);
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+
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/* Actually start the request:
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* 1. Send mdio master packet
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* 2. Busy Wait for mdio master command
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@@ -677,6 +686,7 @@ qca8k_phy_eth_command(struct qca8k_priv
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mgmt_master = priv->mgmt_master;
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if (!mgmt_master) {
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mutex_unlock(&mgmt_eth_data->mutex);
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+ mutex_unlock(&priv->bus->mdio_lock);
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ret = -EINVAL;
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goto err_mgmt_master;
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}
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@@ -764,6 +774,7 @@ exit:
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QCA8K_ETHERNET_TIMEOUT);
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mutex_unlock(&mgmt_eth_data->mutex);
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+ mutex_unlock(&priv->bus->mdio_lock);
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return ret;
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@ -20,7 +20,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -778,21 +778,6 @@ err_clear_skb:
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@@ -789,21 +789,6 @@ err_clear_skb:
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return ret;
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}
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@ -71,7 +71,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
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static void
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qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
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@@ -1829,6 +1830,10 @@ qca8k_setup(struct dsa_switch *ds)
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@@ -1840,6 +1841,10 @@ qca8k_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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@ -16,7 +16,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -1993,6 +1993,8 @@ static const struct dsa_switch_ops qca8k
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@@ -2004,6 +2004,8 @@ static const struct dsa_switch_ops qca8k
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.port_fdb_add = qca8k_port_fdb_add,
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.port_fdb_del = qca8k_port_fdb_del,
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.port_fdb_dump = qca8k_port_fdb_dump,
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@ -14,7 +14,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -1882,15 +1882,12 @@ qca8k_setup(struct dsa_switch *ds)
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@@ -1893,15 +1893,12 @@ qca8k_setup(struct dsa_switch *ds)
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}
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}
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@ -26,7 +26,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -1719,6 +1719,117 @@ qca8k_get_tag_protocol(struct dsa_switch
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@@ -1730,6 +1730,117 @@ qca8k_get_tag_protocol(struct dsa_switch
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return DSA_TAG_PROTO_QCA;
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}
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@ -144,7 +144,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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static void
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qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
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bool operational)
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@@ -2005,8 +2116,9 @@ static const struct dsa_switch_ops qca8k
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@@ -2016,8 +2127,9 @@ static const struct dsa_switch_ops qca8k
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.phylink_mac_link_down = qca8k_phylink_mac_link_down,
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.phylink_mac_link_up = qca8k_phylink_mac_link_up,
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.get_phy_flags = qca8k_get_phy_flags,
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@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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--- a/drivers/net/dsa/qca/qca8k-8xxx.c
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+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
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@@ -1991,6 +1991,12 @@ qca8k_setup(struct dsa_switch *ds)
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@@ -2002,6 +2002,12 @@ qca8k_setup(struct dsa_switch *ds)
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dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index);
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return ret;
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}
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@ -33,7 +33,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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}
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/* Forward all unknown frames to CPU port for Linux processing */
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@@ -2020,11 +2026,6 @@ qca8k_setup(struct dsa_switch *ds)
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@@ -2031,11 +2037,6 @@ qca8k_setup(struct dsa_switch *ds)
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if (ret)
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return ret;
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@ -45,7 +45,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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/* For port based vlans to work we need to set the
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* default egress vid
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*/
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@@ -2076,6 +2077,9 @@ qca8k_setup(struct dsa_switch *ds)
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@@ -2087,6 +2088,9 @@ qca8k_setup(struct dsa_switch *ds)
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/* Set max number of LAGs supported */
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ds->num_lag_ids = QCA8K_NUM_LAGS;
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