treewide: remove files for building 5.10 kernel

All targets are bumped to 5.15. Remove the old 5.10 patches, configs and files using: find target/linux -iname '*-5.10' -exec rm -r {} \; Further, remove the 5.10 include. Signed-off-by: Nick Hainke <vincent@systemli.org>
2024-12-21 06:33:41 +00:00 · 2023-05-04 21:13:33 +02:00 · 2023-05-04 21:13:33 +02:00 · 1d3e71bd97
commit 1d3e71bd97
parent 397ba0b54b
1545 changed files with 0 additions and 254276 deletions
--- a/include/kernel-5.10
+++ b/include/kernel-5.10
@ -1,2 +0,0 @@
 LINUX_VERSION-5.10 = .179
 LINUX_KERNEL_HASH-5.10.179 = 1bbd445c154b053eea46acc883be548a98179988a9ed3a0b81bddfbf30a37e29
--- a/target/linux/apm821xx/config-5.10
+++ b/target/linux/apm821xx/config-5.10
@ -1,244 +0,0 @@
 # CONFIG_40x is not set
 CONFIG_44x=y
 CONFIG_4xx=y
 CONFIG_4xx_SOC=y
 # CONFIG_ADVANCED_OPTIONS is not set
 CONFIG_APM821xx=y
 # CONFIG_APOLLO3G is not set
 # CONFIG_ARCHES is not set
 CONFIG_ARCH_32BIT_OFF_T=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_ARCH_MAY_HAVE_PC_FDC=y
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
 CONFIG_ARCH_MMAP_RND_BITS=11
 CONFIG_ARCH_MMAP_RND_BITS_MAX=17
 CONFIG_ARCH_MMAP_RND_BITS_MIN=11
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARCH_WEAK_RELEASE_ACQUIRE=y
 CONFIG_AUDIT_ARCH=y
 # CONFIG_BAMBOO is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_BLK_MQ_PCI=y
 CONFIG_BLUESTONE=y
 CONFIG_BOOKE=y
 CONFIG_BOOKE_WDT=y
 # CONFIG_CANYONLANDS is not set
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_CMDLINE="rootfstype=squashfs noinitrd"
 CONFIG_CMDLINE_FROM_BOOTLOADER=y
 CONFIG_COMMON_CLK=y
 CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CPU_BIG_ENDIAN=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
 CONFIG_CRYPTO_BLAKE2S=y
 CONFIG_CRYPTO_DEFLATE=y
 CONFIG_CRYPTO_DEV_PPC4XX=y
 CONFIG_CRYPTO_HW=y
 CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
 CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_LZO=y
 # CONFIG_CRYPTO_MD5_PPC is not set
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
 # CONFIG_CRYPTO_SHA1_PPC is not set
 CONFIG_DATA_SHIFT=12
 CONFIG_DMADEVICES=y
 CONFIG_DMA_DIRECT_REMAP=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
 CONFIG_DMA_REMAP=y
 CONFIG_DTC=y
 CONFIG_DW_DMAC=y
 CONFIG_DW_DMAC_CORE=y
 # CONFIG_E200 is not set
 CONFIG_EARLY_PRINTK=y
 # CONFIG_EBONY is not set
 CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_EDAC_SUPPORT=y
 # CONFIG_EIGER is not set
 CONFIG_EXTRA_TARGETS="uImage"
 CONFIG_FIXED_PHY=y
 CONFIG_FORCE_PCI=y
 # CONFIG_FSL_LBC is not set
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_GENERIC_CPU=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 CONFIG_GENERIC_ISA_DMA=y
 CONFIG_GENERIC_MSI_IRQ=y
 CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 # CONFIG_GEN_RTC is not set
 # CONFIG_GLACIER is not set
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_PPC4XX=y
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_IBM_IIC=y
 CONFIG_IBM_EMAC=y
 CONFIG_IBM_EMAC_EMAC4=y
 CONFIG_IBM_EMAC_POLL_WEIGHT=32
 CONFIG_IBM_EMAC_RGMII=y
 CONFIG_IBM_EMAC_RXB=128
 CONFIG_IBM_EMAC_RX_COPY_THRESHOLD=256
 CONFIG_IBM_EMAC_TAH=y
 CONFIG_IBM_EMAC_TXB=128
 # CONFIG_ICON is not set
 CONFIG_ILLEGAL_POINTER_VALUE=0
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_HIERARCHY=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
 CONFIG_ISA_DMA_API=y
 # CONFIG_JFFS2_FS is not set
 # CONFIG_KATMAI is not set
 CONFIG_KERNEL_START=0xc0000000
 CONFIG_LEDS_TRIGGER_MTD=y
 CONFIG_LEDS_TRIGGER_PATTERN=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOWMEM_SIZE=0x30000000
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
 # CONFIG_MATH_EMULATION is not set
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MDIO_DEVRES=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MIGRATION=y
 CONFIG_MMU_GATHER_PAGE_SIZE=y
 CONFIG_MODULES_USE_ELF_RELA=y
 CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 # CONFIG_MTD_CFI_GEOMETRY is not set
 # CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NEED_PER_CPU_KM=y
 CONFIG_NEED_SG_DMA_LENGTH=y
 CONFIG_NOT_COHERENT_CACHE=y
 CONFIG_NO_HZ=y
 CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_IRQS=512
 CONFIG_NVMEM=y
 CONFIG_NVMEM_SYSFS=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
 CONFIG_OF_FLATTREE=y
 CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_KOBJ=y
 CONFIG_OF_MDIO=y
 CONFIG_OF_NET=y
 CONFIG_OLD_SIGACTION=y
 CONFIG_OLD_SIGSUSPEND=y
 CONFIG_PACKING=y
 CONFIG_PAGE_OFFSET=0xc0000000
 CONFIG_PCI=y
 CONFIG_PCIEAER=y
 CONFIG_PCIEPORTBUS=y
 CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_ARCH_FALLBACKS=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
 CONFIG_PHYSICAL_START=0x00000000
 CONFIG_PHYS_64BIT=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 # CONFIG_PMU_SYSFS is not set
 CONFIG_PPC=y
 CONFIG_PPC32=y
 CONFIG_PPC44x_SIMPLE=y
 CONFIG_PPC4xx_GPIO=y
 CONFIG_PPC4xx_MSI=y
 CONFIG_PPC4xx_PCI_EXPRESS=y
 # CONFIG_PPC64 is not set
 # CONFIG_PPC_47x is not set
 # CONFIG_PPC_85xx is not set
 # CONFIG_PPC_8xx is not set
 CONFIG_PPC_ADV_DEBUG_DACS=2
 CONFIG_PPC_ADV_DEBUG_DAC_RANGE=y
 CONFIG_PPC_ADV_DEBUG_DVCS=2
 CONFIG_PPC_ADV_DEBUG_IACS=4
 CONFIG_PPC_ADV_DEBUG_REGS=y
 # CONFIG_PPC_BOOK3S_6xx is not set
 CONFIG_PPC_DCR=y
 CONFIG_PPC_DCR_NATIVE=y
 # CONFIG_PPC_EARLY_DEBUG is not set
 CONFIG_PPC_FPU=y
 CONFIG_PPC_INDIRECT_PCI=y
 # CONFIG_PPC_IRQ_SOFT_MASK_DEBUG is not set
 CONFIG_PPC_MMU_NOHASH=y
 CONFIG_PPC_MMU_NOHASH_32=y
 CONFIG_PPC_MSI_BITMAP=y
 CONFIG_PPC_PAGE_SHIFT=12
 # CONFIG_PPC_PTDUMP is not set
 CONFIG_PPC_UDBG_16550=y
 CONFIG_PPC_WERROR=y
 CONFIG_PTE_64BIT=y
 # CONFIG_RAINIER is not set
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
 CONFIG_REGULATOR=y
 CONFIG_RSEQ=y
 # CONFIG_SAM440EP is not set
 # CONFIG_SCOM_DEBUGFS is not set
 # CONFIG_SEQUOIA is not set
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_MCTRL_GPIO=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SGL_ALLOC=y
 CONFIG_SPARSE_IRQ=y
 CONFIG_SRCU=y
 CONFIG_SWPHY=y
 CONFIG_SYSCTL_EXCEPTION_TRACE=y
 # CONFIG_TAISHAN is not set
 CONFIG_TASK_SIZE=0xc0000000
 CONFIG_THREAD_INFO_IN_TASK=y
 CONFIG_THREAD_SHIFT=13
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_TINY_SRCU=y
 CONFIG_USB_SUPPORT=y
 CONFIG_VDSO32=y
 # CONFIG_VIRTIO_MENU is not set
 # CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
 # CONFIG_WARP is not set
 CONFIG_WATCHDOG_CORE=y
 # CONFIG_XILINX_SYSACE is not set
 CONFIG_XZ_DEC_BCJ=y
 CONFIG_XZ_DEC_POWERPC=y
 # CONFIG_YOSEMITE is not set
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_ZLIB_INFLATE=y
--- a/target/linux/apm821xx/patches-5.10/100-dwc2-disable-powerdown.patch
+++ b/target/linux/apm821xx/patches-5.10/100-dwc2-disable-powerdown.patch
@ -1,29 +0,0 @@
 From 88ca61467a0897c79b1fbf8f5c30691b43b52613 Mon Sep 17 00:00:00 2001
 From: Christian Lamparter <chunkeey@gmail.com>
 Date: Sun, 26 Dec 2021 22:36:29 +0200
 Subject: [PATCH] dwc2: temporary force to be powered up all times
 the APM821xx's onchip dwc2 misbehaves with 5.4 and 5.10
 when a USB device gets connected. Instead of announcing
 and setting up the USB devices it crashes and burns with:
 [   22.023476] dwc2 4bff80000.usbotg: dwc2_restore_global_registers: no global registers to restore
 [   22.032245] dwc2 4bff80000.usbotg: dwc2_exit_partial_power_down: failed to restore registers
 [   22.040647] dwc2 4bff80000.usbotg: exit partial_power_down failed
 [   22.058765] dwc2 4bff80000.usbotg: HC died; cleaning up
 This is all seemingly fixed with dwc2 from a 5.16-rc6.
 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 ---
 --- a/drivers/usb/dwc2/params.c
 +++ b/drivers/usb/dwc2/params.c
@@ -137,6 +137,7 @@ static void dwc2_set_amcc_params(struct
 	struct dwc2_core_params *p = &hsotg->params;
 	p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 +	p->power_down = DWC2_POWER_DOWN_PARAM_NONE;
 }
 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
--- a/target/linux/apm821xx/patches-5.10/201-add-amcc-apollo3g-support.patch
+++ b/target/linux/apm821xx/patches-5.10/201-add-amcc-apollo3g-support.patch
@ -1,30 +0,0 @@
 --- a/arch/powerpc/platforms/44x/Kconfig
 +++ b/arch/powerpc/platforms/44x/Kconfig
@@ -121,6 +121,17 @@ config CANYONLANDS
 	help
 	  This option enables support for the AMCC PPC460EX evaluation board.
 +config APOLLO3G
 +	bool "Apollo3G"
 +	depends on 44x
 +	default n
 +	select PPC44x_SIMPLE
 +	select APM821xx
 +	select IBM_EMAC_RGMII
 +	select 460EX
 +	help
 +	  This option enables support for the AMCC Apollo 3G board.
 +
 config GLACIER
 	bool "Glacier"
 	depends on 44x
 --- a/arch/powerpc/platforms/44x/ppc44x_simple.c
 +++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -47,6 +47,7 @@ machine_device_initcall(ppc44x_simple, p
  * board.c file for it rather than adding it to this list.
  */
 static char *board[] __initdata = {
 +	"amcc,apollo3g",
 	"amcc,arches",
 	"amcc,bamboo",
 	"apm,bluestone",
--- a/target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch
+++ b/target/linux/apm821xx/patches-5.10/300-fix-atheros-nics-on-apm82181.patch
@ -1,51 +0,0 @@
 --- a/arch/powerpc/platforms/4xx/pci.c
 +++ b/arch/powerpc/platforms/4xx/pci.c
@@ -1060,15 +1060,24 @@ static int __init apm821xx_pciex_init_po
 	u32 val;
 	/*
 -	 * Do a software reset on PCIe ports.
 -	 * This code is to fix the issue that pci drivers doesn't re-assign
 -	 * bus number for PCIE devices after Uboot
 -	 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
 -	 * PT quad port, SAS LSI 1064E)
 +	 * Only reset the PHY when no link is currently established.
 +	 * This is for the Atheros PCIe board which has problems to establish
 +	 * the link (again) after this PHY reset. All other currently tested
 +	 * PCIe boards don't show this problem.
 	 */
 -
 -	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
 -	mdelay(10);
 +	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
 +	if (!(val & 0x00001000)) {
 +		/*
 +		 * Do a software reset on PCIe ports.
 +		 * This code is to fix the issue that pci drivers doesn't re-assign
 +		 * bus number for PCIE devices after Uboot
 +		 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
 +		 * PT quad port, SAS LSI 1064E)
 +		 */
 +
 +		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
 +		mdelay(10);
 +	}
 	if (port->endpoint)
 		val = PTYPE_LEGACY_ENDPOINT << 20;
@@ -1085,9 +1094,12 @@ static int __init apm821xx_pciex_init_po
 	mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
 	mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
 -	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
 -	mdelay(50);
 -	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
 +	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
 +	if (!(val & 0x00001000)) {
 +		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
 +		mdelay(50);
 +		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
 +	}
 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
--- a/target/linux/apm821xx/patches-5.10/301-fix-memory-map-wndr4700.patch
+++ b/target/linux/apm821xx/patches-5.10/301-fix-memory-map-wndr4700.patch
@ -1,14 +0,0 @@
 --- a/arch/powerpc/platforms/4xx/pci.c
 +++ b/arch/powerpc/platforms/4xx/pci.c
@@ -1902,9 +1902,9 @@ static void __init ppc4xx_configure_pcie
 		 * if it works
 		 */
 		out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
 -		out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
 +		out_le32(mbase + PECFG_PIM0LAH, 0x00000008);
 		out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
 -		out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
 +		out_le32(mbase + PECFG_PIM1LAH, 0x0000000c);
 		out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
 		out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
--- a/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch
+++ b/target/linux/apm821xx/patches-5.10/802-usb-xhci-force-msi-renesas-xhci.patch
@ -1,53 +0,0 @@
 From a0dc613140bab907a3d5787a7ae7b0638bf674d0 Mon Sep 17 00:00:00 2001
 From: Christian Lamparter <chunkeey@gmail.com>
 Date: Thu, 23 Jun 2016 20:28:20 +0200
 Subject: [PATCH] usb: xhci: force MSI for uPD720201 and
 uPD720202
 The APM82181 does not support MSI-X. When probed, it will
 produce a noisy warning.
 ---
 drivers/usb/host/pci-quirks.c | 362 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 362 insertions(+)
 --- a/drivers/usb/host/xhci-pci.c
 +++ b/drivers/usb/host/xhci-pci.c
@@ -279,6 +279,7 @@ static void xhci_pci_quirks(struct devic
 	    pdev->device == 0x0015) {
 		xhci->quirks |= XHCI_RESET_ON_RESUME;
 		xhci->quirks |= XHCI_ZERO_64B_REGS;
 +		xhci->quirks |= XHCI_FORCE_MSI;
 	}
 	if (pdev->vendor == PCI_VENDOR_ID_VIA)
 		xhci->quirks |= XHCI_RESET_ON_RESUME;
 --- a/drivers/usb/host/xhci.c
 +++ b/drivers/usb/host/xhci.c
@@ -431,10 +431,14 @@ static int xhci_try_enable_msi(struct us
 		free_irq(hcd->irq, hcd);
 	hcd->irq = 0;
 -	ret = xhci_setup_msix(xhci);
 -	if (ret)
 -		/* fall back to msi*/
 +	if (xhci->quirks & XHCI_FORCE_MSI) {
 		ret = xhci_setup_msi(xhci);
 +	} else {
 +		ret = xhci_setup_msix(xhci);
 +		if (ret)
 +			/* fall back to msi*/
 +			ret = xhci_setup_msi(xhci);
 +	}
 	if (!ret) {
 		hcd->msi_enabled = 1;
 --- a/drivers/usb/host/xhci.h
 +++ b/drivers/usb/host/xhci.h
@@ -1902,6 +1902,7 @@ struct xhci_hcd {
 	struct xhci_hub		usb2_rhub;
 	struct xhci_hub		usb3_rhub;
 	/* support xHCI 1.0 spec USB2 hardware LPM */
 +#define XHCI_FORCE_MSI		(1 << 24)
 	unsigned		hw_lpm_support:1;
 	/* Broken Suspend flag for SNPS Suspend resume issue */
 	unsigned		broken_suspend:1;
--- a/target/linux/apm821xx/patches-5.10/803-hwmon-tc654-add-detection-routine.patch
+++ b/target/linux/apm821xx/patches-5.10/803-hwmon-tc654-add-detection-routine.patch
@ -1,65 +0,0 @@
 From 694f9bfb8efaef8a33e8992015ff9d0866faf4a2 Mon Sep 17 00:00:00 2001
 From: Christian Lamparter <chunkeey@gmail.com>
 Date: Sun, 17 Dec 2017 17:27:15 +0100
 Subject: [PATCH 1/2] hwmon: tc654 add detection routine
 This patch adds a detection routine for the TC654/TC655
 chips.  Both IDs are listed in the Datasheet.
 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 ---
 drivers/hwmon/tc654.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 --- a/drivers/hwmon/tc654.c
 +++ b/drivers/hwmon/tc654.c
@@ -55,6 +55,11 @@ enum tc654_regs {
 /* Register data is read (and cached) at most once per second. */
 #define TC654_UPDATE_INTERVAL		HZ
 +/* Manufacturer and Version Identification Register Values */
 +#define TC654_MFR_ID_MICROCHIP		0x84
 +#define TC654_VER_ID			0x00
 +#define TC655_VER_ID			0x01
 +
 struct tc654_data {
 	struct i2c_client *client;
@@ -481,6 +486,29 @@ static const struct i2c_device_id tc654_
 	{}
 };
 +static int
 +tc654_detect(struct i2c_client *new_client, struct i2c_board_info *info)
 +{
 +	struct i2c_adapter *adapter = new_client->adapter;
 +	int manufacturer, product;
 +
 +	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 +		return -ENODEV;
 +
 +	manufacturer = i2c_smbus_read_byte_data(new_client, TC654_REG_MFR_ID);
 +	if (manufacturer != TC654_MFR_ID_MICROCHIP)
 +		return -ENODEV;
 +
 +	product = i2c_smbus_read_byte_data(new_client, TC654_REG_VER_ID);
 +	if (!((product == TC654_VER_ID) || (product == TC655_VER_ID)))
 +		return -ENODEV;
 +
 +	strlcpy(info->type, product == TC654_VER_ID ? "tc654" : "tc655",
 +		I2C_NAME_SIZE);
 +	return 0;
 +}
 +
 +
 MODULE_DEVICE_TABLE(i2c, tc654_id);
 static struct i2c_driver tc654_driver = {
@@ -489,6 +517,7 @@ static struct i2c_driver tc654_driver =
 		   },
 	.probe_new = tc654_probe,
 	.id_table = tc654_id,
 +	.detect = tc654_detect,
 };
 module_i2c_driver(tc654_driver);
--- a/target/linux/apm821xx/patches-5.10/804-hwmon-tc654-add-thermal_cooling-device.patch
+++ b/target/linux/apm821xx/patches-5.10/804-hwmon-tc654-add-thermal_cooling-device.patch
@ -1,166 +0,0 @@
 From 4d49367c5303e3ebd17502a45b74de280f6be539 Mon Sep 17 00:00:00 2001
 From: Christian Lamparter <chunkeey@gmail.com>
 Date: Sun, 13 Feb 2022 01:47:33 +0100
 Subject: hwmon: (tc654) Add thermal_cooling device support
 Adds thermal_cooling device support to the tc654/tc655
 driver. This make it possible to integrate it into a
 device-tree supported thermal-zone node as a
 cooling device.
 I have been using this patch as part of the Netgear WNDR4700
 Centria NAS Router support within OpenWrt since 2016.
 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 Link: https://lore.kernel.org/r/20220213004733.2421193-1-chunkeey@gmail.com
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 ---
 --- a/drivers/hwmon/tc654.c
 +++ b/drivers/hwmon/tc654.c
@@ -15,6 +15,7 @@
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
 +#include <linux/thermal.h>
 #include <linux/util_macros.h>
 enum tc654_regs {
@@ -384,28 +385,20 @@ static ssize_t pwm_show(struct device *d
 	return sprintf(buf, "%d\n", pwm);
 }
 -static ssize_t pwm_store(struct device *dev, struct device_attribute *da,
 -			 const char *buf, size_t count)
 +static int _set_pwm(struct tc654_data *data, unsigned long val)
 {
 -	struct tc654_data *data = dev_get_drvdata(dev);
 	struct i2c_client *client = data->client;
 -	unsigned long val;
 	int ret;
 -	if (kstrtoul(buf, 10, &val))
 -		return -EINVAL;
 -	if (val > 255)
 -		return -EINVAL;
 -
 	mutex_lock(&data->update_lock);
 -	if (val == 0)
 +	if (val == 0) {
 		data->config |= TC654_REG_CONFIG_SDM;
 -	else
 +		data->duty_cycle = 0;
 +	} else {
 		data->config &= ~TC654_REG_CONFIG_SDM;
 -
 -	data->duty_cycle = find_closest(val, tc654_pwm_map,
 -					ARRAY_SIZE(tc654_pwm_map));
 +		data->duty_cycle = val - 1;
 +	}
 	ret = i2c_smbus_write_byte_data(client, TC654_REG_CONFIG, data->config);
 	if (ret < 0)
@@ -416,6 +409,24 @@ static ssize_t pwm_store(struct device *
 out:
 	mutex_unlock(&data->update_lock);
 +	return ret;
 +}
 +
 +static ssize_t pwm_store(struct device *dev, struct device_attribute *da,
 +			 const char *buf, size_t count)
 +{
 +	struct tc654_data *data = dev_get_drvdata(dev);
 +	unsigned long val;
 +	int ret;
 +
 +	if (kstrtoul(buf, 10, &val))
 +		return -EINVAL;
 +	if (val > 255)
 +		return -EINVAL;
 +	if (val > 0)
 +		val = find_closest(val, tc654_pwm_map, ARRAY_SIZE(tc654_pwm_map)) + 1;
 +
 +	ret = _set_pwm(data, val);
 	return ret < 0 ? ret : count;
 }
@@ -448,6 +459,58 @@ static struct attribute *tc654_attrs[] =
 ATTRIBUTE_GROUPS(tc654);
 /*
 + * thermal cooling device functions
 + *
 + * Account for the "ShutDown Mode (SDM)" state by offsetting
 + * the 16 PWM duty cycle states by 1.
 + *
 + * State  0 =   0% PWM | Shutdown - Fan(s) are off
 + * State  1 =  30% PWM | duty_cycle =  0
 + * State  2 = ~35% PWM | duty_cycle =  1
 + * [...]
 + * State 15 = ~95% PWM | duty_cycle = 14
 + * State 16 = 100% PWM | duty_cycle = 15
 + */
 +#define TC654_MAX_COOLING_STATE	16
 +
 +static int tc654_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state)
 +{
 +	*state = TC654_MAX_COOLING_STATE;
 +	return 0;
 +}
 +
 +static int tc654_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state)
 +{
 +	struct tc654_data *data = tc654_update_client(cdev->devdata);
 +
 +	if (IS_ERR(data))
 +		return PTR_ERR(data);
 +
 +	if (data->config & TC654_REG_CONFIG_SDM)
 +		*state = 0;	/* FAN is off */
 +	else
 +		*state = data->duty_cycle + 1;	/* offset PWM States by 1 */
 +
 +	return 0;
 +}
 +
 +static int tc654_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state)
 +{
 +	struct tc654_data *data = tc654_update_client(cdev->devdata);
 +
 +	if (IS_ERR(data))
 +		return PTR_ERR(data);
 +
 +	return _set_pwm(data, clamp_val(state, 0, TC654_MAX_COOLING_STATE));
 +}
 +
 +static const struct thermal_cooling_device_ops tc654_fan_cool_ops = {
 +	.get_max_state = tc654_get_max_state,
 +	.get_cur_state = tc654_get_cur_state,
 +	.set_cur_state = tc654_set_cur_state,
 +};
 +
 +/*
  * device probe and removal
  */
@@ -477,7 +540,18 @@ static int tc654_probe(struct i2c_client
 	hwmon_dev =
 	    devm_hwmon_device_register_with_groups(dev, client->name, data,
 						   tc654_groups);
 -	return PTR_ERR_OR_ZERO(hwmon_dev);
 +	if (IS_ERR(hwmon_dev))
 +		return PTR_ERR(hwmon_dev);
 +
 +	if (IS_ENABLED(CONFIG_THERMAL)) {
 +		struct thermal_cooling_device *cdev;
 +
 +		cdev = devm_thermal_of_cooling_device_register(dev, dev->of_node, client->name,
 +							       hwmon_dev, &tc654_fan_cool_ops);
 +		return PTR_ERR_OR_ZERO(cdev);
 +	}
 +
 +	return 0;
 }
 static const struct i2c_device_id tc654_id[] = {
--- a/target/linux/apm821xx/patches-5.10/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch
+++ b/target/linux/apm821xx/patches-5.10/900-powerpc-bootwrapper-force-gzip-as-mkimage-s-compress.patch
@ -1,29 +0,0 @@
 From c9395ad54e2cabb87d408becc37566f3d8248933 Mon Sep 17 00:00:00 2001
 From: Christian Lamparter <chunkeey@gmail.com>
 Date: Sun, 1 Dec 2019 02:08:23 +0100
 Subject: [PATCH] powerpc: bootwrapper: force gzip as mkimage's compression
 method
 Due to CONFIG_KERNEL_XZ symbol, the bootwrapper code tries to
 instruct the mkimage to use the xz compression, which isn't
 supported. This patch forces the gzip compression, which is
 supported and doesn't matter because the generated uImage for
 the apm821xx target gets ignored as the OpenWrt toolchain will
 do separate U-Boot kernel images for each device individually.
 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
 ---
 arch/powerpc/boot/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/arch/powerpc/boot/Makefile
 +++ b/arch/powerpc/boot/Makefile
@@ -251,7 +251,7 @@ compressor-$(CONFIG_KERNEL_LZO) := lzo
 # args (to if_changed): 1 = (this rule), 2 = platform, 3 = dts 4=dtb 5=initrd
 quiet_cmd_wrap	= WRAP    $@
 -      cmd_wrap	=$(CONFIG_SHELL) $(wrapper) -Z $(compressor-y) -c -o $@ -p $2 \
 +      cmd_wrap	=$(CONFIG_SHELL) $(wrapper) -Z gzip -c -o $@ -p $2 \
 		$(CROSSWRAP) $(if $3, -s $3)$(if $4, -d $4)$(if $5, -i $5) \
 		vmlinux
--- a/target/linux/archs38/config-5.10
+++ b/target/linux/archs38/config-5.10
@ -1,277 +0,0 @@
 # CONFIG_16KSTACKS is not set
 CONFIG_ARC=y
 CONFIG_ARCH_32BIT_OFF_T=y
 CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
 CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
 CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
 CONFIG_ARCH_HAS_PTE_SPECIAL=y
 CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
 CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y
 CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
 CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
 CONFIG_ARC_BUILTIN_DTB_NAME=""
 CONFIG_ARC_CACHE=y
 CONFIG_ARC_CACHE_LINE_SHIFT=6
 CONFIG_ARC_CACHE_PAGES=y
 CONFIG_ARC_CPU_HS=y
 CONFIG_ARC_CURR_IN_REG=y
 CONFIG_ARC_DBG=y
 # CONFIG_ARC_DBG_TLB_PARANOIA is not set
 CONFIG_ARC_DW2_UNWIND=y
 CONFIG_ARC_HAS_ACCL_REGS=y
 CONFIG_ARC_HAS_DCACHE=y
 # CONFIG_ARC_HAS_DCCM is not set
 CONFIG_ARC_HAS_DIV_REM=y
 CONFIG_ARC_HAS_ICACHE=y
 # CONFIG_ARC_HAS_ICCM is not set
 CONFIG_ARC_HAS_LL64=y
 CONFIG_ARC_HAS_LLSC=y
 # CONFIG_ARC_HAS_PAE40 is not set
 CONFIG_ARC_HAS_SWAPE=y
 CONFIG_ARC_IRQ_NO_AUTOSAVE=y
 CONFIG_ARC_KVADDR_SIZE=256
 CONFIG_ARC_MCIP=y
 # CONFIG_ARC_METAWARE_HLINK is not set
 CONFIG_ARC_MMU_V4=y
 # CONFIG_ARC_PAGE_SIZE_16K is not set
 # CONFIG_ARC_PAGE_SIZE_4K is not set
 CONFIG_ARC_PAGE_SIZE_8K=y
 CONFIG_ARC_PLAT_AXS10X=y
 # CONFIG_ARC_PLAT_EZNPS is not set
 # CONFIG_ARC_PLAT_TB10X is not set
 # CONFIG_ARC_SMP_HALT_ON_RESET is not set
 CONFIG_ARC_SOC_HSDK=y
 CONFIG_ARC_TIMERS=y
 CONFIG_ARC_TIMERS_64BIT=y
 CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y
 CONFIG_AXS103=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_SCSI_REQUEST=y
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
 CONFIG_CC_DISABLE_WARN_MAYBE_UNINITIALIZED=y
 CONFIG_CC_HAS_KASAN_GENERIC=y
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y
 CONFIG_CLK_HSDK=y
 CONFIG_ARC_TUNE_MCPU=""
 CONFIG_ARC_DSP_NONE=y
 # CONFIG_ARC_FPU_SAVE_RESTORE is not set
 # CONFIG_ARC_DSP_KERNEL is not set
 # CONFIG_ARC_DSP_USERSPACE is not set
 # CONFIG_ARC_DSP_AGU_USERSPACE is not set
 # CONFIG_ARC_LPB_DISABLE is not set
 # CONFIG_SPI_DW_DMA is not set
 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y
 # CONFIG_HARDENED_USERCOPY is not set
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_COMMON_CLK=y
 CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CPU_RMAP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_BLAKE2S=y
 CONFIG_CRYPTO_CRC32C=y
 CONFIG_CRYPTO_DRBG=y
 CONFIG_CRYPTO_DRBG_HMAC=y
 CONFIG_CRYPTO_DRBG_MENU=y
 CONFIG_CRYPTO_ECHAINIV=y
 CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_RNG_DEFAULT=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_DMADEVICES=y
 CONFIG_DMA_DIRECT_REMAP=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
 CONFIG_DMA_REMAP=y
 CONFIG_DMA_VIRTUAL_CHANNELS=y
 CONFIG_DTC=y
 CONFIG_DWMAC_ANARION=y
 CONFIG_DWMAC_GENERIC=y
 CONFIG_DW_APB_ICTL=y
 CONFIG_DW_AXI_DMAC=y
 CONFIG_EXT4_FS=y
 # CONFIG_EZNPS_GIC is not set
 CONFIG_FAT_FS=y
 CONFIG_FB=y
 CONFIG_FB_CMDLINE=y
 CONFIG_FIXED_PHY=y
 CONFIG_FS_IOMAP=y
 CONFIG_FS_MBCACHE=y
 CONFIG_FS_POSIX_ACL=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CSUM=y
 CONFIG_GENERIC_FIND_FIRST_BIT=y
 CONFIG_GENERIC_IRQ_CHIP=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_PENDING_IRQ=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_SNPS_CREG=y
 CONFIG_GRACE_PERIOD=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_HAVE_ARCH_TRACEHOOK=y
 CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
 CONFIG_HAVE_CLK=y
 CONFIG_HAVE_CLK_PREPARE=y
 CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
 CONFIG_HAVE_FUTEX_CMPXCHG=y
 CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
 CONFIG_HAVE_NET_DSA=y
 CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_PCI=y
 CONFIG_HAVE_PERF_EVENTS=y
 CONFIG_HZ_PERIODIC=y
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_IIO=y
 CONFIG_IIO_BUFFER=y
 CONFIG_IIO_KFIFO_BUF=y
 CONFIG_IIO_ST_PRESS=y
 CONFIG_IIO_ST_PRESS_I2C=y
 CONFIG_IIO_ST_PRESS_SPI=y
 CONFIG_IIO_ST_SENSORS_CORE=y
 CONFIG_IIO_ST_SENSORS_I2C=y
 CONFIG_IIO_ST_SENSORS_SPI=y
 CONFIG_IIO_TRIGGER=y
 CONFIG_IIO_TRIGGERED_BUFFER=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_WORK=y
 # CONFIG_ISA_ARCOMPACT is not set
 CONFIG_ISA_ARCV2=y
 CONFIG_JBD2=y
 CONFIG_KALLSYMS=y
 CONFIG_KERNEL_GZIP=y
 CONFIG_LIBFDT=y
 CONFIG_LINUX_LINK_BASE=0x90000000
 CONFIG_LINUX_RAM_BASE=0x80000000
 CONFIG_LOCKD=y
 CONFIG_LOCKUP_DETECTOR=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MICREL_PHY=y
 CONFIG_MIGRATION=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK=y
 CONFIG_MMC_DW=y
 # CONFIG_MMC_DW_BLUEFIELD is not set
 # CONFIG_MMC_DW_EXYNOS is not set
 # CONFIG_MMC_DW_HI3798CV200 is not set
 # CONFIG_MMC_DW_K3 is not set
 CONFIG_MMC_DW_PLTFM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_MODULES_USE_ELF_RELA=y
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_NAMESPACES=y
 CONFIG_NATIONAL_PHY=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NET_NS=y
 CONFIG_NET_PTP_CLASSIFY=y
 CONFIG_NFS_ACL_SUPPORT=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NO_IOPORT_MAP=y
 CONFIG_NR_CPUS=4
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
 CONFIG_OF_FLATTREE=y
 CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_KOBJ=y
 CONFIG_OF_MDIO=y
 CONFIG_OF_NET=y
 CONFIG_PADATA=y
 CONFIG_PAGE_POOL=y
 CONFIG_PGTABLE_LEVELS=2
 CONFIG_PHYLIB=y
 CONFIG_PHYLINK=y
 CONFIG_PPS=y
 CONFIG_PREEMPT=y
 CONFIG_PREEMPTION=y
 CONFIG_PREEMPT_COUNT=y
 # CONFIG_PREEMPT_NONE is not set
 CONFIG_PREEMPT_RCU=y
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_PTP_1588_CLOCK=y
 CONFIG_RATIONAL=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_REGMAP_SPI=y
 CONFIG_RESET_AXS10X=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_HSDK=y
 CONFIG_RESET_SIMPLE=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RPS=y
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_SCSI=y
 CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_8250_DWLIB=y
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 CONFIG_SERIAL_ARC=y
 CONFIG_SERIAL_ARC_CONSOLE=y
 CONFIG_SERIAL_ARC_NR_PORTS=1
 CONFIG_SERIAL_MCTRL_GPIO=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SG_POOL=y
 CONFIG_SMP=y
 CONFIG_SOFTLOCKUP_DETECTOR=y
 CONFIG_SPI=y
 CONFIG_SPI_DESIGNWARE=y
 CONFIG_SPI_DW_MMIO=y
 CONFIG_SPI_MASTER=y
 CONFIG_SPI_MEM=y
 CONFIG_SRCU=y
 CONFIG_STACKTRACE=y
 # CONFIG_STANDALONE is not set
 CONFIG_STMMAC_ETH=y
 CONFIG_STMMAC_PLATFORM=y
 # CONFIG_STMMAC_SELFTESTS is not set
 CONFIG_SUNRPC=y
 CONFIG_SWPHY=y
 CONFIG_TASKS_RCU=y
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_TIMER_OF=y
 CONFIG_TIMER_PROBE=y
 CONFIG_TI_ADC108S102=y
 CONFIG_TREE_SRCU=y
 CONFIG_UNINLINE_SPIN_UNLOCK=y
 CONFIG_USB_SUPPORT=y
 # CONFIG_USER_NS is not set
 CONFIG_VFAT_FS=y
 CONFIG_WATCHDOG_CORE=y
 CONFIG_XPS=y
--- a/target/linux/armvirt/32/config-5.10
+++ b/target/linux/armvirt/32/config-5.10
@ -1,75 +0,0 @@
 CONFIG_ALIGNMENT_TRAP=y
 CONFIG_ARCH_32BIT_OFF_T=y
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MULTIPLATFORM=y
 CONFIG_ARCH_MULTI_V6_V7=y
 CONFIG_ARCH_MULTI_V7=y
 CONFIG_ARCH_NR_GPIO=0
 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
 CONFIG_ARCH_VIRT=y
 CONFIG_ARM=y
 CONFIG_ARM_CPU_SUSPEND=y
 CONFIG_ARM_HAS_SG_CHAIN=y
 CONFIG_ARM_HEAVY_MB=y
 CONFIG_ARM_L1_CACHE_SHIFT=6
 CONFIG_ARM_L1_CACHE_SHIFT_6=y
 CONFIG_ARM_LPAE=y
 CONFIG_ARM_PATCH_IDIV=y
 CONFIG_ARM_PATCH_PHYS_VIRT=y
 CONFIG_ARM_PSCI=y
 CONFIG_ARM_THUMB=y
 CONFIG_ARM_UNWIND=y
 CONFIG_ARM_VIRT_EXT=y
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
 CONFIG_CACHE_L2X0=y
 CONFIG_COMPAT_32BIT_TIME=y
 CONFIG_CPU_32v6K=y
 CONFIG_CPU_32v7=y
 CONFIG_CPU_ABRT_EV7=y
 CONFIG_CPU_CACHE_V7=y
 CONFIG_CPU_CACHE_VIPT=y
 CONFIG_CPU_COPY_V6=y
 CONFIG_CPU_CP15=y
 CONFIG_CPU_CP15_MMU=y
 CONFIG_CPU_HAS_ASID=y
 CONFIG_CPU_PABRT_V7=y
 CONFIG_CPU_SPECTRE=y
 CONFIG_CPU_THUMB_CAPABLE=y
 CONFIG_CPU_TLB_V7=y
 CONFIG_CPU_V7=y
 CONFIG_CRYPTO_BLAKE2S=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
 CONFIG_DMA_OPS=y
 CONFIG_EDAC_ATOMIC_SCRUB=y
 CONFIG_GENERIC_VDSO_32=y
 CONFIG_HARDEN_BRANCH_PREDICTOR=y
 CONFIG_HAVE_SMP=y
 CONFIG_HZ_FIXED=0
 CONFIG_HZ_PERIODIC=y
 CONFIG_MIGHT_HAVE_CACHE_L2X0=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_NEON=y
 CONFIG_NR_CPUS=4
 CONFIG_OLD_SIGACTION=y
 CONFIG_OLD_SIGSUSPEND3=y
 CONFIG_OUTER_CACHE=y
 CONFIG_OUTER_CACHE_SYNC=y
 CONFIG_PAGE_OFFSET=0xC0000000
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_RTC_MC146818_LIB=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SMP_ON_UP=y
 CONFIG_SWP_EMULATE=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
 CONFIG_UNWINDER_ARM=y
 CONFIG_USE_OF=y
 CONFIG_VFP=y
 CONFIG_VFPv3=y
 CONFIG_XZ_DEC_ARM=y
 CONFIG_XZ_DEC_BCJ=y
 CONFIG_ZBOOT_ROM_BSS=0
 CONFIG_ZBOOT_ROM_TEXT=0
--- a/target/linux/armvirt/64/config-5.10
+++ b/target/linux/armvirt/64/config-5.10
@ -1,154 +0,0 @@
 CONFIG_64BIT=y
 CONFIG_ARCH_MMAP_RND_BITS=18
 CONFIG_ARCH_MMAP_RND_BITS_MAX=24
 CONFIG_ARCH_MMAP_RND_BITS_MIN=18
 CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
 CONFIG_ARCH_PROC_KCORE_TEXT=y
 CONFIG_ARCH_SPARSEMEM_DEFAULT=y
 CONFIG_ARCH_STACKWALK=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARM64=y
 CONFIG_ARM64_4K_PAGES=y
 CONFIG_ARM64_CNP=y
 CONFIG_ARM64_CRYPTO=y
 CONFIG_ARM64_ERRATUM_1165522=y
 CONFIG_ARM64_ERRATUM_1286807=y
 CONFIG_ARM64_ERRATUM_819472=y
 CONFIG_ARM64_ERRATUM_824069=y
 CONFIG_ARM64_ERRATUM_826319=y
 CONFIG_ARM64_ERRATUM_827319=y
 CONFIG_ARM64_ERRATUM_832075=y
 CONFIG_ARM64_ERRATUM_843419=y
 CONFIG_ARM64_HW_AFDBM=y
 CONFIG_ARM64_MODULE_PLTS=y
 CONFIG_ARM64_PAGE_SHIFT=12
 CONFIG_ARM64_PAN=y
 CONFIG_ARM64_PA_BITS=48
 CONFIG_ARM64_PA_BITS_48=y
 CONFIG_ARM64_PTR_AUTH=y
 CONFIG_ARM64_SVE=y
 CONFIG_ARM64_TAGGED_ADDR_ABI=y
 CONFIG_ARM64_UAO=y
 CONFIG_ARM64_VA_BITS=39
 CONFIG_ARM64_VA_BITS_39=y
 CONFIG_ARM64_VHE=y
 CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
 CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
 CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
 CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
 CONFIG_ARM_SBSA_WATCHDOG=y
 CONFIG_ATOMIC64_SELFTEST=y
 CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BLK_PM=y
 CONFIG_CAVIUM_TX2_ERRATUM_219=y
 CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
 CONFIG_CLK_SP810=y
 CONFIG_CLK_VEXPRESS_OSC=y
 # CONFIG_COMPAT_32BIT_TIME is not set
 CONFIG_CPU_IDLE=y
 CONFIG_CPU_IDLE_GOV_MENU=y
 CONFIG_CPU_PM=y
 CONFIG_CRYPTO_AES_ARM64=y
 CONFIG_CRYPTO_AES_ARM64_BS=y
 CONFIG_CRYPTO_AES_ARM64_CE=y
 CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
 CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
 CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
 CONFIG_CRYPTO_BLAKE2S=y
 CONFIG_CRYPTO_CHACHA20=y
 CONFIG_CRYPTO_CHACHA20_NEON=y
 CONFIG_CRYPTO_CRYPTD=y
 CONFIG_CRYPTO_GHASH_ARM64_CE=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_SHA1_ARM64_CE=y
 CONFIG_CRYPTO_SHA256_ARM64=y
 CONFIG_CRYPTO_SHA2_ARM64_CE=y
 CONFIG_CRYPTO_SHA512_ARM64=y
 CONFIG_CRYPTO_SIMD=y
 CONFIG_DMA_DIRECT_REMAP=y
 CONFIG_DMA_SHARED_BUFFER=y
 CONFIG_DRM=y
 CONFIG_DRM_BOCHS=y
 CONFIG_DRM_BRIDGE=y
 CONFIG_DRM_GEM_SHMEM_HELPER=y
 CONFIG_DRM_KMS_HELPER=y
 CONFIG_DRM_PANEL=y
 CONFIG_DRM_PANEL_BRIDGE=y
 CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
 CONFIG_DRM_QXL=y
 CONFIG_DRM_TTM=y
 CONFIG_DRM_TTM_DMA_PAGE_POOL=y
 CONFIG_DRM_TTM_HELPER=y
 CONFIG_DRM_VIRTIO_GPU=y
 CONFIG_DRM_VRAM_HELPER=y
 CONFIG_FB=y
 CONFIG_FB_ARMCLCD=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_IMAGEBLIT=y
 CONFIG_FB_CMDLINE=y
 CONFIG_FB_MODE_HELPERS=y
 # CONFIG_FLATMEM_MANUAL is not set
 CONFIG_FRAME_POINTER=y
 CONFIG_FSL_ERRATUM_A008585=y
 CONFIG_FUJITSU_ERRATUM_010001=y
 CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
 CONFIG_GENERIC_CSUM=y
 CONFIG_GPIO_GENERIC=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 CONFIG_HDMI=y
 CONFIG_HOLES_IN_ZONE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_VIRTIO=y
 CONFIG_I2C=y
 CONFIG_I2C_ALGOBIT=y
 CONFIG_I2C_BOARDINFO=y
 # CONFIG_ICST is not set
 CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
 CONFIG_KCMP=y
 CONFIG_LCD_CLASS_DEVICE=m
 # CONFIG_LCD_PLATFORM is not set
 CONFIG_MFD_CORE=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MFD_VEXPRESS_SYSREG=y
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MODULES_USE_ELF_RELA=y
 CONFIG_NEED_SG_DMA_LENGTH=y
 CONFIG_NO_HZ=y
 CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_NR_CPUS=64
 CONFIG_PM=y
 CONFIG_PM_CLK=y
 CONFIG_PM_GENERIC_DOMAINS=y
 CONFIG_PM_GENERIC_DOMAINS_OF=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_VEXPRESS=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_QUEUED_RWLOCKS=y
 CONFIG_QUEUED_SPINLOCKS=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 CONFIG_RTC_I2C_AND_SPI=y
 CONFIG_SMC91X=y
 CONFIG_SPARSEMEM=y
 CONFIG_SPARSEMEM_EXTREME=y
 CONFIG_SPARSEMEM_MANUAL=y
 CONFIG_SPARSEMEM_VMEMMAP=y
 CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
 CONFIG_SYNC_FILE=y
 CONFIG_SYSCTL_EXCEPTION_TRACE=y
 CONFIG_THREAD_INFO_IN_TASK=y
 CONFIG_UNMAP_KERNEL_AT_EL0=y
 CONFIG_VEXPRESS_CONFIG=y
 CONFIG_VIDEOMODE_HELPERS=y
 CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
 CONFIG_VMAP_STACK=y
 CONFIG_WATCHDOG_CORE=y
 CONFIG_ZONE_DMA32=y
--- a/target/linux/armvirt/config-5.10
+++ b/target/linux/armvirt/config-5.10
@ -1,155 +0,0 @@
 CONFIG_9P_FS=y
 # CONFIG_9P_FS_POSIX_ACL is not set
 # CONFIG_9P_FS_SECURITY is not set
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_KEEP_MEMBLOCK=y
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_ARM_AMBA=y
 CONFIG_ARM_ARCH_TIMER=y
 CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
 CONFIG_ARM_GIC=y
 CONFIG_ARM_GIC_V2M=y
 CONFIG_ARM_GIC_V3=y
 CONFIG_ARM_GIC_V3_ITS=y
 CONFIG_ARM_GIC_V3_ITS_PCI=y
 CONFIG_ARM_PSCI_FW=y
 CONFIG_BALLOON_COMPACTION=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_MQ_PCI=y
 CONFIG_BLK_MQ_VIRTIO=y
 CONFIG_BLK_SCSI_REQUEST=y
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_COMMON_CLK=y
 CONFIG_CPU_RMAP=y
 CONFIG_CRC16=y
 CONFIG_CRYPTO_CRC32=y
 CONFIG_CRYPTO_CRC32C=y
 CONFIG_CRYPTO_RNG2=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DMADEVICES=y
 CONFIG_DMA_ENGINE=y
 CONFIG_DMA_OF=y
 CONFIG_DMA_REMAP=y
 CONFIG_DTC=y
 CONFIG_EDAC_SUPPORT=y
 CONFIG_EXT4_FS=y
 CONFIG_F2FS_FS=y
 CONFIG_FAILOVER=y
 CONFIG_FIX_EARLYCON_MEM=y
 CONFIG_FS_IOMAP=y
 CONFIG_FS_MBCACHE=y
 CONFIG_FW_LOADER_PAGED_BUF=y
 CONFIG_GENERIC_ALLOCATOR=y
 CONFIG_GENERIC_ARCH_TOPOLOGY=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
 CONFIG_GENERIC_CPU_VULNERABILITIES=y
 CONFIG_GENERIC_EARLY_IOREMAP=y
 CONFIG_GENERIC_GETTIMEOFDAY=y
 CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
 CONFIG_GENERIC_IRQ_MIGRATION=y
 CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
 CONFIG_GENERIC_MSI_IRQ=y
 CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
 CONFIG_GENERIC_TIME_VSYSCALL=y
 CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_GPIO_PL061=y
 CONFIG_HANDLE_DOMAIN_IRQ=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT_MAP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_HVC_DRIVER=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
 CONFIG_IRQ_DOMAIN_HIERARCHY=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
 CONFIG_JBD2=y
 CONFIG_LIBFDT=y
 CONFIG_LOCK_DEBUGGING_SUPPORT=y
 CONFIG_LOCK_SPIN_ON_OWNER=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY_BALLOON=y
 CONFIG_MIGRATION=y
 CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_NET_9P=y
 # CONFIG_NET_9P_DEBUG is not set
 CONFIG_NET_9P_VIRTIO=y
 CONFIG_NET_FAILOVER=y
 CONFIG_NET_FLOW_LIMIT=y
 CONFIG_NLS=y
 CONFIG_NVMEM=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_EARLY_FLATTREE=y
 CONFIG_OF_FLATTREE=y
 CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_KOBJ=y
 CONFIG_OF_NET=y
 CONFIG_PADATA=y
 CONFIG_PAGE_REPORTING=y
 CONFIG_PARTITION_PERCPU=y
 CONFIG_PCI=y
 CONFIG_PCI_DOMAINS=y
 CONFIG_PCI_DOMAINS_GENERIC=y
 CONFIG_PCI_ECAM=y
 CONFIG_PCI_HOST_COMMON=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_MSI_IRQ_DOMAIN=y
 CONFIG_PGTABLE_LEVELS=3
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_RATIONAL=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RPS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RWSEM_SPIN_ON_OWNER=y
 CONFIG_SCSI=y
 CONFIG_SCSI_VIRTIO=y
 CONFIG_SERIAL_8250_FSL=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_MCTRL_GPIO=y
 CONFIG_SG_POOL=y
 CONFIG_SMP=y
 CONFIG_SPARSE_IRQ=y
 CONFIG_SRCU=y
 CONFIG_SWIOTLB=y
 CONFIG_SYS_SUPPORTS_HUGETLBFS=y
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_TIMER_OF=y
 CONFIG_TIMER_PROBE=y
 CONFIG_TREE_RCU=y
 CONFIG_TREE_SRCU=y
 CONFIG_USB_SUPPORT=y
 CONFIG_VIRTIO=y
 CONFIG_VIRTIO_BALLOON=y
 CONFIG_VIRTIO_BLK=y
 CONFIG_VIRTIO_CONSOLE=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
 CONFIG_VIRTIO_NET=y
 CONFIG_VIRTIO_PCI=y
 CONFIG_VIRTIO_PCI_LEGACY=y
 CONFIG_XPS=y
--- a/target/linux/at91/patches-5.10/101-ARM-at91-build-dtb-for-q5xr5.patch
+++ b/target/linux/at91/patches-5.10/101-ARM-at91-build-dtb-for-q5xr5.patch
@ -1,10 +0,0 @@
 --- a/arch/arm/boot/dts/Makefile
 +++ b/arch/arm/boot/dts/Makefile
@@ -41,6 +41,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 	at91-kizboxmini-mb.dtb \
 	at91-kizboxmini-rd.dtb \
 	at91-smartkiz.dtb \
 +	at91-q5xr5.dtb \
 	at91-wb45n.dtb \
 	at91sam9g15ek.dtb \
 	at91sam9g25-gardena-smart-gateway.dtb \
--- a/target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch
+++ b/target/linux/at91/patches-5.10/102-dt-bindings-clock-at91-add-sama7g5-pll-defines.patch
@ -1,65 +0,0 @@
 From 44bb7c72cdd830f54fe18e730205f892d9cbfe39 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:08 +0200
 Subject: [PATCH 102/247] dt-bindings: clock: at91: add sama7g5 pll defines
 Add SAMA7G5 specific PLL defines to be referenced in a phandle as a
 PMC_TYPE_CORE clock.
 Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 [claudiu.beznea@microchip.com: adapt comit message, adapt sama7g5.c]
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-3-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c       |  6 +++---
 include/dt-bindings/clock/at91.h | 10 ++++++++++
 2 files changed, 13 insertions(+), 3 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -182,13 +182,13 @@ static const struct {
 		  .p = "audiopll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 -		  .eid = PMC_I2S0_MUX, },
 +		  .eid = PMC_AUDIOPMCPLL, },
 		{ .n = "audiopll_diviock",
 		  .p = "audiopll_fracck",
 		  .l = &pll_layout_divio,
 		  .t = PLL_TYPE_DIV,
 -		  .eid = PMC_I2S1_MUX, },
 +		  .eid = PMC_AUDIOIOPLL, },
 	},
 	[PLL_ID_ETH] = {
@@ -835,7 +835,7 @@ static void __init sama7g5_pmc_setup(str
 	if (IS_ERR(regmap))
 		return;
 -	sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
 +	sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
 					nck(sama7g5_systemck),
 					nck(sama7g5_periphck),
 					nck(sama7g5_gck), 8);
 --- a/include/dt-bindings/clock/at91.h
 +++ b/include/dt-bindings/clock/at91.h
@@ -25,6 +25,16 @@
 #define PMC_PLLBCK		8
 #define PMC_AUDIOPLLCK		9
 +/* SAMA7G5 */
 +#define PMC_CPUPLL		(PMC_MAIN + 1)
 +#define PMC_SYSPLL		(PMC_MAIN + 2)
 +#define PMC_DDRPLL		(PMC_MAIN + 3)
 +#define PMC_IMGPLL		(PMC_MAIN + 4)
 +#define PMC_BAUDPLL		(PMC_MAIN + 5)
 +#define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
 +#define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
 +#define PMC_ETHPLL		(PMC_MAIN + 8)
 +
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
 #define AT91_PMC_LOCKA		1		/* PLLA Lock */
--- a/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch
+++ b/target/linux/at91/patches-5.10/103-clk-at91-sama7g5-allow-SYS-and-CPU-PLLs-to-be-export.patch
@ -1,41 +0,0 @@
 From 55c14526f970805a6bf2ed4b820f062334375abe Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:09 +0200
 Subject: [PATCH 103/247] clk: at91: sama7g5: allow SYS and CPU PLLs to be
 exported and referenced in DT
 Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock
 from phandle in DT.
 Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL]
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-4-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -117,7 +117,8 @@ static const struct {
 		  .p = "cpupll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 -		  .c = 1, },
 +		  .c = 1,
 +		  .eid = PMC_CPUPLL, },
 	},
 	[PLL_ID_SYS] = {
@@ -131,7 +132,8 @@ static const struct {
 		  .p = "syspll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 -		  .c = 1, },
 +		  .c = 1,
 +		  .eid = PMC_SYSPLL, },
 	},
 	[PLL_ID_DDR] = {
--- a/target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch
+++ b/target/linux/at91/patches-5.10/104-clk-at91-clk-master-add-5th-divisor-for-mck-master.patch
@ -1,42 +0,0 @@
 From b2349278894bb381fa26a8717d3093d53f08fd36 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:10 +0200
 Subject: [PATCH 104/247] clk: at91: clk-master: add 5th divisor for mck master
 clk-master can have 5 divisors with a field width of 3 bits
 on some products.
 Change the mask and number of divisors accordingly.
 Reported-by: Mihai Sain <mihai.sain@microchip.com>
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/clk-master.c | 2 +-
 drivers/clk/at91/pmc.h        | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
 --- a/drivers/clk/at91/clk-master.c
 +++ b/drivers/clk/at91/clk-master.c
@@ -15,7 +15,7 @@
 #define MASTER_PRES_MASK	0x7
 #define MASTER_PRES_MAX		MASTER_PRES_MASK
 #define MASTER_DIV_SHIFT	8
 -#define MASTER_DIV_MASK		0x3
 +#define MASTER_DIV_MASK		0x7
 #define PMC_MCR			0x30
 #define PMC_MCR_ID_MSK		GENMASK(3, 0)
 --- a/drivers/clk/at91/pmc.h
 +++ b/drivers/clk/at91/pmc.h
@@ -48,7 +48,7 @@ extern const struct clk_master_layout at
 struct clk_master_characteristics {
 	struct clk_range output;
 -	u32 divisors[4];
 +	u32 divisors[5];
 	u8 have_div3_pres;
 };
--- a/target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch
+++ b/target/linux/at91/patches-5.10/105-clk-at91-sama7g5-add-5th-divisor-for-mck0-layout-and.patch
@ -1,36 +0,0 @@
 From c41f013e13962dcc78239d5e4834214d44556cfb Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:11 +0200
 Subject: [PATCH 105/247] clk: at91: sama7g5: add 5th divisor for mck0 layout
 and characteristics
 This SoC has the 5th divisor for the mck0 master clock.
 Adapt the characteristics accordingly.
 Reported-by: Mihai Sain <mihai.sain@microchip.com>
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-6-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -775,13 +775,13 @@ static const struct clk_pll_characterist
 /* MCK0 characteristics. */
 static const struct clk_master_characteristics mck0_characteristics = {
 	.output = { .min = 140000000, .max = 200000000 },
 -	.divisors = { 1, 2, 4, 3 },
 +	.divisors = { 1, 2, 4, 3, 5 },
 	.have_div3_pres = 1,
 };
 /* MCK0 layout. */
 static const struct clk_master_layout mck0_layout = {
 -	.mask = 0x373,
 +	.mask = 0x773,
 	.pres_shift = 4,
 	.offset = 0x28,
 };
--- a/target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch
+++ b/target/linux/at91/patches-5.10/106-clk-at91-clk-sam9x60-pll-allow-runtime-changes-for-p.patch
@ -1,510 +0,0 @@
 From 6fe2927863de96edf35d8357712dbf83a489f556 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:12 +0200
 Subject: [PATCH 106/247] clk: at91: clk-sam9x60-pll: allow runtime changes for
 pll
 Allow runtime frequency changes for PLLs registered with proper flags.
 This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-7-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/clk-sam9x60-pll.c | 145 +++++++++++++++++++++++++----
 drivers/clk/at91/pmc.h             |   4 +-
 drivers/clk/at91/sam9x60.c         |  22 ++++-
 drivers/clk/at91/sama7g5.c         |  67 +++++++++----
 4 files changed, 197 insertions(+), 41 deletions(-)
 --- a/drivers/clk/at91/clk-sam9x60-pll.c
 +++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -229,6 +229,57 @@ static int sam9x60_frac_pll_set_rate(str
 	return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
 }
 +static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
 +					 unsigned long parent_rate)
 +{
 +	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 +	struct sam9x60_frac *frac = to_sam9x60_frac(core);
 +	struct regmap *regmap = core->regmap;
 +	unsigned long irqflags;
 +	unsigned int val, cfrac, cmul;
 +	long ret;
 +
 +	ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
 +	if (ret <= 0)
 +		return ret;
 +
 +	spin_lock_irqsave(core->lock, irqflags);
 +
 +	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
 +			   core->id);
 +	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
 +	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
 +	cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
 +
 +	if (cmul == frac->mul && cfrac == frac->frac)
 +		goto unlock;
 +
 +	regmap_write(regmap, AT91_PMC_PLL_CTRL1,
 +		     (frac->mul << core->layout->mul_shift) |
 +		     (frac->frac << core->layout->frac_shift));
 +
 +	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 +			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 +			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
 +
 +	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 +			   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
 +			   AT91_PMC_PLL_CTRL0_ENLOCK |
 +			   AT91_PMC_PLL_CTRL0_ENPLL);
 +
 +	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 +			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 +			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
 +
 +	while (!sam9x60_pll_ready(regmap, core->id))
 +		cpu_relax();
 +
 +unlock:
 +	spin_unlock_irqrestore(core->lock, irqflags);
 +
 +	return ret;
 +}
 +
 static const struct clk_ops sam9x60_frac_pll_ops = {
 	.prepare = sam9x60_frac_pll_prepare,
 	.unprepare = sam9x60_frac_pll_unprepare,
@@ -238,6 +289,15 @@ static const struct clk_ops sam9x60_frac
 	.set_rate = sam9x60_frac_pll_set_rate,
 };
 +static const struct clk_ops sam9x60_frac_pll_ops_chg = {
 +	.prepare = sam9x60_frac_pll_prepare,
 +	.unprepare = sam9x60_frac_pll_unprepare,
 +	.is_prepared = sam9x60_frac_pll_is_prepared,
 +	.recalc_rate = sam9x60_frac_pll_recalc_rate,
 +	.round_rate = sam9x60_frac_pll_round_rate,
 +	.set_rate = sam9x60_frac_pll_set_rate_chg,
 +};
 +
 static int sam9x60_div_pll_prepare(struct clk_hw *hw)
 {
 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
@@ -384,6 +444,44 @@ static int sam9x60_div_pll_set_rate(stru
 	return 0;
 }
 +static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
 +					unsigned long parent_rate)
 +{
 +	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 +	struct sam9x60_div *div = to_sam9x60_div(core);
 +	struct regmap *regmap = core->regmap;
 +	unsigned long irqflags;
 +	unsigned int val, cdiv;
 +
 +	div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
 +
 +	spin_lock_irqsave(core->lock, irqflags);
 +	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
 +			   core->id);
 +	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 +	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
 +
 +	/* Stop if nothing changed. */
 +	if (cdiv == div->div)
 +		goto unlock;
 +
 +	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 +			   core->layout->div_mask,
 +			   (div->div << core->layout->div_shift));
 +
 +	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 +			   AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 +			   AT91_PMC_PLL_UPDT_UPDATE | core->id);
 +
 +	while (!sam9x60_pll_ready(regmap, core->id))
 +		cpu_relax();
 +
 +unlock:
 +	spin_unlock_irqrestore(core->lock, irqflags);
 +
 +	return 0;
 +}
 +
 static const struct clk_ops sam9x60_div_pll_ops = {
 	.prepare = sam9x60_div_pll_prepare,
 	.unprepare = sam9x60_div_pll_unprepare,
@@ -393,17 +491,26 @@ static const struct clk_ops sam9x60_div_
 	.set_rate = sam9x60_div_pll_set_rate,
 };
 +static const struct clk_ops sam9x60_div_pll_ops_chg = {
 +	.prepare = sam9x60_div_pll_prepare,
 +	.unprepare = sam9x60_div_pll_unprepare,
 +	.is_prepared = sam9x60_div_pll_is_prepared,
 +	.recalc_rate = sam9x60_div_pll_recalc_rate,
 +	.round_rate = sam9x60_div_pll_round_rate,
 +	.set_rate = sam9x60_div_pll_set_rate_chg,
 +};
 +
 struct clk_hw * __init
 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			      const char *name, const char *parent_name,
 			      struct clk_hw *parent_hw, u8 id,
 			      const struct clk_pll_characteristics *characteristics,
 -			      const struct clk_pll_layout *layout, bool critical)
 +			      const struct clk_pll_layout *layout, u32 flags)
 {
 	struct sam9x60_frac *frac;
 	struct clk_hw *hw;
 	struct clk_init_data init;
 -	unsigned long parent_rate, flags;
 +	unsigned long parent_rate, irqflags;
 	unsigned int val;
 	int ret;
@@ -417,10 +524,12 @@ sam9x60_clk_register_frac_pll(struct reg
 	init.name = name;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 -	init.ops = &sam9x60_frac_pll_ops;
 -	init.flags = CLK_SET_RATE_GATE;
 -	if (critical)
 -		init.flags |= CLK_IS_CRITICAL;
 +	if (flags & CLK_SET_RATE_GATE)
 +		init.ops = &sam9x60_frac_pll_ops;
 +	else
 +		init.ops = &sam9x60_frac_pll_ops_chg;
 +
 +	init.flags = flags;
 	frac->core.id = id;
 	frac->core.hw.init = &init;
@@ -429,7 +538,7 @@ sam9x60_clk_register_frac_pll(struct reg
 	frac->core.regmap = regmap;
 	frac->core.lock = lock;
 -	spin_lock_irqsave(frac->core.lock, flags);
 +	spin_lock_irqsave(frac->core.lock, irqflags);
 	if (sam9x60_pll_ready(regmap, id)) {
 		regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 				   AT91_PMC_PLL_UPDT_ID_MSK, id);
@@ -457,7 +566,7 @@ sam9x60_clk_register_frac_pll(struct reg
 			goto free;
 		}
 	}
 -	spin_unlock_irqrestore(frac->core.lock, flags);
 +	spin_unlock_irqrestore(frac->core.lock, irqflags);
 	hw = &frac->core.hw;
 	ret = clk_hw_register(NULL, hw);
@@ -469,7 +578,7 @@ sam9x60_clk_register_frac_pll(struct reg
 	return hw;
 free:
 -	spin_unlock_irqrestore(frac->core.lock, flags);
 +	spin_unlock_irqrestore(frac->core.lock, irqflags);
 	kfree(frac);
 	return hw;
 }
@@ -478,12 +587,12 @@ struct clk_hw * __init
 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 			     const char *name, const char *parent_name, u8 id,
 			     const struct clk_pll_characteristics *characteristics,
 -			     const struct clk_pll_layout *layout, bool critical)
 +			     const struct clk_pll_layout *layout, u32 flags)
 {
 	struct sam9x60_div *div;
 	struct clk_hw *hw;
 	struct clk_init_data init;
 -	unsigned long flags;
 +	unsigned long irqflags;
 	unsigned int val;
 	int ret;
@@ -497,11 +606,11 @@ sam9x60_clk_register_div_pll(struct regm
 	init.name = name;
 	init.parent_names = &parent_name;
 	init.num_parents = 1;
 -	init.ops = &sam9x60_div_pll_ops;
 -	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 -		     CLK_SET_RATE_PARENT;
 -	if (critical)
 -		init.flags |= CLK_IS_CRITICAL;
 +	if (flags & CLK_SET_RATE_GATE)
 +		init.ops = &sam9x60_div_pll_ops;
 +	else
 +		init.ops = &sam9x60_div_pll_ops_chg;
 +	init.flags = flags;
 	div->core.id = id;
 	div->core.hw.init = &init;
@@ -510,14 +619,14 @@ sam9x60_clk_register_div_pll(struct regm
 	div->core.regmap = regmap;
 	div->core.lock = lock;
 -	spin_lock_irqsave(div->core.lock, flags);
 +	spin_lock_irqsave(div->core.lock, irqflags);
 	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 			   AT91_PMC_PLL_UPDT_ID_MSK, id);
 	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 	div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
 -	spin_unlock_irqrestore(div->core.lock, flags);
 +	spin_unlock_irqrestore(div->core.lock, irqflags);
 	hw = &div->core.hw;
 	ret = clk_hw_register(NULL, hw);
 --- a/drivers/clk/at91/pmc.h
 +++ b/drivers/clk/at91/pmc.h
@@ -190,14 +190,14 @@ struct clk_hw * __init
 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 			     const char *name, const char *parent_name, u8 id,
 			     const struct clk_pll_characteristics *characteristics,
 -			     const struct clk_pll_layout *layout, bool critical);
 +			     const struct clk_pll_layout *layout, u32 flags);
 struct clk_hw * __init
 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			      const char *name, const char *parent_name,
 			      struct clk_hw *parent_hw, u8 id,
 			      const struct clk_pll_characteristics *characteristics,
 -			      const struct clk_pll_layout *layout, bool critical);
 +			      const struct clk_pll_layout *layout, u32 flags);
 struct clk_hw * __init
 at91_clk_register_programmable(struct regmap *regmap, const char *name,
 --- a/drivers/clk/at91/sam9x60.c
 +++ b/drivers/clk/at91/sam9x60.c
@@ -224,13 +224,24 @@ static void __init sam9x60_pmc_setup(str
 	hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
 					   "mainck", sam9x60_pmc->chws[PMC_MAIN],
 					   0, &plla_characteristics,
 -					   &pll_frac_layout, true);
 +					   &pll_frac_layout,
 +					   /*
 +					    * This feeds pllack_divck which
 +					    * feeds CPU. It should not be
 +					    * disabled.
 +					    */
 +					   CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
 	if (IS_ERR(hw))
 		goto err_free;
 	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",
 					  "pllack_fracck", 0, &plla_characteristics,
 -					  &pll_div_layout, true);
 +					  &pll_div_layout,
 +					   /*
 +					    * This feeds CPU. It should not
 +					    * be disabled.
 +					    */
 +					  CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
 	if (IS_ERR(hw))
 		goto err_free;
@@ -239,13 +250,16 @@ static void __init sam9x60_pmc_setup(str
 	hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
 					   "main_osc", main_osc_hw, 1,
 					   &upll_characteristics,
 -					   &pll_frac_layout, false);
 +					   &pll_frac_layout, CLK_SET_RATE_GATE);
 	if (IS_ERR(hw))
 		goto err_free;
 	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",
 					  "upllck_fracck", 1, &upll_characteristics,
 -					  &pll_div_layout, false);
 +					  &pll_div_layout,
 +					  CLK_SET_RATE_GATE |
 +					  CLK_SET_PARENT_GATE |
 +					  CLK_SET_RATE_PARENT);
 	if (IS_ERR(hw))
 		goto err_free;
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -95,15 +95,15 @@ static const struct clk_pll_layout pll_l
  * @p:		clock parent
  * @l:		clock layout
  * @t:		clock type
 - * @f:		true if clock is critical and cannot be disabled
 + * @f:		clock flags
  * @eid:	export index in sama7g5->chws[] array
  */
 static const struct {
 	const char *n;
 	const char *p;
 	const struct clk_pll_layout *l;
 +	unsigned long f;
 	u8 t;
 -	u8 c;
 	u8 eid;
 } sama7g5_plls[][PLL_ID_MAX] = {
 	[PLL_ID_CPU] = {
@@ -111,13 +111,18 @@ static const struct {
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 		  .t = PLL_TYPE_FRAC,
 -		  .c = 1, },
 +		   /*
 +		    * This feeds cpupll_divpmcck which feeds CPU. It should
 +		    * not be disabled.
 +		    */
 +		  .f = CLK_IS_CRITICAL, },
 		{ .n = "cpupll_divpmcck",
 		  .p = "cpupll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 -		  .c = 1,
 +		   /* This feeds CPU. It should not be disabled. */
 +		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
 		  .eid = PMC_CPUPLL, },
 	},
@@ -126,13 +131,22 @@ static const struct {
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 		  .t = PLL_TYPE_FRAC,
 -		  .c = 1, },
 +		   /*
 +		    * This feeds syspll_divpmcck which may feed critial parts
 +		    * of the systems like timers. Therefore it should not be
 +		    * disabled.
 +		    */
 +		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 		{ .n = "syspll_divpmcck",
 		  .p = "syspll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 -		  .c = 1,
 +		   /*
 +		    * This may feed critial parts of the systems like timers.
 +		    * Therefore it should not be disabled.
 +		    */
 +		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
 		  .eid = PMC_SYSPLL, },
 	},
@@ -141,55 +155,71 @@ static const struct {
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 		  .t = PLL_TYPE_FRAC,
 -		  .c = 1, },
 +		   /*
 +		    * This feeds ddrpll_divpmcck which feeds DDR. It should not
 +		    * be disabled.
 +		    */
 +		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 		{ .n = "ddrpll_divpmcck",
 		  .p = "ddrpll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 -		  .c = 1, },
 +		   /* This feeds DDR. It should not be disabled. */
 +		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 	},
 	[PLL_ID_IMG] = {
 		{ .n = "imgpll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 -		  .t = PLL_TYPE_FRAC, },
 +		  .t = PLL_TYPE_FRAC,
 +		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "imgpll_divpmcck",
 		  .p = "imgpll_fracck",
 		  .l = &pll_layout_divpmc,
 -		  .t = PLL_TYPE_DIV, },
 +		  .t = PLL_TYPE_DIV,
 +		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 +		       CLK_SET_RATE_PARENT, },
 	},
 	[PLL_ID_BAUD] = {
 		{ .n = "baudpll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 -		  .t = PLL_TYPE_FRAC, },
 +		  .t = PLL_TYPE_FRAC,
 +		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "baudpll_divpmcck",
 		  .p = "baudpll_fracck",
 		  .l = &pll_layout_divpmc,
 -		  .t = PLL_TYPE_DIV, },
 +		  .t = PLL_TYPE_DIV,
 +		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 +		       CLK_SET_RATE_PARENT, },
 	},
 	[PLL_ID_AUDIO] = {
 		{ .n = "audiopll_fracck",
 		  .p = "main_xtal",
 		  .l = &pll_layout_frac,
 -		  .t = PLL_TYPE_FRAC, },
 +		  .t = PLL_TYPE_FRAC,
 +		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "audiopll_divpmcck",
 		  .p = "audiopll_fracck",
 		  .l = &pll_layout_divpmc,
 		  .t = PLL_TYPE_DIV,
 +		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 +		       CLK_SET_RATE_PARENT,
 		  .eid = PMC_AUDIOPMCPLL, },
 		{ .n = "audiopll_diviock",
 		  .p = "audiopll_fracck",
 		  .l = &pll_layout_divio,
 		  .t = PLL_TYPE_DIV,
 +		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 +		       CLK_SET_RATE_PARENT,
 		  .eid = PMC_AUDIOIOPLL, },
 	},
@@ -197,12 +227,15 @@ static const struct {
 		{ .n = "ethpll_fracck",
 		  .p = "main_xtal",
 		  .l = &pll_layout_frac,
 -		  .t = PLL_TYPE_FRAC, },
 +		  .t = PLL_TYPE_FRAC,
 +		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "ethpll_divpmcck",
 		  .p = "ethpll_fracck",
 		  .l = &pll_layout_divpmc,
 -		  .t = PLL_TYPE_DIV, },
 +		  .t = PLL_TYPE_DIV,
 +		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 +		       CLK_SET_RATE_PARENT, },
 	},
 };
@@ -890,7 +923,7 @@ static void __init sama7g5_pmc_setup(str
 					sama7g5_plls[i][j].p, parent_hw, i,
 					&pll_characteristics,
 					sama7g5_plls[i][j].l,
 -					sama7g5_plls[i][j].c);
 +					sama7g5_plls[i][j].f);
 				break;
 			case PLL_TYPE_DIV:
@@ -899,7 +932,7 @@ static void __init sama7g5_pmc_setup(str
 					sama7g5_plls[i][j].p, i,
 					&pll_characteristics,
 					sama7g5_plls[i][j].l,
 -					sama7g5_plls[i][j].c);
 +					sama7g5_plls[i][j].f);
 				break;
 			default:
--- a/target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch
+++ b/target/linux/at91/patches-5.10/107-clk-at91-sama7g5-remove-mck0-from-parent-list-of-oth.patch
@ -1,196 +0,0 @@
 From 7cfe2dfe5ac7c72b904e4b59b240caa42721ee07 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:13 +0200
 Subject: [PATCH 107/247] clk: at91: sama7g5: remove mck0 from parent list of
 other clocks
 MCK0 is changed at runtime by DVFS. Due to this, since not all IPs
 are glitch free aware at MCK0 changes, remove MCK0 from parent list
 of other clocks (e.g. generic clock, programmable/system clock, MCKX).
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-8-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 55 ++++++++++++++++++--------------------
 1 file changed, 26 insertions(+), 29 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -280,7 +280,7 @@ static const struct {
 	  .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
 	  .ep_mux_table = { 5, 6, 7, },
 	  .ep_count = 3,
 -	  .ep_chg_id = 6, },
 +	  .ep_chg_id = 5, },
 	{ .n = "mck4",
 	  .id = 4,
@@ -313,7 +313,7 @@ static const struct {
 };
 /* Mux table for programmable clocks. */
 -static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, };
 +static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
 /**
  * Peripheral clock description
@@ -436,7 +436,7 @@ static const struct {
 	  .pp = { "audiopll_divpmcck", },
 	  .pp_mux_table = { 9, },
 	  .pp_count = 1,
 -	  .pp_chg_id = 4, },
 +	  .pp_chg_id = 3, },
 	{ .n  = "csi_gclk",
 	  .id = 33,
@@ -548,7 +548,7 @@ static const struct {
 	  .pp = { "ethpll_divpmcck", },
 	  .pp_mux_table = { 10, },
 	  .pp_count = 1,
 -	  .pp_chg_id = 4, },
 +	  .pp_chg_id = 3, },
 	{ .n  = "gmac1_gclk",
 	  .id = 52,
@@ -580,7 +580,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 	  .pp_mux_table = { 5, 9, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n  = "i2smcc1_gclk",
 	  .id = 58,
@@ -588,7 +588,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 	  .pp_mux_table = { 5, 9, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n  = "mcan0_gclk",
 	  .id = 61,
@@ -730,7 +730,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 	  .pp_mux_table = { 5, 8, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n  = "sdmmc1_gclk",
 	  .id = 81,
@@ -738,7 +738,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 	  .pp_mux_table = { 5, 8, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n  = "sdmmc2_gclk",
 	  .id = 82,
@@ -746,7 +746,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
 	  .pp_mux_table = { 5, 8, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n  = "spdifrx_gclk",
 	  .id = 84,
@@ -754,7 +754,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 	  .pp_mux_table = { 5, 9, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n = "spdiftx_gclk",
 	  .id = 85,
@@ -762,7 +762,7 @@ static const struct {
 	  .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
 	  .pp_mux_table = { 5, 9, },
 	  .pp_count = 2,
 -	  .pp_chg_id = 5, },
 +	  .pp_chg_id = 4, },
 	{ .n  = "tcb0_ch0_gclk",
 	  .id = 88,
@@ -961,9 +961,8 @@ static void __init sama7g5_pmc_setup(str
 	parent_names[0] = md_slck_name;
 	parent_names[1] = td_slck_name;
 	parent_names[2] = "mainck";
 -	parent_names[3] = "mck0";
 	for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
 -		u8 num_parents = 4 + sama7g5_mckx[i].ep_count;
 +		u8 num_parents = 3 + sama7g5_mckx[i].ep_count;
 		u32 *mux_table;
 		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
@@ -971,10 +970,10 @@ static void __init sama7g5_pmc_setup(str
 		if (!mux_table)
 			goto err_free;
 -		SAMA7G5_INIT_TABLE(mux_table, 4);
 -		SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table,
 +		SAMA7G5_INIT_TABLE(mux_table, 3);
 +		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
 				   sama7g5_mckx[i].ep_count);
 -		SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep,
 +		SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep,
 				   sama7g5_mckx[i].ep_count);
 		hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
@@ -997,20 +996,19 @@ static void __init sama7g5_pmc_setup(str
 	parent_names[0] = md_slck_name;
 	parent_names[1] = td_slck_name;
 	parent_names[2] = "mainck";
 -	parent_names[3] = "mck0";
 -	parent_names[4] = "syspll_divpmcck";
 -	parent_names[5] = "ddrpll_divpmcck";
 -	parent_names[6] = "imgpll_divpmcck";
 -	parent_names[7] = "baudpll_divpmcck";
 -	parent_names[8] = "audiopll_divpmcck";
 -	parent_names[9] = "ethpll_divpmcck";
 +	parent_names[3] = "syspll_divpmcck";
 +	parent_names[4] = "ddrpll_divpmcck";
 +	parent_names[5] = "imgpll_divpmcck";
 +	parent_names[6] = "baudpll_divpmcck";
 +	parent_names[7] = "audiopll_divpmcck";
 +	parent_names[8] = "ethpll_divpmcck";
 	for (i = 0; i < 8; i++) {
 		char name[6];
 		snprintf(name, sizeof(name), "prog%d", i);
 		hw = at91_clk_register_programmable(regmap, name, parent_names,
 -						    10, i,
 +						    9, i,
 						    &programmable_layout,
 						    sama7g5_prog_mux_table);
 		if (IS_ERR(hw))
@@ -1047,9 +1045,8 @@ static void __init sama7g5_pmc_setup(str
 	parent_names[0] = md_slck_name;
 	parent_names[1] = td_slck_name;
 	parent_names[2] = "mainck";
 -	parent_names[3] = "mck0";
 	for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
 -		u8 num_parents = 4 + sama7g5_gck[i].pp_count;
 +		u8 num_parents = 3 + sama7g5_gck[i].pp_count;
 		u32 *mux_table;
 		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
@@ -1057,10 +1054,10 @@ static void __init sama7g5_pmc_setup(str
 		if (!mux_table)
 			goto err_free;
 -		SAMA7G5_INIT_TABLE(mux_table, 4);
 -		SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table,
 +		SAMA7G5_INIT_TABLE(mux_table, 3);
 +		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
 				   sama7g5_gck[i].pp_count);
 -		SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp,
 +		SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp,
 				   sama7g5_gck[i].pp_count);
 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
--- a/target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch
+++ b/target/linux/at91/patches-5.10/108-clk-at91-sama7g5-decrease-lower-limit-for-MCK0-rate.patch
@ -1,30 +0,0 @@
 From 8b88f1e9918c173b24b43015cdb713cdde9e4d17 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:14 +0200
 Subject: [PATCH 108/247] clk: at91: sama7g5: decrease lower limit for MCK0
 rate
 On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
 CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
 also changed by DVFS to avoid over/under clocking of MCK0 consumers.
 The lower limit is changed to be able to set MCK0 accordingly by
 DVFS.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -807,7 +807,7 @@ static const struct clk_pll_characterist
 /* MCK0 characteristics. */
 static const struct clk_master_characteristics mck0_characteristics = {
 -	.output = { .min = 140000000, .max = 200000000 },
 +	.output = { .min = 50000000, .max = 200000000 },
 	.divisors = { 1, 2, 4, 3, 5 },
 	.have_div3_pres = 1,
 };
--- a/target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch
+++ b/target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch
@ -1,221 +0,0 @@
 From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:15 +0200
 Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher
 than 1GHz
 Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
 than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++---------
 1 file changed, 47 insertions(+), 14 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l
 	.endiv_shift	= 30,
 };
 +/*
 + * CPU PLL output range.
 + * Notice: The upper limit has been setup to 1000000002 due to hardware
 + * block which cannot output exactly 1GHz.
 + */
 +static const struct clk_range cpu_pll_outputs[] = {
 +	{ .min = 2343750, .max = 1000000002 },
 +};
 +
 +/* PLL output range. */
 +static const struct clk_range pll_outputs[] = {
 +	{ .min = 2343750, .max = 1200000000 },
 +};
 +
 +/* CPU PLL characteristics. */
 +static const struct clk_pll_characteristics cpu_pll_characteristics = {
 +	.input = { .min = 12000000, .max = 50000000 },
 +	.num_output = ARRAY_SIZE(cpu_pll_outputs),
 +	.output = cpu_pll_outputs,
 +};
 +
 +/* PLL characteristics. */
 +static const struct clk_pll_characteristics pll_characteristics = {
 +	.input = { .min = 12000000, .max = 50000000 },
 +	.num_output = ARRAY_SIZE(pll_outputs),
 +	.output = pll_outputs,
 +};
 +
 /**
  * PLL clocks description
  * @n:		clock name
  * @p:		clock parent
  * @l:		clock layout
 + * @c:		clock characteristics
  * @t:		clock type
  * @f:		clock flags
  * @eid:	export index in sama7g5->chws[] array
@@ -102,6 +131,7 @@ static const struct {
 	const char *n;
 	const char *p;
 	const struct clk_pll_layout *l;
 +	const struct clk_pll_characteristics *c;
 	unsigned long f;
 	u8 t;
 	u8 eid;
@@ -110,6 +140,7 @@ static const struct {
 		{ .n = "cpupll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 +		  .c = &cpu_pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		   /*
 		    * This feeds cpupll_divpmcck which feeds CPU. It should
@@ -120,6 +151,7 @@ static const struct {
 		{ .n = "cpupll_divpmcck",
 		  .p = "cpupll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &cpu_pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		   /* This feeds CPU. It should not be disabled. */
 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
@@ -130,6 +162,7 @@ static const struct {
 		{ .n = "syspll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		   /*
 		    * This feeds syspll_divpmcck which may feed critial parts
@@ -141,6 +174,7 @@ static const struct {
 		{ .n = "syspll_divpmcck",
 		  .p = "syspll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		   /*
 		    * This may feed critial parts of the systems like timers.
@@ -154,6 +188,7 @@ static const struct {
 		{ .n = "ddrpll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		   /*
 		    * This feeds ddrpll_divpmcck which feeds DDR. It should not
@@ -164,6 +199,7 @@ static const struct {
 		{ .n = "ddrpll_divpmcck",
 		  .p = "ddrpll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		   /* This feeds DDR. It should not be disabled. */
 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
@@ -173,12 +209,14 @@ static const struct {
 		{ .n = "imgpll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "imgpll_divpmcck",
 		  .p = "imgpll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 		       CLK_SET_RATE_PARENT, },
@@ -188,12 +226,14 @@ static const struct {
 		{ .n = "baudpll_fracck",
 		  .p = "mainck",
 		  .l = &pll_layout_frac,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "baudpll_divpmcck",
 		  .p = "baudpll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 		       CLK_SET_RATE_PARENT, },
@@ -203,12 +243,14 @@ static const struct {
 		{ .n = "audiopll_fracck",
 		  .p = "main_xtal",
 		  .l = &pll_layout_frac,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "audiopll_divpmcck",
 		  .p = "audiopll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 		       CLK_SET_RATE_PARENT,
@@ -217,6 +259,7 @@ static const struct {
 		{ .n = "audiopll_diviock",
 		  .p = "audiopll_fracck",
 		  .l = &pll_layout_divio,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 		       CLK_SET_RATE_PARENT,
@@ -227,12 +270,14 @@ static const struct {
 		{ .n = "ethpll_fracck",
 		  .p = "main_xtal",
 		  .l = &pll_layout_frac,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		  .f = CLK_SET_RATE_GATE, },
 		{ .n = "ethpll_divpmcck",
 		  .p = "ethpll_fracck",
 		  .l = &pll_layout_divpmc,
 +		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		  .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 		       CLK_SET_RATE_PARENT, },
@@ -793,18 +838,6 @@ static const struct {
 	  .pp_chg_id = INT_MIN, },
 };
 -/* PLL output range. */
 -static const struct clk_range pll_outputs[] = {
 -	{ .min = 2343750, .max = 1200000000 },
 -};
 -
 -/* PLL characteristics. */
 -static const struct clk_pll_characteristics pll_characteristics = {
 -	.input = { .min = 12000000, .max = 50000000 },
 -	.num_output = ARRAY_SIZE(pll_outputs),
 -	.output = pll_outputs,
 -};
 -
 /* MCK0 characteristics. */
 static const struct clk_master_characteristics mck0_characteristics = {
 	.output = { .min = 50000000, .max = 200000000 },
@@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str
 				hw = sam9x60_clk_register_frac_pll(regmap,
 					&pmc_pll_lock, sama7g5_plls[i][j].n,
 					sama7g5_plls[i][j].p, parent_hw, i,
 -					&pll_characteristics,
 +					sama7g5_plls[i][j].c,
 					sama7g5_plls[i][j].l,
 					sama7g5_plls[i][j].f);
 				break;
@@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str
 				hw = sam9x60_clk_register_div_pll(regmap,
 					&pmc_pll_lock, sama7g5_plls[i][j].n,
 					sama7g5_plls[i][j].p, i,
 -					&pll_characteristics,
 +					sama7g5_plls[i][j].c,
 					sama7g5_plls[i][j].l,
 					sama7g5_plls[i][j].f);
 				break;
--- a/target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch
+++ b/target/linux/at91/patches-5.10/110-clk-at91-clk-master-re-factor-master-clock.patch
--- a/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch
+++ b/target/linux/at91/patches-5.10/111-clk-at91-sama7g5-register-cpu-clock.patch
@ -1,65 +0,0 @@
 From 36e97c421dd9f866e31fe14bcb7af01334791890 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Thu, 19 Nov 2020 17:43:17 +0200
 Subject: [PATCH 111/247] clk: at91: sama7g5: register cpu clock
 Register CPU clock as being the master clock prescaler. This would
 be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
 between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
 frequencies supported by SAMA7G5 could be directly received from
 CPUPLL + master clock prescaler and the extra divider would do no work in
 case it would be enabled.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c       | 13 ++++++-------
 include/dt-bindings/clock/at91.h |  1 +
 2 files changed, 7 insertions(+), 7 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -904,7 +904,7 @@ static void __init sama7g5_pmc_setup(str
 	if (IS_ERR(regmap))
 		return;
 -	sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1,
 +	sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1,
 					nck(sama7g5_systemck),
 					nck(sama7g5_periphck),
 					nck(sama7g5_gck), 8);
@@ -981,18 +981,17 @@ static void __init sama7g5_pmc_setup(str
 		}
 	}
 -	parent_names[0] = md_slck_name;
 -	parent_names[1] = "mainck";
 -	parent_names[2] = "cpupll_divpmcck";
 -	parent_names[3] = "syspll_divpmcck";
 -	hw = at91_clk_register_master_pres(regmap, "mck0_pres", 4, parent_names,
 +	parent_names[0] = "cpupll_divpmcck";
 +	hw = at91_clk_register_master_pres(regmap, "cpuck", 1, parent_names,
 					   &mck0_layout, &mck0_characteristics,
 					   &pmc_mck0_lock,
 					   CLK_SET_RATE_PARENT, 0);
 	if (IS_ERR(hw))
 		goto err_free;
 -	hw = at91_clk_register_master_div(regmap, "mck0_div", "mck0_pres",
 +	sama7g5_pmc->chws[PMC_CPU] = hw;
 +
 +	hw = at91_clk_register_master_div(regmap, "mck0", "cpuck",
 					  &mck0_layout, &mck0_characteristics,
 					  &pmc_mck0_lock, 0);
 	if (IS_ERR(hw))
 --- a/include/dt-bindings/clock/at91.h
 +++ b/include/dt-bindings/clock/at91.h
@@ -34,6 +34,7 @@
 #define PMC_AUDIOPMCPLL		(PMC_MAIN + 6)
 #define PMC_AUDIOIOPLL		(PMC_MAIN + 7)
 #define PMC_ETHPLL		(PMC_MAIN + 8)
 +#define PMC_CPU			(PMC_MAIN + 9)
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
--- a/target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch
+++ b/target/linux/at91/patches-5.10/112-clk-at91-Fix-the-declaration-of-the-clocks.patch
@ -1,181 +0,0 @@
 From 5a25e2437af0db535b17da352fb16680a8dfdeda Mon Sep 17 00:00:00 2001
 From: Tudor Ambarus <tudor.ambarus@microchip.com>
 Date: Wed, 3 Feb 2021 17:43:32 +0200
 Subject: [PATCH 112/247] clk: at91: Fix the declaration of the clocks
 These are all "early clocks" that require initialization just at
 of_clk_init() time. Use CLK_OF_DECLARE() to declare them.
 This also fixes a problem that was spotted when fw_devlink was
 set to 'on' by default: the boards failed to boot. The reason is
 that CLK_OF_DECLARE_DRIVER() clears the OF_POPULATED and causes
 the consumers of the clock to be postponed by fw_devlink until
 the second initialization routine of the clock has been completed.
 One of the consumers of the clock is the timer, which is used as a
 clocksource, and needs the clock initialized early. Postponing the
 timers caused the fail at boot.
 Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
 Link: https://lore.kernel.org/r/20210203154332.470587-1-tudor.ambarus@microchip.com
 Acked-by: Saravana Kannan <saravanak@google.com>
 Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/at91rm9200.c  |  3 +--
 drivers/clk/at91/at91sam9260.c | 16 ++++++++--------
 drivers/clk/at91/at91sam9g45.c |  3 +--
 drivers/clk/at91/at91sam9n12.c |  3 +--
 drivers/clk/at91/at91sam9rl.c  |  3 ++-
 drivers/clk/at91/at91sam9x5.c  | 20 ++++++++++----------
 drivers/clk/at91/sama5d2.c     |  3 ++-
 drivers/clk/at91/sama5d3.c     |  2 +-
 drivers/clk/at91/sama5d4.c     |  3 ++-
 9 files changed, 28 insertions(+), 28 deletions(-)
 --- a/drivers/clk/at91/at91rm9200.c
 +++ b/drivers/clk/at91/at91rm9200.c
@@ -215,5 +215,4 @@ err_free:
  * deferring properly. Once this is fixed, this can be switched to a platform
  * driver.
  */
 -CLK_OF_DECLARE_DRIVER(at91rm9200_pmc, "atmel,at91rm9200-pmc",
 -		      at91rm9200_pmc_setup);
 +CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);
 --- a/drivers/clk/at91/at91sam9260.c
 +++ b/drivers/clk/at91/at91sam9260.c
@@ -491,26 +491,26 @@ static void __init at91sam9260_pmc_setup
 {
 	at91sam926x_pmc_setup(np, &at91sam9260_data);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9260_pmc, "atmel,at91sam9260-pmc",
 -		      at91sam9260_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);
 static void __init at91sam9261_pmc_setup(struct device_node *np)
 {
 	at91sam926x_pmc_setup(np, &at91sam9261_data);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9261_pmc, "atmel,at91sam9261-pmc",
 -		      at91sam9261_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);
 static void __init at91sam9263_pmc_setup(struct device_node *np)
 {
 	at91sam926x_pmc_setup(np, &at91sam9263_data);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9263_pmc, "atmel,at91sam9263-pmc",
 -		      at91sam9263_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);
 static void __init at91sam9g20_pmc_setup(struct device_node *np)
 {
 	at91sam926x_pmc_setup(np, &at91sam9g20_data);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9g20_pmc, "atmel,at91sam9g20-pmc",
 -		      at91sam9g20_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);
 --- a/drivers/clk/at91/at91sam9g45.c
 +++ b/drivers/clk/at91/at91sam9g45.c
@@ -228,5 +228,4 @@ err_free:
  * The TCB is used as the clocksource so its clock is needed early. This means
  * this can't be a platform driver.
  */
 -CLK_OF_DECLARE_DRIVER(at91sam9g45_pmc, "atmel,at91sam9g45-pmc",
 -		      at91sam9g45_pmc_setup);
 +CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);
 --- a/drivers/clk/at91/at91sam9n12.c
 +++ b/drivers/clk/at91/at91sam9n12.c
@@ -255,5 +255,4 @@ err_free:
  * The TCB is used as the clocksource so its clock is needed early. This means
  * this can't be a platform driver.
  */
 -CLK_OF_DECLARE_DRIVER(at91sam9n12_pmc, "atmel,at91sam9n12-pmc",
 -		      at91sam9n12_pmc_setup);
 +CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
 --- a/drivers/clk/at91/at91sam9rl.c
 +++ b/drivers/clk/at91/at91sam9rl.c
@@ -186,4 +186,5 @@ static void __init at91sam9rl_pmc_setup(
 err_free:
 	kfree(at91sam9rl_pmc);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
 --- a/drivers/clk/at91/at91sam9x5.c
 +++ b/drivers/clk/at91/at91sam9x5.c
@@ -302,33 +302,33 @@ static void __init at91sam9g15_pmc_setup
 {
 	at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9g15_pmc, "atmel,at91sam9g15-pmc",
 -		      at91sam9g15_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);
 static void __init at91sam9g25_pmc_setup(struct device_node *np)
 {
 	at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9g25_pmc, "atmel,at91sam9g25-pmc",
 -		      at91sam9g25_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);
 static void __init at91sam9g35_pmc_setup(struct device_node *np)
 {
 	at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9g35_pmc, "atmel,at91sam9g35-pmc",
 -		      at91sam9g35_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);
 static void __init at91sam9x25_pmc_setup(struct device_node *np)
 {
 	at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9x25_pmc, "atmel,at91sam9x25-pmc",
 -		      at91sam9x25_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);
 static void __init at91sam9x35_pmc_setup(struct device_node *np)
 {
 	at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
 }
 -CLK_OF_DECLARE_DRIVER(at91sam9x35_pmc, "atmel,at91sam9x35-pmc",
 -		      at91sam9x35_pmc_setup);
 +
 +CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);
 --- a/drivers/clk/at91/sama5d2.c
 +++ b/drivers/clk/at91/sama5d2.c
@@ -372,4 +372,5 @@ static void __init sama5d2_pmc_setup(str
 err_free:
 	kfree(sama5d2_pmc);
 }
 -CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
 +
 +CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
 --- a/drivers/clk/at91/sama5d3.c
 +++ b/drivers/clk/at91/sama5d3.c
@@ -255,4 +255,4 @@ err_free:
  * The TCB is used as the clocksource so its clock is needed early. This means
  * this can't be a platform driver.
  */
 -CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
 +CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
 --- a/drivers/clk/at91/sama5d4.c
 +++ b/drivers/clk/at91/sama5d4.c
@@ -286,4 +286,5 @@ static void __init sama5d4_pmc_setup(str
 err_free:
 	kfree(sama5d4_pmc);
 }
 -CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
 +
 +CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
--- a/target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch
+++ b/target/linux/at91/patches-5.10/113-clk-at91-Trivial-typo-fixes-in-the-file-sama7g5.c.patch
@ -1,45 +0,0 @@
 From 268b36c42b7d1e480dd56ecfec626a46f4b5975e Mon Sep 17 00:00:00 2001
 From: Bhaskar Chowdhury <unixbhaskar@gmail.com>
 Date: Sat, 13 Mar 2021 11:02:22 +0530
 Subject: [PATCH 113/247] clk: at91: Trivial typo fixes in the file sama7g5.c
 s/critial/critical/  ......two different places
 s/parrent/parent/
 Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com>
 Link: https://lore.kernel.org/r/20210313053222.14706-1-unixbhaskar@gmail.com
 Acked-by: Randy Dunlap <rdunlap@infradead.org>
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -166,7 +166,7 @@ static const struct {
 		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_FRAC,
 		   /*
 -		    * This feeds syspll_divpmcck which may feed critial parts
 +		    * This feeds syspll_divpmcck which may feed critical parts
 		    * of the systems like timers. Therefore it should not be
 		    * disabled.
 		    */
@@ -178,7 +178,7 @@ static const struct {
 		  .c = &pll_characteristics,
 		  .t = PLL_TYPE_DIV,
 		   /*
 -		    * This may feed critial parts of the systems like timers.
 +		    * This may feed critical parts of the systems like timers.
 		    * Therefore it should not be disabled.
 		    */
 		  .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
@@ -455,7 +455,7 @@ static const struct {
  * @pp:			PLL parents
  * @pp_mux_table:	PLL parents mux table
  * @r:			clock output range
 - * @pp_chg_id:		id in parrent array of changeable PLL parent
 + * @pp_chg_id:		id in parent array of changeable PLL parent
  * @pp_count:		PLL parents count
  * @id:			clock id
  */
--- a/target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch
+++ b/target/linux/at91/patches-5.10/114-clk-at91-sama7g5-remove-all-kernel-doc-kernel-doc-wa.patch
@ -1,90 +0,0 @@
 From 9997227090cf529675aeb775585ec9f6c2f0f131 Mon Sep 17 00:00:00 2001
 From: Randy Dunlap <rdunlap@infradead.org>
 Date: Thu, 19 Aug 2021 15:32:37 -0700
 Subject: [PATCH 114/247] clk: at91: sama7g5: remove all kernel-doc &
 kernel-doc warnings
 Remove all "/**" kernel-doc markers from sama7g5.c since they are
 all internal to this driver source file only.
 This eliminates 14 warnings that were reported by the kernel test robot.
 Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
 Reported-by: kernel test robot <lkp@intel.com>
 Cc: Claudiu Beznea <claudiu.beznea@microchip.com>
 Cc: Michael Turquette <mturquette@baylibre.com>
 Cc: Stephen Boyd <sboyd@kernel.org>
 Cc: Eugen Hristev <eugen.hristev@microchip.com>
 Cc: linux-clk@vger.kernel.org
 Cc: linux-arm-kernel@lists.infradead.org
 Link: https://lore.kernel.org/r/20210819223237.20115-1-rdunlap@infradead.org
 Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 ---
 drivers/clk/at91/sama7g5.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)
 --- a/drivers/clk/at91/sama7g5.c
 +++ b/drivers/clk/at91/sama7g5.c
@@ -35,7 +35,7 @@ static DEFINE_SPINLOCK(pmc_pll_lock);
 static DEFINE_SPINLOCK(pmc_mck0_lock);
 static DEFINE_SPINLOCK(pmc_mckX_lock);
 -/**
 +/*
  * PLL clocks identifiers
  * @PLL_ID_CPU:		CPU PLL identifier
  * @PLL_ID_SYS:		System PLL identifier
@@ -56,7 +56,7 @@ enum pll_ids {
 	PLL_ID_MAX,
 };
 -/**
 +/*
  * PLL type identifiers
  * @PLL_TYPE_FRAC:	fractional PLL identifier
  * @PLL_TYPE_DIV:	divider PLL identifier
@@ -118,7 +118,7 @@ static const struct clk_pll_characterist
 	.output = pll_outputs,
 };
 -/**
 +/*
  * PLL clocks description
  * @n:		clock name
  * @p:		clock parent
@@ -285,7 +285,7 @@ static const struct {
 	},
 };
 -/**
 +/*
  * Master clock (MCK[1..4]) description
  * @n:			clock name
  * @ep:			extra parents names array
@@ -337,7 +337,7 @@ static const struct {
 	  .c = 1, },
 };
 -/**
 +/*
  * System clock description
  * @n:	clock name
  * @p:	clock parent name
@@ -361,7 +361,7 @@ static const struct {
 /* Mux table for programmable clocks. */
 static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, };
 -/**
 +/*
  * Peripheral clock description
  * @n:		clock name
  * @p:		clock parent name
@@ -449,7 +449,7 @@ static const struct {
 	{ .n = "uhphs_clk",	.p = "mck1", .id = 106, },
 };
 -/**
 +/*
  * Generic clock description
  * @n:			clock name
  * @pp:			PLL parents
--- a/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch
+++ b/target/linux/at91/patches-5.10/115-net-macb-add-userio-bits-as-platform-configuration.patch
@ -1,179 +0,0 @@
 From 89f37ac2780d113d3c17d329726c0e92a1400744 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 9 Dec 2020 15:03:32 +0200
 Subject: [PATCH 115/247] net: macb: add userio bits as platform configuration
 This is necessary for SAMA7G5 as it uses different values for
 PHY interface and also introduces hdfctlen bit.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb.h      | 10 +++++++++
 drivers/net/ethernet/cadence/macb_main.c | 28 ++++++++++++++++++++----
 2 files changed, 34 insertions(+), 4 deletions(-)
 --- a/drivers/net/ethernet/cadence/macb.h
 +++ b/drivers/net/ethernet/cadence/macb.h
@@ -1104,6 +1104,14 @@ struct macb_pm_data {
 	u32 usrio;
 };
 +struct macb_usrio_config {
 +	u32 mii;
 +	u32 rmii;
 +	u32 rgmii;
 +	u32 refclk;
 +	u32 hdfctlen;
 +};
 +
 struct macb_config {
 	u32			caps;
 	unsigned int		dma_burst_length;
@@ -1112,6 +1120,7 @@ struct macb_config {
 			    struct clk **rx_clk, struct clk **tsu_clk);
 	int	(*init)(struct platform_device *pdev);
 	int	jumbo_max_len;
 +	const struct macb_usrio_config *usrio;
 };
 struct tsu_incr {
@@ -1244,6 +1253,7 @@ struct macb {
 	u32	rx_intr_mask;
 	struct macb_pm_data pm_data;
 +	const struct macb_usrio_config *usrio;
 };
 #ifdef CONFIG_MACB_USE_HWSTAMP
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -3828,15 +3828,15 @@ static int macb_init(struct platform_dev
 	if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
 		val = 0;
 		if (phy_interface_mode_is_rgmii(bp->phy_interface))
 -			val = GEM_BIT(RGMII);
 +			val = bp->usrio->rgmii;
 		else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
 			 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
 -			val = MACB_BIT(RMII);
 +			val = bp->usrio->rmii;
 		else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
 -			val = MACB_BIT(MII);
 +			val = bp->usrio->mii;
 		if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
 -			val |= MACB_BIT(CLKEN);
 +			val |= bp->usrio->refclk;
 		macb_or_gem_writel(bp, USRIO, val);
 	}
@@ -4354,6 +4354,13 @@ static int fu540_c000_init(struct platfo
 	return macb_init(pdev);
 }
 +static const struct macb_usrio_config macb_default_usrio = {
 +	.mii = MACB_BIT(MII),
 +	.rmii = MACB_BIT(RMII),
 +	.rgmii = GEM_BIT(RGMII),
 +	.refclk = MACB_BIT(CLKEN),
 +};
 +
 static const struct macb_config fu540_c000_config = {
 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
 		MACB_CAPS_GEM_HAS_PTP,
@@ -4361,12 +4368,14 @@ static const struct macb_config fu540_c0
 	.clk_init = fu540_c000_clk_init,
 	.init = fu540_c000_init,
 	.jumbo_max_len = 10240,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config at91sam9260_config = {
 	.caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config sama5d3macb_config = {
@@ -4374,6 +4383,7 @@ static const struct macb_config sama5d3m
 	      | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config pc302gem_config = {
@@ -4381,6 +4391,7 @@ static const struct macb_config pc302gem
 	.dma_burst_length = 16,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config sama5d2_config = {
@@ -4388,6 +4399,7 @@ static const struct macb_config sama5d2_
 	.dma_burst_length = 16,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config sama5d3_config = {
@@ -4397,6 +4409,7 @@ static const struct macb_config sama5d3_
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 	.jumbo_max_len = 10240,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config sama5d4_config = {
@@ -4404,18 +4417,21 @@ static const struct macb_config sama5d4_
 	.dma_burst_length = 4,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config emac_config = {
 	.caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
 	.clk_init = at91ether_clk_init,
 	.init = at91ether_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config np4_config = {
 	.caps = MACB_CAPS_USRIO_DISABLED,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config zynqmp_config = {
@@ -4426,6 +4442,7 @@ static const struct macb_config zynqmp_c
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 	.jumbo_max_len = 10240,
 +	.usrio = &macb_default_usrio,
 };
 static const struct macb_config zynq_config = {
@@ -4434,6 +4451,7 @@ static const struct macb_config zynq_con
 	.dma_burst_length = 16,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 };
 static const struct of_device_id macb_dt_ids[] = {
@@ -4554,6 +4572,8 @@ static int macb_probe(struct platform_de
 		bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
 	device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
 +	bp->usrio = macb_config->usrio;
 +
 	spin_lock_init(&bp->lock);
 	/* setup capabilities */
--- a/target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch
+++ b/target/linux/at91/patches-5.10/116-net-macb-add-capability-to-not-set-the-clock-rate.patch
@ -1,85 +0,0 @@
 From 1b15259551b701f416aa024050a2e619860bd0d8 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 9 Dec 2020 15:03:33 +0200
 Subject: [PATCH 116/247] net: macb: add capability to not set the clock rate
 SAMA7G5's ethernet IPs TX clock could be provided by its generic clock or
 by the external clock provided by the PHY. The internal IP logic divides
 properly this clock depending on the link speed. The patch adds a new
 capability so that macb_set_tx_clock() to not be called for IPs having
 this capability (the clock rate, in case of generic clock, is set at the
 boot time via device tree and the driver only enables it).
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb.h      |  1 +
 drivers/net/ethernet/cadence/macb_main.c | 18 +++++++++---------
 2 files changed, 10 insertions(+), 9 deletions(-)
 --- a/drivers/net/ethernet/cadence/macb.h
 +++ b/drivers/net/ethernet/cadence/macb.h
@@ -658,6 +658,7 @@
 #define MACB_CAPS_GEM_HAS_PTP			0x00000040
 #define MACB_CAPS_BD_RD_PREFETCH		0x00000080
 #define MACB_CAPS_NEEDS_RSTONUBR		0x00000100
 +#define MACB_CAPS_CLK_HW_CHG			0x04000000
 #define MACB_CAPS_MACB_IS_EMAC			0x08000000
 #define MACB_CAPS_FIFO_MODE			0x10000000
 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE	0x20000000
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -457,15 +457,14 @@ static void macb_init_buffers(struct mac
 /**
  * macb_set_tx_clk() - Set a clock to a new frequency
 - * @clk:	Pointer to the clock to change
 + * @bp:		pointer to struct macb
  * @speed:	New frequency in Hz
 - * @dev:	Pointer to the struct net_device
  */
 -static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
 +static void macb_set_tx_clk(struct macb *bp, int speed)
 {
 	long ferr, rate, rate_rounded;
 -	if (!clk)
 +	if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
 		return;
 	switch (speed) {
@@ -482,7 +481,7 @@ static void macb_set_tx_clk(struct clk *
 		return;
 	}
 -	rate_rounded = clk_round_rate(clk, rate);
 +	rate_rounded = clk_round_rate(bp->tx_clk, rate);
 	if (rate_rounded < 0)
 		return;
@@ -492,11 +491,12 @@ static void macb_set_tx_clk(struct clk *
 	ferr = abs(rate_rounded - rate);
 	ferr = DIV_ROUND_UP(ferr, rate / 100000);
 	if (ferr > 5)
 -		netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
 +		netdev_warn(bp->dev,
 +			    "unable to generate target frequency: %ld Hz\n",
 			    rate);
 -	if (clk_set_rate(clk, rate_rounded))
 -		netdev_err(dev, "adjusting tx_clk failed.\n");
 +	if (clk_set_rate(bp->tx_clk, rate_rounded))
 +		netdev_err(bp->dev, "adjusting tx_clk failed.\n");
 }
 static void macb_validate(struct phylink_config *config,
@@ -649,7 +649,7 @@ static void macb_mac_link_up(struct phyl
 		if (rx_pause)
 			ctrl |= MACB_BIT(PAE);
 -		macb_set_tx_clk(bp->tx_clk, speed, ndev);
 +		macb_set_tx_clk(bp, speed);
 		/* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
 		 * cleared the pipeline and control registers.
--- a/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch
+++ b/target/linux/at91/patches-5.10/117-net-macb-add-function-to-disable-all-macb-clocks.patch
@ -1,82 +0,0 @@
 From 935d9aae15ee245a1bc6e322cbef02566a8996cc Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 9 Dec 2020 15:03:34 +0200
 Subject: [PATCH 117/247] net: macb: add function to disable all macb clocks
 Add function to disable all macb clocks.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Suggested-by: Andrew Lunn <andrew@lunn.ch>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb_main.c | 38 +++++++++++++-----------
 1 file changed, 21 insertions(+), 17 deletions(-)
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -3603,6 +3603,20 @@ static void macb_probe_queues(void __iom
 	*num_queues = hweight32(*queue_mask);
 }
 +static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
 +			      struct clk *rx_clk, struct clk *tsu_clk)
 +{
 +	struct clk_bulk_data clks[] = {
 +		{ .clk = tsu_clk, },
 +		{ .clk = rx_clk, },
 +		{ .clk = pclk, },
 +		{ .clk = hclk, },
 +		{ .clk = tx_clk },
 +	};
 +
 +	clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
 +}
 +
 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
 			 struct clk **hclk, struct clk **tx_clk,
 			 struct clk **rx_clk, struct clk **tsu_clk)
@@ -4665,11 +4679,7 @@ err_out_free_netdev:
 	free_netdev(dev);
 err_disable_clocks:
 -	clk_disable_unprepare(tx_clk);
 -	clk_disable_unprepare(hclk);
 -	clk_disable_unprepare(pclk);
 -	clk_disable_unprepare(rx_clk);
 -	clk_disable_unprepare(tsu_clk);
 +	macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
 	pm_runtime_disable(&pdev->dev);
 	pm_runtime_set_suspended(&pdev->dev);
 	pm_runtime_dont_use_autosuspend(&pdev->dev);
@@ -4694,11 +4704,8 @@ static int macb_remove(struct platform_d
 		pm_runtime_disable(&pdev->dev);
 		pm_runtime_dont_use_autosuspend(&pdev->dev);
 		if (!pm_runtime_suspended(&pdev->dev)) {
 -			clk_disable_unprepare(bp->tx_clk);
 -			clk_disable_unprepare(bp->hclk);
 -			clk_disable_unprepare(bp->pclk);
 -			clk_disable_unprepare(bp->rx_clk);
 -			clk_disable_unprepare(bp->tsu_clk);
 +			macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
 +					  bp->rx_clk, bp->tsu_clk);
 			pm_runtime_set_suspended(&pdev->dev);
 		}
 		phylink_destroy(bp->phylink);
@@ -4877,13 +4884,10 @@ static int __maybe_unused macb_runtime_s
 	struct net_device *netdev = dev_get_drvdata(dev);
 	struct macb *bp = netdev_priv(netdev);
 -	if (!(device_may_wakeup(dev))) {
 -		clk_disable_unprepare(bp->tx_clk);
 -		clk_disable_unprepare(bp->hclk);
 -		clk_disable_unprepare(bp->pclk);
 -		clk_disable_unprepare(bp->rx_clk);
 -	}
 -	clk_disable_unprepare(bp->tsu_clk);
 +	if (!(device_may_wakeup(dev)))
 +		macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
 +	else
 +		macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
 	return 0;
 }
--- a/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch
+++ b/target/linux/at91/patches-5.10/118-net-macb-unprepare-clocks-in-case-of-failure.patch
@ -1,60 +0,0 @@
 From 9692c07ee8bf8f68b74d553d861d092e33264781 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 9 Dec 2020 15:03:35 +0200
 Subject: [PATCH 118/247] net: macb: unprepare clocks in case of failure
 Unprepare clocks in case of any failure in fu540_c000_clk_init().
 Fixes: c218ad559020 ("macb: Add support for SiFive FU540-C000")
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb_main.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4335,8 +4335,10 @@ static int fu540_c000_clk_init(struct pl
 		return err;
 	mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
 -	if (!mgmt)
 -		return -ENOMEM;
 +	if (!mgmt) {
 +		err = -ENOMEM;
 +		goto err_disable_clks;
 +	}
 	init.name = "sifive-gemgxl-mgmt";
 	init.ops = &fu540_c000_ops;
@@ -4347,16 +4349,26 @@ static int fu540_c000_clk_init(struct pl
 	mgmt->hw.init = &init;
 	*tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
 -	if (IS_ERR(*tx_clk))
 -		return PTR_ERR(*tx_clk);
 +	if (IS_ERR(*tx_clk)) {
 +		err = PTR_ERR(*tx_clk);
 +		goto err_disable_clks;
 +	}
 	err = clk_prepare_enable(*tx_clk);
 -	if (err)
 +	if (err) {
 		dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
 -	else
 +		*tx_clk = NULL;
 +		goto err_disable_clks;
 +	} else {
 		dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
 +	}
 	return 0;
 +
 +err_disable_clks:
 +	macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
 +
 +	return err;
 }
 static int fu540_c000_init(struct platform_device *pdev)
--- a/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch
+++ b/target/linux/at91/patches-5.10/119-net-macb-add-support-for-sama7g5-gem-interface.patch
@ -1,54 +0,0 @@
 From 0085cd8576ceeaddeedf973b939b41ba96e3f77c Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 9 Dec 2020 15:03:38 +0200
 Subject: [PATCH 119/247] net: macb: add support for sama7g5 gem interface
 Add support for SAMA7G5 gigabit ethernet interface.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb_main.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4387,6 +4387,14 @@ static const struct macb_usrio_config ma
 	.refclk = MACB_BIT(CLKEN),
 };
 +static const struct macb_usrio_config sama7g5_usrio = {
 +	.mii = 0,
 +	.rmii = 1,
 +	.rgmii = 2,
 +	.refclk = BIT(2),
 +	.hdfctlen = BIT(6),
 +};
 +
 static const struct macb_config fu540_c000_config = {
 	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
 		MACB_CAPS_GEM_HAS_PTP,
@@ -4480,6 +4488,14 @@ static const struct macb_config zynq_con
 	.usrio = &macb_default_usrio,
 };
 +static const struct macb_config sama7g5_gem_config = {
 +	.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG,
 +	.dma_burst_length = 16,
 +	.clk_init = macb_clk_init,
 +	.init = macb_init,
 +	.usrio = &sama7g5_usrio,
 +};
 +
 static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "cdns,at32ap7000-macb" },
 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
@@ -4497,6 +4513,7 @@ static const struct of_device_id macb_dt
 	{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
 	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
 	{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
 +	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, macb_dt_ids);
--- a/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch
+++ b/target/linux/at91/patches-5.10/120-net-macb-add-support-for-sama7g5-emac-interface.patch
@ -1,39 +0,0 @@
 From a42f90357cfcfcf5cdade4594ad79a1eae633a9f Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 9 Dec 2020 15:03:39 +0200
 Subject: [PATCH 120/247] net: macb: add support for sama7g5 emac interface
 Add support for SAMA7G5 10/100Mbps interface.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb_main.c | 9 +++++++++
 1 file changed, 9 insertions(+)
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4496,6 +4496,14 @@ static const struct macb_config sama7g5_
 	.usrio = &sama7g5_usrio,
 };
 +static const struct macb_config sama7g5_emac_config = {
 +	.caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_USRIO_HAS_CLKEN,
 +	.dma_burst_length = 16,
 +	.clk_init = macb_clk_init,
 +	.init = macb_init,
 +	.usrio = &sama7g5_usrio,
 +};
 +
 static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "cdns,at32ap7000-macb" },
 	{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
@@ -4514,6 +4522,7 @@ static const struct of_device_id macb_dt
 	{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
 	{ .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
 	{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
 +	{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, macb_dt_ids);
--- a/target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch
+++ b/target/linux/at91/patches-5.10/121-ASoC-pcm5102a-Make-codec-selectable.patch
@ -1,28 +0,0 @@
 From 5ac0e1f5577b266543756521b1a749003b0f3686 Mon Sep 17 00:00:00 2001
 From: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Date: Mon, 12 Oct 2020 17:19:11 +0300
 Subject: [PATCH 121/247] ASoC: pcm5102a: Make codec selectable
 The TI PCM5102A codec driver can be used with the generic sound card
 drivers, so it should be selectable. For example, with the addition
 of #sound-dai-cells = <0> property in DT, it can be used with simple/graph
 card drivers.
 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20201012141911.3150996-1-codrin.ciubotariu@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/codecs/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/sound/soc/codecs/Kconfig
 +++ b/sound/soc/codecs/Kconfig
@@ -1007,7 +1007,7 @@ config SND_SOC_PCM3168A_SPI
 	select REGMAP_SPI
 config SND_SOC_PCM5102A
 -	tristate
 +	tristate "Texas Instruments PCM5102A CODEC"
 config SND_SOC_PCM512x
 	tristate
--- a/target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch
+++ b/target/linux/at91/patches-5.10/122-ASoC-atmel-i2s-do-not-warn-if-muxclk-is-missing.patch
@ -1,30 +0,0 @@
 From f4389949bf422fe04775c17b833100fa0e95ea68 Mon Sep 17 00:00:00 2001
 From: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Date: Tue, 3 Nov 2020 12:05:54 +0200
 Subject: [PATCH 122/247] ASoC: atmel-i2s: do not warn if muxclk is missing
 Besides the fact that muxclk is optional, muxclk can be set using
 assigned-clocks, removing the need to set it in driver. The warning is
 thus unneeded, so we can transform it in a debug print, eventually to just
 reflect that muxclk was not set by the driver.
 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20201103100554.1307190-1-codrin.ciubotariu@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/atmel-i2s.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 --- a/sound/soc/atmel/atmel-i2s.c
 +++ b/sound/soc/atmel/atmel-i2s.c
@@ -581,8 +581,8 @@ static int atmel_i2s_sama5d2_mck_init(st
 		err = PTR_ERR(muxclk);
 		if (err == -EPROBE_DEFER)
 			return -EPROBE_DEFER;
 -		dev_warn(dev->dev,
 -			 "failed to get the I2S clock control: %d\n", err);
 +		dev_dbg(dev->dev,
 +			"failed to get the I2S clock control: %d\n", err);
 		return 0;
 	}
--- a/target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch
+++ b/target/linux/at91/patches-5.10/123-regulator-mcp16502-add-linear_min_sel.patch
@ -1,25 +0,0 @@
 From f5a73f3bb600b96b6149f2115360e1d0d51fbac4 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 13 Nov 2020 17:21:07 +0200
 Subject: [PATCH 123/247] regulator: mcp16502: add linear_min_sel
 Selectors b/w zero and VDD_LOW_SEL are not valid. Use linear_min_sel.
 Fixes: 919261c03e7ca ("regulator: mcp16502: add regulator driver for MCP16502")
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605280870-32432-4-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/mcp16502.c | 1 +
 1 file changed, 1 insertion(+)
 --- a/drivers/regulator/mcp16502.c
 +++ b/drivers/regulator/mcp16502.c
@@ -93,6 +93,7 @@ static unsigned int mcp16502_of_map_mode
 		.owner			= THIS_MODULE,			\
 		.n_voltages		= MCP16502_VSEL + 1,		\
 		.linear_ranges		= _ranges,			\
 +		.linear_min_sel		= VDD_LOW_SEL,			\
 		.n_linear_ranges	= ARRAY_SIZE(_ranges),		\
 		.of_match		= of_match_ptr(_name),		\
 		.of_map_mode		= mcp16502_of_map_mode,		\
--- a/target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch
+++ b/target/linux/at91/patches-5.10/124-regulator-mcp16502-adapt-for-get-set-on-other-regist.patch
@ -1,117 +0,0 @@
 From 5295f4c122258a11fb6012b7e043248e681db5a2 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 13 Nov 2020 17:21:08 +0200
 Subject: [PATCH 124/247] regulator: mcp16502: adapt for get/set on other
 registers
 MCP16502 have multiple registers for each regulator (as described
 in enum mcp16502_reg). Adapt the code to be able to get/set all these
 registers. This is necessary for the following commits.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605280870-32432-5-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/mcp16502.c | 43 ++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 16 deletions(-)
 --- a/drivers/regulator/mcp16502.c
 +++ b/drivers/regulator/mcp16502.c
@@ -54,13 +54,9 @@
  * This function is useful for iterating over all regulators and accessing their
  * registers in a generic way or accessing a regulator device by its id.
  */
 -#define MCP16502_BASE(i) (((i) + 1) << 4)
 +#define MCP16502_REG_BASE(i, r) ((((i) + 1) << 4) + MCP16502_REG_##r)
 #define MCP16502_STAT_BASE(i) ((i) + 5)
 -#define MCP16502_OFFSET_MODE_A 0
 -#define MCP16502_OFFSET_MODE_LPM 1
 -#define MCP16502_OFFSET_MODE_HIB 2
 -
 #define MCP16502_OPMODE_ACTIVE REGULATOR_MODE_NORMAL
 #define MCP16502_OPMODE_LPM REGULATOR_MODE_IDLE
 #define MCP16502_OPMODE_HIB REGULATOR_MODE_STANDBY
@@ -75,6 +71,23 @@
 #define MCP16502_MIN_REG 0x0
 #define MCP16502_MAX_REG 0x65
 +/**
 + * enum mcp16502_reg - MCP16502 regulators's registers
 + * @MCP16502_REG_A: active state register
 + * @MCP16502_REG_LPM: low power mode state register
 + * @MCP16502_REG_HIB: hibernate state register
 + * @MCP16502_REG_SEQ: startup sequence register
 + * @MCP16502_REG_CFG: configuration register
 + */
 +enum mcp16502_reg {
 +	MCP16502_REG_A,
 +	MCP16502_REG_LPM,
 +	MCP16502_REG_HIB,
 +	MCP16502_REG_HPM,
 +	MCP16502_REG_SEQ,
 +	MCP16502_REG_CFG,
 +};
 +
 static unsigned int mcp16502_of_map_mode(unsigned int mode)
 {
 	if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)
@@ -144,22 +157,20 @@ static void mcp16502_gpio_set_mode(struc
 }
 /*
 - * mcp16502_get_reg() - get the PMIC's configuration register for opmode
 + * mcp16502_get_reg() - get the PMIC's state configuration register for opmode
  *
  * @rdev: the regulator whose register we are searching
  * @opmode: the PMIC's operating mode ACTIVE, Low-power, Hibernate
  */
 -static int mcp16502_get_reg(struct regulator_dev *rdev, int opmode)
 +static int mcp16502_get_state_reg(struct regulator_dev *rdev, int opmode)
 {
 -	int reg = MCP16502_BASE(rdev_get_id(rdev));
 -
 	switch (opmode) {
 	case MCP16502_OPMODE_ACTIVE:
 -		return reg + MCP16502_OFFSET_MODE_A;
 +		return MCP16502_REG_BASE(rdev_get_id(rdev), A);
 	case MCP16502_OPMODE_LPM:
 -		return reg + MCP16502_OFFSET_MODE_LPM;
 +		return MCP16502_REG_BASE(rdev_get_id(rdev), LPM);
 	case MCP16502_OPMODE_HIB:
 -		return reg + MCP16502_OFFSET_MODE_HIB;
 +		return MCP16502_REG_BASE(rdev_get_id(rdev), HIB);
 	default:
 		return -EINVAL;
 	}
@@ -179,7 +190,7 @@ static unsigned int mcp16502_get_mode(st
 	unsigned int val;
 	int ret, reg;
 -	reg = mcp16502_get_reg(rdev, MCP16502_OPMODE_ACTIVE);
 +	reg = mcp16502_get_state_reg(rdev, MCP16502_OPMODE_ACTIVE);
 	if (reg < 0)
 		return reg;
@@ -210,7 +221,7 @@ static int _mcp16502_set_mode(struct reg
 	int val;
 	int reg;
 -	reg = mcp16502_get_reg(rdev, op_mode);
 +	reg = mcp16502_get_state_reg(rdev, op_mode);
 	if (reg < 0)
 		return reg;
@@ -269,10 +280,10 @@ static int mcp16502_suspend_get_target_r
 {
 	switch (pm_suspend_target_state) {
 	case PM_SUSPEND_STANDBY:
 -		return mcp16502_get_reg(rdev, MCP16502_OPMODE_LPM);
 +		return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_LPM);
 	case PM_SUSPEND_ON:
 	case PM_SUSPEND_MEM:
 -		return mcp16502_get_reg(rdev, MCP16502_OPMODE_HIB);
 +		return mcp16502_get_state_reg(rdev, MCP16502_OPMODE_HIB);
 	default:
 		dev_err(&rdev->dev, "invalid suspend target: %d\n",
 			pm_suspend_target_state);
--- a/target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch
+++ b/target/linux/at91/patches-5.10/125-regulator-mcp16502-add-support-for-ramp-delay.patch
@ -1,141 +0,0 @@
 From 7f13433e11a3c88f1fd6417c4c5e5a6c98370b9a Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 13 Nov 2020 17:21:09 +0200
 Subject: [PATCH 125/247] regulator: mcp16502: add support for ramp delay
 MCP16502 have configurable ramp delay support (via DVSR bits in
 regulators' CFG register).
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605280870-32432-6-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/mcp16502.c | 89 +++++++++++++++++++++++++++++++++++-
 1 file changed, 87 insertions(+), 2 deletions(-)
 --- a/drivers/regulator/mcp16502.c
 +++ b/drivers/regulator/mcp16502.c
@@ -22,8 +22,9 @@
 #define VDD_LOW_SEL 0x0D
 #define VDD_HIGH_SEL 0x3F
 -#define MCP16502_FLT BIT(7)
 -#define MCP16502_ENS BIT(0)
 +#define MCP16502_FLT		BIT(7)
 +#define MCP16502_DVSR		GENMASK(3, 2)
 +#define MCP16502_ENS		BIT(0)
 /*
  * The PMIC has four sets of registers corresponding to four power modes:
@@ -88,6 +89,12 @@ enum mcp16502_reg {
 	MCP16502_REG_CFG,
 };
 +/* Ramp delay (uV/us) for buck1, ldo1, ldo2. */
 +static const int mcp16502_ramp_b1l12[] = { 6250, 3125, 2083, 1563 };
 +
 +/* Ramp delay (uV/us) for buck2, buck3, buck4. */
 +static const int mcp16502_ramp_b234[] = { 3125, 1563, 1042, 781 };
 +
 static unsigned int mcp16502_of_map_mode(unsigned int mode)
 {
 	if (mode == REGULATOR_MODE_NORMAL || mode == REGULATOR_MODE_IDLE)
@@ -271,6 +278,80 @@ static int mcp16502_get_status(struct re
 	return REGULATOR_STATUS_UNDEFINED;
 }
 +static int mcp16502_set_voltage_time_sel(struct regulator_dev *rdev,
 +					 unsigned int old_sel,
 +					 unsigned int new_sel)
 +{
 +	static const u8 us_ramp[] = { 8, 16, 24, 32 };
 +	int id = rdev_get_id(rdev);
 +	unsigned int uV_delta, val;
 +	int ret;
 +
 +	ret = regmap_read(rdev->regmap, MCP16502_REG_BASE(id, CFG), &val);
 +	if (ret)
 +		return ret;
 +
 +	val = (val & MCP16502_DVSR) >> 2;
 +	uV_delta = abs(new_sel * rdev->desc->linear_ranges->step -
 +		       old_sel * rdev->desc->linear_ranges->step);
 +	switch (id) {
 +	case BUCK1:
 +	case LDO1:
 +	case LDO2:
 +		ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val],
 +					mcp16502_ramp_b1l12[val]);
 +		break;
 +
 +	case BUCK2:
 +	case BUCK3:
 +	case BUCK4:
 +		ret = DIV_ROUND_CLOSEST(uV_delta * us_ramp[val],
 +					mcp16502_ramp_b234[val]);
 +		break;
 +
 +	default:
 +		return -EINVAL;
 +	}
 +
 +	return ret;
 +}
 +
 +static int mcp16502_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
 +{
 +	const int *ramp;
 +	int id = rdev_get_id(rdev);
 +	unsigned int i, size;
 +
 +	switch (id) {
 +	case BUCK1:
 +	case LDO1:
 +	case LDO2:
 +		ramp = mcp16502_ramp_b1l12;
 +		size = ARRAY_SIZE(mcp16502_ramp_b1l12);
 +		break;
 +
 +	case BUCK2:
 +	case BUCK3:
 +	case BUCK4:
 +		ramp = mcp16502_ramp_b234;
 +		size = ARRAY_SIZE(mcp16502_ramp_b234);
 +		break;
 +
 +	default:
 +		return -EINVAL;
 +	}
 +
 +	for (i = 0; i < size; i++) {
 +		if (ramp[i] == ramp_delay)
 +			break;
 +	}
 +	if (i == size)
 +		return -EINVAL;
 +
 +	return regmap_update_bits(rdev->regmap, MCP16502_REG_BASE(id, CFG),
 +				  MCP16502_DVSR, (i << 2));
 +}
 +
 #ifdef CONFIG_SUSPEND
 /*
  * mcp16502_suspend_get_target_reg() - get the reg of the target suspend PMIC
@@ -365,6 +446,8 @@ static const struct regulator_ops mcp165
 	.disable			= regulator_disable_regmap,
 	.is_enabled			= regulator_is_enabled_regmap,
 	.get_status			= mcp16502_get_status,
 +	.set_voltage_time_sel		= mcp16502_set_voltage_time_sel,
 +	.set_ramp_delay			= mcp16502_set_ramp_delay,
 	.set_mode			= mcp16502_set_mode,
 	.get_mode			= mcp16502_get_mode,
@@ -389,6 +472,8 @@ static const struct regulator_ops mcp165
 	.disable			= regulator_disable_regmap,
 	.is_enabled			= regulator_is_enabled_regmap,
 	.get_status			= mcp16502_get_status,
 +	.set_voltage_time_sel		= mcp16502_set_voltage_time_sel,
 +	.set_ramp_delay			= mcp16502_set_ramp_delay,
 #ifdef CONFIG_SUSPEND
 	.set_suspend_voltage		= mcp16502_set_suspend_voltage,
--- a/target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch
+++ b/target/linux/at91/patches-5.10/126-regulator-mcp16502-remove-void-documentation-of-stru.patch
@ -1,27 +0,0 @@
 From 8dcbcb052f682478dcbfa7fc9abdd909e1deab87 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 13 Nov 2020 17:21:10 +0200
 Subject: [PATCH 126/247] regulator: mcp16502: remove void documentation of
 struct mcp16502
 struct mcp16502 has no members called rdev or rmap. Remove the
 documentation.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605280870-32432-7-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/mcp16502.c | 2 --
 1 file changed, 2 deletions(-)
 --- a/drivers/regulator/mcp16502.c
 +++ b/drivers/regulator/mcp16502.c
@@ -135,8 +135,6 @@ enum {
 /*
  * struct mcp16502 - PMIC representation
 - * @rdev: the regulators belonging to this chip
 - * @rmap: regmap to be used for I2C communication
  * @lpm: LPM GPIO descriptor
  */
 struct mcp16502 {
--- a/target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch
+++ b/target/linux/at91/patches-5.10/127-regulator-core-validate-selector-against-linear_min_.patch
@ -1,64 +0,0 @@
 From 3aee4f22ed0a22d3d6d22fc49812c03d876c7637 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 13 Nov 2020 17:21:05 +0200
 Subject: [PATCH 127/247] regulator: core: validate selector against
 linear_min_sel
 There are regulators who's min selector is not zero. Selectors loops
 (looping b/w zero and regulator::desc::n_voltages) might throw errors
 because invalid selectors are used (lower than
 regulator::desc::linear_min_sel). For this situations validate selectors
 against regulator::desc::linear_min_sel.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605280870-32432-2-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/core.c    | 9 +++++++--
 drivers/regulator/helpers.c | 3 ++-
 2 files changed, 9 insertions(+), 3 deletions(-)
 --- a/drivers/regulator/core.c
 +++ b/drivers/regulator/core.c
@@ -3000,7 +3000,8 @@ static int _regulator_list_voltage(struc
 		return rdev->desc->fixed_uV;
 	if (ops->list_voltage) {
 -		if (selector >= rdev->desc->n_voltages)
 +		if (selector >= rdev->desc->n_voltages ||
 +		    selector < rdev->desc->linear_min_sel)
 			return -EINVAL;
 		if (lock)
 			regulator_lock(rdev);
@@ -3151,7 +3152,8 @@ int regulator_list_hardware_vsel(struct
 	struct regulator_dev *rdev = regulator->rdev;
 	const struct regulator_ops *ops = rdev->desc->ops;
 -	if (selector >= rdev->desc->n_voltages)
 +	if (selector >= rdev->desc->n_voltages ||
 +	    selector < rdev->desc->linear_min_sel)
 		return -EINVAL;
 	if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap)
 		return -EOPNOTSUPP;
@@ -4074,6 +4076,9 @@ int regulator_set_voltage_time(struct re
 	for (i = 0; i < rdev->desc->n_voltages; i++) {
 		/* We only look for exact voltage matches here */
 +		if (i < rdev->desc->linear_min_sel)
 +			continue;
 +
 		voltage = regulator_list_voltage(regulator, i);
 		if (voltage < 0)
 			return -EINVAL;
 --- a/drivers/regulator/helpers.c
 +++ b/drivers/regulator/helpers.c
@@ -647,7 +647,8 @@ int regulator_list_voltage_table(struct
 		return -EINVAL;
 	}
 -	if (selector >= rdev->desc->n_voltages)
 +	if (selector >= rdev->desc->n_voltages ||
 +	    selector < rdev->desc->linear_min_sel)
 		return -EINVAL;
 	return rdev->desc->volt_table[selector];
--- a/target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch
+++ b/target/linux/at91/patches-5.10/128-regulator-core-do-not-continue-if-selector-match.patch
@ -1,26 +0,0 @@
 From 42b56e8bd343f34d5f2a601d8a8a05d8c861c08c Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 13 Nov 2020 19:56:04 +0200
 Subject: [PATCH 128/247] regulator: core: do not continue if selector match
 Do not continue if selector has already been located.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1605290164-11556-1-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/core.c | 3 +++
 1 file changed, 3 insertions(+)
 --- a/drivers/regulator/core.c
 +++ b/drivers/regulator/core.c
@@ -4079,6 +4079,9 @@ int regulator_set_voltage_time(struct re
 		if (i < rdev->desc->linear_min_sel)
 			continue;
 +		if (old_sel >= 0 && new_sel >= 0)
 +			break;
 +
 		voltage = regulator_list_voltage(regulator, i);
 		if (voltage < 0)
 			return -EINVAL;
--- a/target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch
+++ b/target/linux/at91/patches-5.10/129-regulator-core-return-zero-for-selectors-lower-than-.patch
@ -1,64 +0,0 @@
 From 0e933ffc049a0e181b5a6c3af1933976d6959ba9 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 25 Nov 2020 19:25:47 +0200
 Subject: [PATCH 129/247] regulator: core: return zero for selectors lower than
 linear_min_sel
 Selectors lower than linear_min_sel should not be considered invalid.
 Thus return zero in case _regulator_list_voltage(),
 regulator_list_hardware_vsel() or regulator_list_voltage_table()
 receives such selectors as argument.
 Fixes: bdcd1177578c ("regulator: core: validate selector against linear_min_sel")
 Reported-by: Jon Hunter <jonathanh@nvidia.com>
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1606325147-606-1-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/core.c    | 10 ++++++----
 drivers/regulator/helpers.c |  5 +++--
 2 files changed, 9 insertions(+), 6 deletions(-)
 --- a/drivers/regulator/core.c
 +++ b/drivers/regulator/core.c
@@ -3000,9 +3000,10 @@ static int _regulator_list_voltage(struc
 		return rdev->desc->fixed_uV;
 	if (ops->list_voltage) {
 -		if (selector >= rdev->desc->n_voltages ||
 -		    selector < rdev->desc->linear_min_sel)
 +		if (selector >= rdev->desc->n_voltages)
 			return -EINVAL;
 +		if (selector < rdev->desc->linear_min_sel)
 +			return 0;
 		if (lock)
 			regulator_lock(rdev);
 		ret = ops->list_voltage(rdev, selector);
@@ -3152,9 +3153,10 @@ int regulator_list_hardware_vsel(struct
 	struct regulator_dev *rdev = regulator->rdev;
 	const struct regulator_ops *ops = rdev->desc->ops;
 -	if (selector >= rdev->desc->n_voltages ||
 -	    selector < rdev->desc->linear_min_sel)
 +	if (selector >= rdev->desc->n_voltages)
 		return -EINVAL;
 +	if (selector < rdev->desc->linear_min_sel)
 +		return 0;
 	if (ops->set_voltage_sel != regulator_set_voltage_sel_regmap)
 		return -EOPNOTSUPP;
 --- a/drivers/regulator/helpers.c
 +++ b/drivers/regulator/helpers.c
@@ -647,9 +647,10 @@ int regulator_list_voltage_table(struct
 		return -EINVAL;
 	}
 -	if (selector >= rdev->desc->n_voltages ||
 -	    selector < rdev->desc->linear_min_sel)
 +	if (selector >= rdev->desc->n_voltages)
 		return -EINVAL;
 +	if (selector < rdev->desc->linear_min_sel)
 +		return 0;
 	return rdev->desc->volt_table[selector];
 }
--- a/target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch
+++ b/target/linux/at91/patches-5.10/130-regulator-mcp16502-lpm-pin-can-be-optional-on-some-p.patch
@ -1,30 +0,0 @@
 From 763fe72f607d4e929d2c710c88e5c6978dd6ad97 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Thu, 7 Jan 2021 16:15:26 +0200
 Subject: [PATCH 130/247] regulator: mcp16502: lpm pin can be optional on some
 platforms
 On some platform (e.g. SAMA7G5) LPM pin should be optional as it can
 be controlled explicitly (via shutdown controller registers) in the
 platform specific power saving code to decrease the power consumption
 while suspended as this SoC pin may be connected to other devices that
 could take power saving actions based on its value.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Link: https://lore.kernel.org/r/1610028927-9842-3-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 drivers/regulator/mcp16502.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/drivers/regulator/mcp16502.c
 +++ b/drivers/regulator/mcp16502.c
@@ -550,7 +550,7 @@ static int mcp16502_probe(struct i2c_cli
 	config.regmap = rmap;
 	config.driver_data = mcp;
 -	mcp->lpm = devm_gpiod_get(dev, "lpm", GPIOD_OUT_LOW);
 +	mcp->lpm = devm_gpiod_get_optional(dev, "lpm", GPIOD_OUT_LOW);
 	if (IS_ERR(mcp->lpm)) {
 		dev_err(dev, "failed to get lpm pin: %ld\n", PTR_ERR(mcp->lpm));
 		return PTR_ERR(mcp->lpm);
--- a/target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch
+++ b/target/linux/at91/patches-5.10/131-pinctrl-at91-pio4-add-support-for-fewer-lines-on-las.patch
@ -1,70 +0,0 @@
 From 7cb1dad7a7dfe4cfe55ebe86930dd6aef0de66b4 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Fri, 13 Nov 2020 15:24:29 +0200
 Subject: [PATCH 131/247] pinctrl: at91-pio4: add support for fewer lines on
 last PIO bank
 Some products, like sama7g5, do not have a full last bank of PIO lines.
 In this case for example, sama7g5 only has 8 lines for the PE bank.
 PA0-31, PB0-31, PC0-31, PD0-31, PE0-7, in total 136 lines.
 To cope with this situation, added a data attribute that is product dependent,
 to specify the number of lines of the last bank.
 In case this number is different from the macro ATMEL_PIO_NPINS_PER_BANK,
 adjust the total number of lines accordingly.
 This will avoid advertising 160 lines instead of the actual 136, as this
 product supports, and to avoid reading/writing to invalid register addresses.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
 Link: https://lore.kernel.org/r/20201113132429.420940-1-eugen.hristev@microchip.com
 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 ---
 drivers/pinctrl/pinctrl-at91-pio4.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)
 --- a/drivers/pinctrl/pinctrl-at91-pio4.c
 +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -71,8 +71,15 @@
 /* Custom pinconf parameters */
 #define ATMEL_PIN_CONFIG_DRIVE_STRENGTH	(PIN_CONFIG_END + 1)
 +/**
 + * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
 + * @nbanks: number of PIO banks
 + * @last_bank_count: number of lines in the last bank (can be less than
 + *	the rest of the banks).
 + */
 struct atmel_pioctrl_data {
 	unsigned nbanks;
 +	unsigned last_bank_count;
 };
 struct atmel_group {
@@ -980,11 +987,13 @@ static const struct dev_pm_ops atmel_pct
  * We can have up to 16 banks.
  */
 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
 -	.nbanks		= 4,
 +	.nbanks			= 4,
 +	.last_bank_count	= ATMEL_PIO_NPINS_PER_BANK,
 };
 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
 -	.nbanks		= 5,
 +	.nbanks			= 5,
 +	.last_bank_count	= 8, /* sama7g5 has only PE0 to PE7 */
 };
 static const struct of_device_id atmel_pctrl_of_match[] = {
@@ -1025,6 +1034,11 @@ static int atmel_pinctrl_probe(struct pl
 	atmel_pioctrl_data = match->data;
 	atmel_pioctrl->nbanks = atmel_pioctrl_data->nbanks;
 	atmel_pioctrl->npins = atmel_pioctrl->nbanks * ATMEL_PIO_NPINS_PER_BANK;
 +	/* if last bank has limited number of pins, adjust accordingly */
 +	if (atmel_pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
 +		atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
 +		atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
 +	}
 	atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(atmel_pioctrl->reg_base))
--- a/target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch
+++ b/target/linux/at91/patches-5.10/132-dmaengine-at_xdmac-adapt-perid-for-mem2mem-operation.patch
@ -1,50 +0,0 @@
 From 1dccaa4c1e99cd8bd27684a2c87ec806d426c088 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Fri, 16 Oct 2020 12:37:25 +0300
 Subject: [PATCH 132/247] dmaengine: at_xdmac: adapt perid for mem2mem
 operations
 The PERID in the CC register for mem2mem operations must match an unused
 PERID.
 The PERID field is 7 bits, but the selected value is 0x3f.
 On later products we can have more reserved PERIDs for actual peripherals,
 thus this needs to be increased to maximum size.
 Changing the value to 0x7f, which is the maximum for 7 bits field.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
 Link: https://lore.kernel.org/r/20201016093725.289880-1-eugen.hristev@microchip.com
 Signed-off-by: Vinod Koul <vkoul@kernel.org>
 ---
 drivers/dma/at_xdmac.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
 --- a/drivers/dma/at_xdmac.c
 +++ b/drivers/dma/at_xdmac.c
@@ -865,7 +865,7 @@ at_xdmac_interleaved_queue_desc(struct d
 	 * match the one of another channel. If not, it could lead to spurious
 	 * flag status.
 	 */
 -	u32			chan_cc = AT_XDMAC_CC_PERID(0x3f)
 +	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
 					| AT_XDMAC_CC_DIF(0)
 					| AT_XDMAC_CC_SIF(0)
 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
@@ -1047,7 +1047,7 @@ at_xdmac_prep_dma_memcpy(struct dma_chan
 	 * match the one of another channel. If not, it could lead to spurious
 	 * flag status.
 	 */
 -	u32			chan_cc = AT_XDMAC_CC_PERID(0x3f)
 +	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
 					| AT_XDMAC_CC_DAM_INCREMENTED_AM
 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
 					| AT_XDMAC_CC_DIF(0)
@@ -1153,7 +1153,7 @@ static struct at_xdmac_desc *at_xdmac_me
 	 * match the one of another channel. If not, it could lead to spurious
 	 * flag status.
 	 */
 -	u32			chan_cc = AT_XDMAC_CC_PERID(0x3f)
 +	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
 					| AT_XDMAC_CC_DAM_UBS_AM
 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
 					| AT_XDMAC_CC_DIF(0)
--- a/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch
+++ b/target/linux/at91/patches-5.10/133-dmaengine-at_xdmac-add-support-for-sama7g5-based-at_.patch
@ -1,280 +0,0 @@
 From 613af756b93fe005d9db11ea26fd0318f239d5a2 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Fri, 16 Oct 2020 12:38:50 +0300
 Subject: [PATCH 133/247] dmaengine: at_xdmac: add support for sama7g5 based
 at_xdmac
 SAMA7G5 SoC uses a slightly different variant of the AT_XDMAC.
 Added support by a new compatible and a layout struct that copes
 to the specific version considering the compatible string.
 Only the differences in register map are present in the layout struct.
 I reworked the register access for this part that has the differences.
 Also the Source/Destination Interface bits are no longer valid for this
 variant of the XDMAC. Thus, the layout also has a bool for specifying
 whether these bits are required or not.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Link: https://lore.kernel.org/r/20201016093850.290053-1-eugen.hristev@microchip.com
 Signed-off-by: Vinod Koul <vkoul@kernel.org>
 ---
 drivers/dma/at_xdmac.c | 110 +++++++++++++++++++++++++++++++----------
 1 file changed, 84 insertions(+), 26 deletions(-)
 --- a/drivers/dma/at_xdmac.c
 +++ b/drivers/dma/at_xdmac.c
@@ -38,13 +38,6 @@
 #define AT_XDMAC_GE		0x1C	/* Global Channel Enable Register */
 #define AT_XDMAC_GD		0x20	/* Global Channel Disable Register */
 #define AT_XDMAC_GS		0x24	/* Global Channel Status Register */
 -#define AT_XDMAC_GRS		0x28	/* Global Channel Read Suspend Register */
 -#define AT_XDMAC_GWS		0x2C	/* Global Write Suspend Register */
 -#define AT_XDMAC_GRWS		0x30	/* Global Channel Read Write Suspend Register */
 -#define AT_XDMAC_GRWR		0x34	/* Global Channel Read Write Resume Register */
 -#define AT_XDMAC_GSWR		0x38	/* Global Channel Software Request Register */
 -#define AT_XDMAC_GSWS		0x3C	/* Global channel Software Request Status Register */
 -#define AT_XDMAC_GSWF		0x40	/* Global Channel Software Flush Request Register */
 #define AT_XDMAC_VERSION	0xFFC	/* XDMAC Version Register */
 /* Channel relative registers offsets */
@@ -151,8 +144,6 @@
 #define AT_XDMAC_CSUS		0x30	/* Channel Source Microblock Stride */
 #define AT_XDMAC_CDUS		0x34	/* Channel Destination Microblock Stride */
 -#define AT_XDMAC_CHAN_REG_BASE	0x50	/* Channel registers base address */
 -
 /* Microblock control members */
 #define AT_XDMAC_MBR_UBC_UBLEN_MAX	0xFFFFFFUL	/* Maximum Microblock Length */
 #define AT_XDMAC_MBR_UBC_NDE		(0x1 << 24)	/* Next Descriptor Enable */
@@ -180,6 +171,27 @@ enum atc_status {
 	AT_XDMAC_CHAN_IS_PAUSED,
 };
 +struct at_xdmac_layout {
 +	/* Global Channel Read Suspend Register */
 +	u8				grs;
 +	/* Global Write Suspend Register */
 +	u8				gws;
 +	/* Global Channel Read Write Suspend Register */
 +	u8				grws;
 +	/* Global Channel Read Write Resume Register */
 +	u8				grwr;
 +	/* Global Channel Software Request Register */
 +	u8				gswr;
 +	/* Global channel Software Request Status Register */
 +	u8				gsws;
 +	/* Global Channel Software Flush Request Register */
 +	u8				gswf;
 +	/* Channel reg base */
 +	u8				chan_cc_reg_base;
 +	/* Source/Destination Interface must be specified or not */
 +	bool				sdif;
 +};
 +
 /* ----- Channels ----- */
 struct at_xdmac_chan {
 	struct dma_chan			chan;
@@ -213,6 +225,7 @@ struct at_xdmac {
 	struct clk		*clk;
 	u32			save_gim;
 	struct dma_pool		*at_xdmac_desc_pool;
 +	const struct at_xdmac_layout	*layout;
 	struct at_xdmac_chan	chan[];
 };
@@ -245,9 +258,33 @@ struct at_xdmac_desc {
 	struct list_head		xfer_node;
 } __aligned(sizeof(u64));
 +static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {
 +	.grs = 0x28,
 +	.gws = 0x2C,
 +	.grws = 0x30,
 +	.grwr = 0x34,
 +	.gswr = 0x38,
 +	.gsws = 0x3C,
 +	.gswf = 0x40,
 +	.chan_cc_reg_base = 0x50,
 +	.sdif = true,
 +};
 +
 +static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
 +	.grs = 0x30,
 +	.gws = 0x38,
 +	.grws = 0x40,
 +	.grwr = 0x44,
 +	.gswr = 0x48,
 +	.gsws = 0x4C,
 +	.gswf = 0x50,
 +	.chan_cc_reg_base = 0x60,
 +	.sdif = false,
 +};
 +
 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
 {
 -	return atxdmac->regs + (AT_XDMAC_CHAN_REG_BASE + chan_nb * 0x40);
 +	return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40);
 }
 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
@@ -343,8 +380,10 @@ static void at_xdmac_start_xfer(struct a
 	first->active_xfer = true;
 	/* Tell xdmac where to get the first descriptor. */
 -	reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys)
 -	      | AT_XDMAC_CNDA_NDAIF(atchan->memif);
 +	reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys);
 +	if (atxdmac->layout->sdif)
 +		reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif);
 +
 	at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
 	/*
@@ -539,6 +578,7 @@ static int at_xdmac_compute_chan_conf(st
 				      enum dma_transfer_direction direction)
 {
 	struct at_xdmac_chan	*atchan = to_at_xdmac_chan(chan);
 +	struct at_xdmac		*atxdmac = to_at_xdmac(atchan->chan.device);
 	int			csize, dwidth;
 	if (direction == DMA_DEV_TO_MEM) {
@@ -546,12 +586,14 @@ static int at_xdmac_compute_chan_conf(st
 			AT91_XDMAC_DT_PERID(atchan->perid)
 			| AT_XDMAC_CC_DAM_INCREMENTED_AM
 			| AT_XDMAC_CC_SAM_FIXED_AM
 -			| AT_XDMAC_CC_DIF(atchan->memif)
 -			| AT_XDMAC_CC_SIF(atchan->perif)
 			| AT_XDMAC_CC_SWREQ_HWR_CONNECTED
 			| AT_XDMAC_CC_DSYNC_PER2MEM
 			| AT_XDMAC_CC_MBSIZE_SIXTEEN
 			| AT_XDMAC_CC_TYPE_PER_TRAN;
 +		if (atxdmac->layout->sdif)
 +			atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) |
 +				       AT_XDMAC_CC_SIF(atchan->perif);
 +
 		csize = ffs(atchan->sconfig.src_maxburst) - 1;
 		if (csize < 0) {
 			dev_err(chan2dev(chan), "invalid src maxburst value\n");
@@ -569,12 +611,14 @@ static int at_xdmac_compute_chan_conf(st
 			AT91_XDMAC_DT_PERID(atchan->perid)
 			| AT_XDMAC_CC_DAM_FIXED_AM
 			| AT_XDMAC_CC_SAM_INCREMENTED_AM
 -			| AT_XDMAC_CC_DIF(atchan->perif)
 -			| AT_XDMAC_CC_SIF(atchan->memif)
 			| AT_XDMAC_CC_SWREQ_HWR_CONNECTED
 			| AT_XDMAC_CC_DSYNC_MEM2PER
 			| AT_XDMAC_CC_MBSIZE_SIXTEEN
 			| AT_XDMAC_CC_TYPE_PER_TRAN;
 +		if (atxdmac->layout->sdif)
 +			atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) |
 +				       AT_XDMAC_CC_SIF(atchan->memif);
 +
 		csize = ffs(atchan->sconfig.dst_maxburst) - 1;
 		if (csize < 0) {
 			dev_err(chan2dev(chan), "invalid src maxburst value\n");
@@ -864,10 +908,12 @@ at_xdmac_interleaved_queue_desc(struct d
 	 * ERRATA: Even if useless for memory transfers, the PERID has to not
 	 * match the one of another channel. If not, it could lead to spurious
 	 * flag status.
 +	 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
 +	 * Thus, no need to have the SIF/DIF interfaces here.
 +	 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
 +	 * zero.
 	 */
 	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
 -					| AT_XDMAC_CC_DIF(0)
 -					| AT_XDMAC_CC_SIF(0)
 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
 					| AT_XDMAC_CC_TYPE_MEM_TRAN;
@@ -1046,12 +1092,14 @@ at_xdmac_prep_dma_memcpy(struct dma_chan
 	 * ERRATA: Even if useless for memory transfers, the PERID has to not
 	 * match the one of another channel. If not, it could lead to spurious
 	 * flag status.
 +	 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
 +	 * Thus, no need to have the SIF/DIF interfaces here.
 +	 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
 +	 * zero.
 	 */
 	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
 					| AT_XDMAC_CC_DAM_INCREMENTED_AM
 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
 -					| AT_XDMAC_CC_DIF(0)
 -					| AT_XDMAC_CC_SIF(0)
 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
 					| AT_XDMAC_CC_TYPE_MEM_TRAN;
 	unsigned long		irqflags;
@@ -1152,12 +1200,14 @@ static struct at_xdmac_desc *at_xdmac_me
 	 * ERRATA: Even if useless for memory transfers, the PERID has to not
 	 * match the one of another channel. If not, it could lead to spurious
 	 * flag status.
 +	 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
 +	 * Thus, no need to have the SIF/DIF interfaces here.
 +	 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
 +	 * zero.
 	 */
 	u32			chan_cc = AT_XDMAC_CC_PERID(0x7f)
 					| AT_XDMAC_CC_DAM_UBS_AM
 					| AT_XDMAC_CC_SAM_INCREMENTED_AM
 -					| AT_XDMAC_CC_DIF(0)
 -					| AT_XDMAC_CC_SIF(0)
 					| AT_XDMAC_CC_MBSIZE_SIXTEEN
 					| AT_XDMAC_CC_MEMSET_HW_MODE
 					| AT_XDMAC_CC_TYPE_MEM_TRAN;
@@ -1436,7 +1486,7 @@ at_xdmac_tx_status(struct dma_chan *chan
 	mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
 	value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
 	if ((desc->lld.mbr_cfg & mask) == value) {
 -		at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
 +		at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
 		while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
 			cpu_relax();
 	}
@@ -1494,7 +1544,7 @@ at_xdmac_tx_status(struct dma_chan *chan
 	 * FIFO flush ensures that data are really written.
 	 */
 	if ((desc->lld.mbr_cfg & mask) == value) {
 -		at_xdmac_write(atxdmac, AT_XDMAC_GSWF, atchan->mask);
 +		at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
 		while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
 			cpu_relax();
 	}
@@ -1762,7 +1812,7 @@ static int at_xdmac_device_pause(struct
 		return 0;
 	spin_lock_irqsave(&atchan->lock, flags);
 -	at_xdmac_write(atxdmac, AT_XDMAC_GRWS, atchan->mask);
 +	at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);
 	while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
 	       & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
 		cpu_relax();
@@ -1785,7 +1835,7 @@ static int at_xdmac_device_resume(struct
 		return 0;
 	}
 -	at_xdmac_write(atxdmac, AT_XDMAC_GRWR, atchan->mask);
 +	at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);
 	clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
 	spin_unlock_irqrestore(&atchan->lock, flags);
@@ -1992,6 +2042,10 @@ static int at_xdmac_probe(struct platfor
 	atxdmac->regs = base;
 	atxdmac->irq = irq;
 +	atxdmac->layout = of_device_get_match_data(&pdev->dev);
 +	if (!atxdmac->layout)
 +		return -ENODEV;
 +
 	atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
 	if (IS_ERR(atxdmac->clk)) {
 		dev_err(&pdev->dev, "can't get dma_clk\n");
@@ -2134,6 +2188,10 @@ static const struct dev_pm_ops atmel_xdm
 static const struct of_device_id atmel_xdmac_dt_ids[] = {
 	{
 		.compatible = "atmel,sama5d4-dma",
 +		.data = &at_xdmac_sama5d4_layout,
 +	}, {
 +		.compatible = "microchip,sama7g5-dma",
 +		.data = &at_xdmac_sama7g5_layout,
 	}, {
 		/* sentinel */
 	}
--- a/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch
+++ b/target/linux/at91/patches-5.10/134-dmaengine-at_xdmac-add-AXI-priority-support-and-reco.patch
@ -1,113 +0,0 @@
 From 4833d6ea13a6d2c44a91247991a82c3eb6c1613e Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Fri, 16 Oct 2020 12:39:18 +0300
 Subject: [PATCH 134/247] dmaengine: at_xdmac: add AXI priority support and
 recommended settings
 The sama7g5 version of the XDMAC supports priority configuration and
 outstanding capabilities.
 Add defines for the specific registers for this configuration, together
 with recommended settings.
 However the settings are very different if the XDMAC is a mem2mem or a
 per2mem controller.
 Thus, we need to differentiate according to device tree property.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Link: https://lore.kernel.org/r/20201016093918.290137-1-eugen.hristev@microchip.com
 Signed-off-by: Vinod Koul <vkoul@kernel.org>
 ---
 drivers/dma/at_xdmac.c | 47 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 --- a/drivers/dma/at_xdmac.c
 +++ b/drivers/dma/at_xdmac.c
@@ -30,7 +30,24 @@
 #define		AT_XDMAC_FIFO_SZ(i)	(((i) >> 5) & 0x7FF)		/* Number of Bytes */
 #define		AT_XDMAC_NB_REQ(i)	((((i) >> 16) & 0x3F) + 1)	/* Number of Peripheral Requests Minus One */
 #define AT_XDMAC_GCFG		0x04	/* Global Configuration Register */
 +#define		AT_XDMAC_WRHP(i)		(((i) & 0xF) << 4)
 +#define		AT_XDMAC_WRMP(i)		(((i) & 0xF) << 8)
 +#define		AT_XDMAC_WRLP(i)		(((i) & 0xF) << 12)
 +#define		AT_XDMAC_RDHP(i)		(((i) & 0xF) << 16)
 +#define		AT_XDMAC_RDMP(i)		(((i) & 0xF) << 20)
 +#define		AT_XDMAC_RDLP(i)		(((i) & 0xF) << 24)
 +#define		AT_XDMAC_RDSG(i)		(((i) & 0xF) << 28)
 +#define AT_XDMAC_GCFG_M2M	(AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
 +#define AT_XDMAC_GCFG_P2M	(AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
 +				AT_XDMAC_WRHP(0x5))
 #define AT_XDMAC_GWAC		0x08	/* Global Weighted Arbiter Configuration Register */
 +#define		AT_XDMAC_PW0(i)		(((i) & 0xF) << 0)
 +#define		AT_XDMAC_PW1(i)		(((i) & 0xF) << 4)
 +#define		AT_XDMAC_PW2(i)		(((i) & 0xF) << 8)
 +#define		AT_XDMAC_PW3(i)		(((i) & 0xF) << 12)
 +#define AT_XDMAC_GWAC_M2M	0
 +#define AT_XDMAC_GWAC_P2M	(AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
 +
 #define AT_XDMAC_GIE		0x0C	/* Global Interrupt Enable Register */
 #define AT_XDMAC_GID		0x10	/* Global Interrupt Disable Register */
 #define AT_XDMAC_GIM		0x14	/* Global Interrupt Mask Register */
@@ -190,6 +207,8 @@ struct at_xdmac_layout {
 	u8				chan_cc_reg_base;
 	/* Source/Destination Interface must be specified or not */
 	bool				sdif;
 +	/* AXI queue priority configuration supported */
 +	bool				axi_config;
 };
 /* ----- Channels ----- */
@@ -268,6 +287,7 @@ static const struct at_xdmac_layout at_x
 	.gswf = 0x40,
 	.chan_cc_reg_base = 0x50,
 	.sdif = true,
 +	.axi_config = false,
 };
 static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
@@ -280,6 +300,7 @@ static const struct at_xdmac_layout at_x
 	.gswf = 0x50,
 	.chan_cc_reg_base = 0x60,
 	.sdif = false,
 +	.axi_config = true,
 };
 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
@@ -2003,6 +2024,30 @@ static int atmel_xdmac_resume(struct dev
 }
 #endif /* CONFIG_PM_SLEEP */
 +static void at_xdmac_axi_config(struct platform_device *pdev)
 +{
 +	struct at_xdmac	*atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
 +	bool dev_m2m = false;
 +	u32 dma_requests;
 +
 +	if (!atxdmac->layout->axi_config)
 +		return; /* Not supported */
 +
 +	if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
 +				  &dma_requests)) {
 +		dev_info(&pdev->dev, "controller in mem2mem mode.\n");
 +		dev_m2m = true;
 +	}
 +
 +	if (dev_m2m) {
 +		at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
 +		at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
 +	} else {
 +		at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
 +		at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
 +	}
 +}
 +
 static int at_xdmac_probe(struct platform_device *pdev)
 {
 	struct at_xdmac	*atxdmac;
@@ -2147,6 +2192,8 @@ static int at_xdmac_probe(struct platfor
 	dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
 		 nr_channels, atxdmac->regs);
 +	at_xdmac_axi_config(pdev);
 +
 	return 0;
 err_dma_unregister:
--- a/target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch
+++ b/target/linux/at91/patches-5.10/135-net-macb-Correct-usage-of-MACB_CAPS_CLK_HW_CHG-flag.patch
@ -1,45 +0,0 @@
 From 982347f757b85ef526afaf243867ddd515475e1b Mon Sep 17 00:00:00 2001
 From: Charles Keepax <ckeepax@opensource.cirrus.com>
 Date: Mon, 4 Jan 2021 10:38:02 +0000
 Subject: [PATCH 135/247] net: macb: Correct usage of MACB_CAPS_CLK_HW_CHG flag
 A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of
 macb_set_tx_clk were gated on the presence of this flag.
 -   if (!clk)
 + if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
 However the flag was not added to anything other than the new
 sama7g5_gem, turning that function call into a no op for all other
 systems. This breaks the networking on Zynq.
 The commit message adding this states: a new capability so that
 macb_set_tx_clock() to not be called for IPs having this
 capability
 This strongly implies that present of the flag was intended to skip
 the function not absence of the flag. Update the if statement to
 this effect, which repairs the existing users.
 Fixes: daafa1d33cc9 ("net: macb: add capability to not set the clock rate")
 Suggested-by: Andrew Lunn <andrew@lunn.ch>
 Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
 Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
 Link: https://lore.kernel.org/r/20210104103802.13091-1-ckeepax@opensource.cirrus.com
 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 ---
 drivers/net/ethernet/cadence/macb_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -464,7 +464,7 @@ static void macb_set_tx_clk(struct macb
 {
 	long ferr, rate, rate_rounded;
 -	if (!bp->tx_clk || !(bp->caps & MACB_CAPS_CLK_HW_CHG))
 +	if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
 		return;
 	switch (speed) {
--- a/target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch
+++ b/target/linux/at91/patches-5.10/136-ARM-at91-sam9x60-SiP-types-added-to-soc-description.patch
@ -1,43 +0,0 @@
 From a2eda4ef1e3d617cdd669e256e45e969fab62398 Mon Sep 17 00:00:00 2001
 From: Kai Stuhlemmer <kai.stuhlemmer@ebee.de>
 Date: Thu, 8 Oct 2020 14:50:28 +0200
 Subject: [PATCH 136/247] ARM: at91: sam9x60 SiP types added to soc description
 Adding SAM9X60 SIP variants to the soc description list.
 Signed-off-by: Kai Stuhlemmer <kai.stuhlemmer@ebee.de>
 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
 Link: https://lore.kernel.org/r/20201008125028.21071-1-nicolas.ferre@microchip.com
 ---
 drivers/soc/atmel/soc.c | 6 ++++++
 drivers/soc/atmel/soc.h | 3 +++
 2 files changed, 9 insertions(+)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -69,6 +69,12 @@ static const struct at91_soc __initconst
 #endif
 #ifdef CONFIG_SOC_SAM9X60
 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
 +	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
 +		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
 +	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
 +		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
 +	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
 +		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
 #ifdef CONFIG_SOC_SAMA5
 	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
 --- a/drivers/soc/atmel/soc.h
 +++ b/drivers/soc/atmel/soc.h
@@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *soc
 #define AT91SAM9CN11_EXID_MATCH		0x00000009
 #define SAM9X60_EXID_MATCH		0x00000000
 +#define SAM9X60_D5M_EXID_MATCH		0x00000001
 +#define SAM9X60_D1G_EXID_MATCH		0x00000010
 +#define SAM9X60_D6K_EXID_MATCH		0x00000011
 #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
 #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
--- a/target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch
+++ b/target/linux/at91/patches-5.10/137-drivers-soc-atmel-use-GENMASK.patch
@ -1,25 +0,0 @@
 From 8d858d9c57a0210ca1ce9e5ba76fab8bdb4d7b39 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 22 Jan 2021 14:21:32 +0200
 Subject: [PATCH 137/247] drivers: soc: atmel: use GENMASK
 Use GENMASK() to define CIDR match mask.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Link: https://lore.kernel.org/r/1611318097-8970-3-git-send-email-claudiu.beznea@microchip.com
 ---
 drivers/soc/atmel/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -27,7 +27,7 @@
 #define AT91_CHIPID_EXID		0x04
 #define AT91_CIDR_VERSION(x)		((x) & 0x1f)
 #define AT91_CIDR_EXT			BIT(31)
 -#define AT91_CIDR_MATCH_MASK		0x7fffffe0
 +#define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
 static const struct at91_soc __initconst socs[] = {
 #ifdef CONFIG_SOC_AT91RM9200
--- a/target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch
+++ b/target/linux/at91/patches-5.10/138-drivers-soc-atmel-fix-__initconst-should-be-placed-a.patch
@ -1,26 +0,0 @@
 From ed871f95827e9b6d4ee9f9eafec4e18b87fb1a56 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 22 Jan 2021 14:21:33 +0200
 Subject: [PATCH 138/247] drivers: soc: atmel: fix "__initconst should be
 placed after socs[]" warning
 Fix checkpatch.pl warning: "__initconst should be placed after socs[]".
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Link: https://lore.kernel.org/r/1611318097-8970-4-git-send-email-claudiu.beznea@microchip.com
 ---
 drivers/soc/atmel/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -29,7 +29,7 @@
 #define AT91_CIDR_EXT			BIT(31)
 #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
 -static const struct at91_soc __initconst socs[] = {
 +static const struct at91_soc socs[] __initconst = {
 #ifdef CONFIG_SOC_AT91RM9200
 	AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
 #endif
--- a/target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch
+++ b/target/linux/at91/patches-5.10/139-drivers-soc-atmel-add-per-soc-id-and-version-match-m.patch
@ -1,348 +0,0 @@
 From 8f6f7ef363268f417f1729bb0b234326dd1e8e2a Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 22 Jan 2021 14:21:35 +0200
 Subject: [PATCH 139/247] drivers: soc: atmel: add per soc id and version match
 masks
 SAMA7G5 has different masks for chip ID and chip version on CIDR
 register compared to previous AT91 SoCs. For this the commit adapts
 the code for SAMA7G5 addition by introducing 2 new members in
 struct at91_soc and fill them properly and also preparing the
 parsing of proper DT binding.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Link: https://lore.kernel.org/r/1611318097-8970-6-git-send-email-claudiu.beznea@microchip.com
 ---
 drivers/soc/atmel/soc.c | 199 +++++++++++++++++++++++++++-------------
 drivers/soc/atmel/soc.h |   7 +-
 2 files changed, 140 insertions(+), 66 deletions(-)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -25,135 +25,200 @@
 #define AT91_DBGU_EXID			0x44
 #define AT91_CHIPID_CIDR		0x00
 #define AT91_CHIPID_EXID		0x04
 -#define AT91_CIDR_VERSION(x)		((x) & 0x1f)
 +#define AT91_CIDR_VERSION(x, m)		((x) & (m))
 +#define AT91_CIDR_VERSION_MASK		GENMASK(4, 0)
 #define AT91_CIDR_EXT			BIT(31)
 #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
 static const struct at91_soc socs[] __initconst = {
 #ifdef CONFIG_SOC_AT91RM9200
 -	AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
 +	AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
 #endif
 #ifdef CONFIG_SOC_AT91SAM9
 -	AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
 -	AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
 -	AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
 -	AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
 -	AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
 -	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
 +	AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
 +	AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
 +	AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
 +	AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
 +	AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
 +	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
 		 "at91sam9m11", "at91sam9g45"),
 -	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
 +	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
 		 "at91sam9m10", "at91sam9g45"),
 -	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
 +	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
 		 "at91sam9g46", "at91sam9g45"),
 -	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
 +	AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
 		 "at91sam9g45", "at91sam9g45"),
 -	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
 +	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
 		 "at91sam9g15", "at91sam9x5"),
 -	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
 +	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
 		 "at91sam9g35", "at91sam9x5"),
 -	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
 +	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
 		 "at91sam9x35", "at91sam9x5"),
 -	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
 +	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
 		 "at91sam9g25", "at91sam9x5"),
 -	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
 +	AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
 		 "at91sam9x25", "at91sam9x5"),
 -	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
 +	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
 		 "at91sam9cn12", "at91sam9n12"),
 -	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
 +	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
 		 "at91sam9n12", "at91sam9n12"),
 -	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
 +	AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
 		 "at91sam9cn11", "at91sam9n12"),
 -	AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
 -	AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
 -	AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
 +	AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
 +	AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
 +	AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
 #endif
 #ifdef CONFIG_SOC_SAM9X60
 -	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
 +	AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 +		 "sam9x60", "sam9x60"),
 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
 +		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 		 "sam9x60 64MiB DDR2 SiP", "sam9x60"),
 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
 +		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 		 "sam9x60 128MiB DDR2 SiP", "sam9x60"),
 	AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
 +		 AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
 		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
 #ifdef CONFIG_SOC_SAMA5
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
 		 "sama5d21", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
 		 "sama5d22", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
 		 "sama5d225c 16MiB SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
 		 "sama5d23", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
 		 "sama5d24", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
 		 "sama5d24", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
 		 "sama5d26", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
 		 "sama5d27", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
 		 "sama5d27", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
 		 "sama5d27c 128MiB SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
 		 "sama5d27c 64MiB SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
 		 "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
 		 "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
 		 "sama5d28", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
 		 "sama5d28", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
 		 "sama5d28c 128MiB SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
 		 "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,
 +	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
 		 "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
 -	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
 +	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
 		 "sama5d31", "sama5d3"),
 -	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
 +	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
 		 "sama5d33", "sama5d3"),
 -	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
 +	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
 		 "sama5d34", "sama5d3"),
 -	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
 +	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
 		 "sama5d35", "sama5d3"),
 -	AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
 +	AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
 		 "sama5d36", "sama5d3"),
 -	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
 +	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
 		 "sama5d41", "sama5d4"),
 -	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
 +	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
 		 "sama5d42", "sama5d4"),
 -	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
 +	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
 		 "sama5d43", "sama5d4"),
 -	AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
 +	AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
 		 "sama5d44", "sama5d4"),
 #endif
 #ifdef CONFIG_SOC_SAMV7
 -	AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
 +	AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
 		 "same70q21", "same7"),
 -	AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
 +	AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
 		 "same70q20", "same7"),
 -	AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
 +	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK
 +		 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
 		 "same70q19", "same7"),
 -	AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
 +	AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
 		 "sams70q21", "sams7"),
 -	AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
 +	AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
 		 "sams70q20", "sams7"),
 -	AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
 +	AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
 		 "sams70q19", "sams7"),
 -	AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
 +	AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
 		 "samv71q21", "samv7"),
 -	AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
 +	AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
 		 "samv71q20", "samv7"),
 -	AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
 +	AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
 		 "samv71q19", "samv7"),
 -	AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,
 +	AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
 		 "samv70q20", "samv7"),
 -	AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,
 +	AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
 		 "samv70q19", "samv7"),
 #endif
 	{ /* sentinel */ },
@@ -191,8 +256,12 @@ static int __init at91_get_cidr_exid_fro
 {
 	struct device_node *np;
 	void __iomem *regs;
 +	static const struct of_device_id chipids[] = {
 +		{ .compatible = "atmel,sama5d2-chipid" },
 +		{ },
 +	};
 -	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
 +	np = of_find_matching_node(NULL, chipids);
 	if (!np)
 		return -ENODEV;
@@ -235,7 +304,7 @@ struct soc_device * __init at91_soc_init
 	}
 	for (soc = socs; soc->name; soc++) {
 -		if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
 +		if (soc->cidr_match != (cidr & soc->cidr_mask))
 			continue;
 		if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
@@ -254,7 +323,7 @@ struct soc_device * __init at91_soc_init
 	soc_dev_attr->family = soc->family;
 	soc_dev_attr->soc_id = soc->name;
 	soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
 -					   AT91_CIDR_VERSION(cidr));
 +					   AT91_CIDR_VERSION(cidr, soc->version_mask));
 	soc_dev = soc_device_register(soc_dev_attr);
 	if (IS_ERR(soc_dev)) {
 		kfree(soc_dev_attr->revision);
@@ -266,7 +335,7 @@ struct soc_device * __init at91_soc_init
 	if (soc->family)
 		pr_info("Detected SoC family: %s\n", soc->family);
 	pr_info("Detected SoC: %s, revision %X\n", soc->name,
 -		AT91_CIDR_VERSION(cidr));
 +		AT91_CIDR_VERSION(cidr, soc->version_mask));
 	return soc_dev;
 }
 --- a/drivers/soc/atmel/soc.h
 +++ b/drivers/soc/atmel/soc.h
@@ -16,14 +16,19 @@
 struct at91_soc {
 	u32 cidr_match;
 +	u32 cidr_mask;
 +	u32 version_mask;
 	u32 exid_match;
 	const char *name;
 	const char *family;
 };
 -#define AT91_SOC(__cidr, __exid, __name, __family)		\
 +#define AT91_SOC(__cidr, __cidr_mask, __version_mask, __exid,	\
 +		 __name, __family)				\
 	{							\
 		.cidr_match = (__cidr),				\
 +		.cidr_mask = (__cidr_mask),			\
 +		.version_mask = (__version_mask),		\
 		.exid_match = (__exid),				\
 		.name = (__name),				\
 		.family = (__family),				\
--- a/target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch
+++ b/target/linux/at91/patches-5.10/140-drivers-soc-atmel-add-support-for-sama7g5.patch
@ -1,87 +0,0 @@
 From e20bb57fc51741677a6fcae04e564797fd18921b Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Fri, 22 Jan 2021 14:21:37 +0200
 Subject: [PATCH 140/247] drivers: soc: atmel: add support for sama7g5
 Add support for SAMA7G5 SoCs.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Link: https://lore.kernel.org/r/1611318097-8970-8-git-send-email-claudiu.beznea@microchip.com
 ---
 drivers/soc/atmel/soc.c | 18 ++++++++++++++++++
 drivers/soc/atmel/soc.h |  6 ++++++
 2 files changed, 24 insertions(+)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -27,8 +27,10 @@
 #define AT91_CHIPID_EXID		0x04
 #define AT91_CIDR_VERSION(x, m)		((x) & (m))
 #define AT91_CIDR_VERSION_MASK		GENMASK(4, 0)
 +#define AT91_CIDR_VERSION_MASK_SAMA7G5	GENMASK(3, 0)
 #define AT91_CIDR_EXT			BIT(31)
 #define AT91_CIDR_MATCH_MASK		GENMASK(30, 5)
 +#define AT91_CIDR_MASK_SAMA7G5		GENMASK(27, 5)
 static const struct at91_soc socs[] __initconst = {
 #ifdef CONFIG_SOC_AT91RM9200
@@ -221,6 +223,20 @@ static const struct at91_soc socs[] __in
 		 AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
 		 "samv70q19", "samv7"),
 #endif
 +#ifdef CONFIG_SOC_SAMA7
 +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
 +		 "sama7g51", "sama7g5"),
 +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
 +		 "sama7g52", "sama7g5"),
 +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
 +		 "sama7g53", "sama7g5"),
 +	AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 +		 AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
 +		 "sama7g54", "sama7g5"),
 +#endif
 	{ /* sentinel */ },
 };
@@ -258,6 +274,7 @@ static int __init at91_get_cidr_exid_fro
 	void __iomem *regs;
 	static const struct of_device_id chipids[] = {
 		{ .compatible = "atmel,sama5d2-chipid" },
 +		{ .compatible = "microchip,sama7g5-chipid" },
 		{ },
 	};
@@ -345,6 +362,7 @@ static const struct of_device_id at91_so
 	{ .compatible = "atmel,at91sam9", },
 	{ .compatible = "atmel,sama5", },
 	{ .compatible = "atmel,samv7", },
 +	{ .compatible = "microchip,sama7g5", },
 	{ }
 };
 --- a/drivers/soc/atmel/soc.h
 +++ b/drivers/soc/atmel/soc.h
@@ -48,6 +48,7 @@ at91_soc_init(const struct at91_soc *soc
 #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
 #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
 #define SAM9X60_CIDR_MATCH		0x019b35a0
 +#define SAMA7G5_CIDR_MATCH		0x00162100
 #define AT91SAM9M11_EXID_MATCH		0x00000001
 #define AT91SAM9M10_EXID_MATCH		0x00000002
@@ -69,6 +70,11 @@ at91_soc_init(const struct at91_soc *soc
 #define SAM9X60_D1G_EXID_MATCH		0x00000010
 #define SAM9X60_D6K_EXID_MATCH		0x00000011
 +#define SAMA7G51_EXID_MATCH		0x3
 +#define SAMA7G52_EXID_MATCH		0x2
 +#define SAMA7G53_EXID_MATCH		0x1
 +#define SAMA7G54_EXID_MATCH		0x0
 +
 #define AT91SAM9XE128_CIDR_MATCH	0x329973a0
 #define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
 #define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0
--- a/target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch
+++ b/target/linux/at91/patches-5.10/141-drivers-soc-atmel-add-spdx-license-identifier.patch
@ -1,49 +0,0 @@
 From acd4816cfa7811b13ca2864645f2de41031ccf4d Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Tue, 26 Jan 2021 11:29:30 +0200
 Subject: [PATCH 141/247] drivers: soc: atmel: add spdx license identifier
 Add SPDX-License-Identifier.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 [nicolas.ferre@microhcip.com: remove license boilerplate now it's useless]
 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Link: https://lore.kernel.org/r/1611653376-24168-2-git-send-email-claudiu.beznea@microchip.com
 ---
 drivers/soc/atmel/soc.c | 6 +-----
 drivers/soc/atmel/soc.h | 6 +-----
 2 files changed, 2 insertions(+), 10 deletions(-)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -1,13 +1,9 @@
 +// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (C) 2015 Atmel
  *
  * Alexandre Belloni <alexandre.belloni@free-electrons.com
  * Boris Brezillon <boris.brezillon@free-electrons.com
 - *
 - * This file is licensed under the terms of the GNU General Public
 - * License version 2.  This program is licensed "as is" without any
 - * warranty of any kind, whether express or implied.
 - *
  */
 #define pr_fmt(fmt)	"AT91: " fmt
 --- a/drivers/soc/atmel/soc.h
 +++ b/drivers/soc/atmel/soc.h
@@ -1,12 +1,8 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (C) 2015 Atmel
  *
  * Boris Brezillon <boris.brezillon@free-electrons.com
 - *
 - * This file is licensed under the terms of the GNU General Public
 - * License version 2.  This program is licensed "as is" without any
 - * warranty of any kind, whether express or implied.
 - *
  */
 #ifndef __AT91_SOC_H
--- a/target/linux/at91/patches-5.10/142-drivers-soc-atmel-fix-type-for-same7.patch
+++ b/target/linux/at91/patches-5.10/142-drivers-soc-atmel-fix-type-for-same7.patch
@ -1,28 +0,0 @@
 From b105d1dfab46c13070b8bdea1ab28d223a9c1bee Mon Sep 17 00:00:00 2001
 From: Arnd Bergmann <arnd@arndb.de>
 Date: Thu, 4 Feb 2021 16:49:25 +0100
 Subject: [PATCH 142/247] drivers: soc: atmel: fix type for same7
 A missing comma caused a build failure:
 drivers/soc/atmel/soc.c:196:24: error: too few arguments provided to function-like macro invocation
 Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks")
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 ---
 drivers/soc/atmel/soc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 --- a/drivers/soc/atmel/soc.c
 +++ b/drivers/soc/atmel/soc.c
@@ -191,7 +191,7 @@ static const struct at91_soc socs[] __in
 	AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 		 AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
 		 "same70q20", "same7"),
 -	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK
 +	AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 		 AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
 		 "same70q19", "same7"),
 	AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
--- a/target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch
+++ b/target/linux/at91/patches-5.10/143-clocksource-drivers-timer-microchip-pit64b-Add-clock.patch
@ -1,173 +0,0 @@
 From 5f090a664d62ceeaf9a0f482426e35cab18d65a9 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Tue, 19 Jan 2021 14:59:25 +0200
 Subject: [PATCH 143/247] clocksource/drivers/timer-microchip-pit64b: Add
 clocksource suspend/resume
 Add suspend/resume support for clocksource timer.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
 Link: https://lore.kernel.org/r/1611061165-30180-1-git-send-email-claudiu.beznea@microchip.com
 ---
 drivers/clocksource/timer-microchip-pit64b.c | 86 ++++++++++++++++----
 1 file changed, 71 insertions(+), 15 deletions(-)
 --- a/drivers/clocksource/timer-microchip-pit64b.c
 +++ b/drivers/clocksource/timer-microchip-pit64b.c
@@ -71,10 +71,24 @@ struct mchp_pit64b_clkevt {
 	struct clock_event_device	clkevt;
 };
 -#define to_mchp_pit64b_timer(x) \
 +#define clkevt_to_mchp_pit64b_timer(x) \
 	((struct mchp_pit64b_timer *)container_of(x,\
 		struct mchp_pit64b_clkevt, clkevt))
 +/**
 + * mchp_pit64b_clksrc - PIT64B clocksource data structure
 + * @timer: PIT64B timer
 + * @clksrc: clocksource
 + */
 +struct mchp_pit64b_clksrc {
 +	struct mchp_pit64b_timer	timer;
 +	struct clocksource		clksrc;
 +};
 +
 +#define clksrc_to_mchp_pit64b_timer(x) \
 +	((struct mchp_pit64b_timer *)container_of(x,\
 +		struct mchp_pit64b_clksrc, clksrc))
 +
 /* Base address for clocksource timer. */
 static void __iomem *mchp_pit64b_cs_base;
 /* Default cycles for clockevent timer. */
@@ -116,6 +130,36 @@ static inline void mchp_pit64b_reset(str
 	writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
 }
 +static void mchp_pit64b_suspend(struct mchp_pit64b_timer *timer)
 +{
 +	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
 +	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
 +		clk_disable_unprepare(timer->gclk);
 +	clk_disable_unprepare(timer->pclk);
 +}
 +
 +static void mchp_pit64b_resume(struct mchp_pit64b_timer *timer)
 +{
 +	clk_prepare_enable(timer->pclk);
 +	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
 +		clk_prepare_enable(timer->gclk);
 +}
 +
 +static void mchp_pit64b_clksrc_suspend(struct clocksource *cs)
 +{
 +	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
 +
 +	mchp_pit64b_suspend(timer);
 +}
 +
 +static void mchp_pit64b_clksrc_resume(struct clocksource *cs)
 +{
 +	struct mchp_pit64b_timer *timer = clksrc_to_mchp_pit64b_timer(cs);
 +
 +	mchp_pit64b_resume(timer);
 +	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
 +}
 +
 static u64 mchp_pit64b_clksrc_read(struct clocksource *cs)
 {
 	return mchp_pit64b_cnt_read(mchp_pit64b_cs_base);
@@ -128,7 +172,7 @@ static u64 notrace mchp_pit64b_sched_rea
 static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev)
 {
 -	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 +	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
@@ -137,7 +181,7 @@ static int mchp_pit64b_clkevt_shutdown(s
 static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev)
 {
 -	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 +	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 	mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
 			  MCHP_PIT64B_IER_PERIOD);
@@ -148,7 +192,7 @@ static int mchp_pit64b_clkevt_set_period
 static int mchp_pit64b_clkevt_set_next_event(unsigned long evt,
 					     struct clock_event_device *cedev)
 {
 -	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 +	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 	mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
 			  MCHP_PIT64B_IER_PERIOD);
@@ -158,21 +202,16 @@ static int mchp_pit64b_clkevt_set_next_e
 static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev)
 {
 -	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 +	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 -	writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
 -	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
 -		clk_disable_unprepare(timer->gclk);
 -	clk_disable_unprepare(timer->pclk);
 +	mchp_pit64b_suspend(timer);
 }
 static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev)
 {
 -	struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
 +	struct mchp_pit64b_timer *timer = clkevt_to_mchp_pit64b_timer(cedev);
 -	clk_prepare_enable(timer->pclk);
 -	if (timer->mode & MCHP_PIT64B_MR_SGCLK)
 -		clk_prepare_enable(timer->gclk);
 +	mchp_pit64b_resume(timer);
 }
 static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id)
@@ -296,20 +335,37 @@ done:
 static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
 					  u32 clk_rate)
 {
 +	struct mchp_pit64b_clksrc *cs;
 	int ret;
 +	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 +	if (!cs)
 +		return -ENOMEM;
 +
 	mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
 	mchp_pit64b_cs_base = timer->base;
 -	ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
 -				    210, 64, mchp_pit64b_clksrc_read);
 +	cs->timer.base = timer->base;
 +	cs->timer.pclk = timer->pclk;
 +	cs->timer.gclk = timer->gclk;
 +	cs->timer.mode = timer->mode;
 +	cs->clksrc.name = MCHP_PIT64B_NAME;
 +	cs->clksrc.mask = CLOCKSOURCE_MASK(64);
 +	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 +	cs->clksrc.rating = 210;
 +	cs->clksrc.read = mchp_pit64b_clksrc_read;
 +	cs->clksrc.suspend = mchp_pit64b_clksrc_suspend;
 +	cs->clksrc.resume = mchp_pit64b_clksrc_resume;
 +
 +	ret = clocksource_register_hz(&cs->clksrc, clk_rate);
 	if (ret) {
 		pr_debug("clksrc: Failed to register PIT64B clocksource!\n");
 		/* Stop timer. */
 		writel_relaxed(MCHP_PIT64B_CR_SWRST,
 			       timer->base + MCHP_PIT64B_CR);
 +		kfree(cs);
 		return ret;
 	}
--- a/target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch
+++ b/target/linux/at91/patches-5.10/144-ASoC-atmel-pdc-Use-managed-DMA-buffer-allocation.patch
@ -1,135 +0,0 @@
 From 0b20c174a17dcfa805ddac1301a5af7298877ec3 Mon Sep 17 00:00:00 2001
 From: Lars-Peter Clausen <lars@metafoo.de>
 Date: Wed, 6 Jan 2021 14:36:48 +0100
 Subject: [PATCH 144/247] ASoC: atmel-pdc: Use managed DMA buffer allocation
 Instead of manually managing its DMA buffers using
 dma_{alloc,free}_coherent() lets the sound core take care of this using
 managed buffers.
 On one hand this reduces the amount of boiler plate code, but the main
 motivation for the change is to use the shared code where possible. This
 makes it easier to argue about correctness and that the code does not
 contain subtle bugs like data leakage or similar.
 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 Reviewed-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20210106133650.13509-1-lars@metafoo.de
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/atmel-pcm-pdc.c | 78 ++-------------------------------
 1 file changed, 4 insertions(+), 74 deletions(-)
 --- a/sound/soc/atmel/atmel-pcm-pdc.c
 +++ b/sound/soc/atmel/atmel-pcm-pdc.c
@@ -34,86 +34,21 @@
 #include "atmel-pcm.h"
 -static int atmel_pcm_preallocate_dma_buffer(struct snd_pcm *pcm,
 -	int stream)
 -{
 -	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
 -	struct snd_dma_buffer *buf = &substream->dma_buffer;
 -	size_t size = ATMEL_SSC_DMABUF_SIZE;
 -
 -	buf->dev.type = SNDRV_DMA_TYPE_DEV;
 -	buf->dev.dev = pcm->card->dev;
 -	buf->private_data = NULL;
 -	buf->area = dma_alloc_coherent(pcm->card->dev, size,
 -			&buf->addr, GFP_KERNEL);
 -	pr_debug("atmel-pcm: alloc dma buffer: area=%p, addr=%p, size=%zu\n",
 -			(void *)buf->area, (void *)(long)buf->addr, size);
 -
 -	if (!buf->area)
 -		return -ENOMEM;
 -
 -	buf->bytes = size;
 -	return 0;
 -}
 -
 -static int atmel_pcm_mmap(struct snd_soc_component *component,
 -			  struct snd_pcm_substream *substream,
 -			  struct vm_area_struct *vma)
 -{
 -	return remap_pfn_range(vma, vma->vm_start,
 -		       substream->dma_buffer.addr >> PAGE_SHIFT,
 -		       vma->vm_end - vma->vm_start, vma->vm_page_prot);
 -}
 -
 static int atmel_pcm_new(struct snd_soc_component *component,
 			 struct snd_soc_pcm_runtime *rtd)
 {
 	struct snd_card *card = rtd->card->snd_card;
 -	struct snd_pcm *pcm = rtd->pcm;
 	int ret;
 	ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
 	if (ret)
 		return ret;
 -	if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
 -		pr_debug("atmel-pcm: allocating PCM playback DMA buffer\n");
 -		ret = atmel_pcm_preallocate_dma_buffer(pcm,
 -			SNDRV_PCM_STREAM_PLAYBACK);
 -		if (ret)
 -			goto out;
 -	}
 +	snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV,
 +				       card->dev, ATMEL_SSC_DMABUF_SIZE,
 +				       ATMEL_SSC_DMABUF_SIZE);
 -	if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
 -		pr_debug("atmel-pcm: allocating PCM capture DMA buffer\n");
 -		ret = atmel_pcm_preallocate_dma_buffer(pcm,
 -			SNDRV_PCM_STREAM_CAPTURE);
 -		if (ret)
 -			goto out;
 -	}
 - out:
 -	return ret;
 -}
 -
 -static void atmel_pcm_free(struct snd_soc_component *component,
 -			   struct snd_pcm *pcm)
 -{
 -	struct snd_pcm_substream *substream;
 -	struct snd_dma_buffer *buf;
 -	int stream;
 -
 -	for (stream = 0; stream < 2; stream++) {
 -		substream = pcm->streams[stream].substream;
 -		if (!substream)
 -			continue;
 -
 -		buf = &substream->dma_buffer;
 -		if (!buf->area)
 -			continue;
 -		dma_free_coherent(pcm->card->dev, buf->bytes,
 -				  buf->area, buf->addr);
 -		buf->area = NULL;
 -	}
 +	return 0;
 }
 /*--------------------------------------------------------------------------*\
@@ -210,9 +145,6 @@ static int atmel_pcm_hw_params(struct sn
 	/* this may get called several times by oss emulation
 	 * with different params */
 -	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
 -	runtime->dma_bytes = params_buffer_bytes(params);
 -
 	prtd->params = snd_soc_dai_get_dma_data(asoc_rtd_to_cpu(rtd, 0), substream);
 	prtd->params->dma_intr_handler = atmel_pcm_dma_irq;
@@ -384,9 +316,7 @@ static const struct snd_soc_component_dr
 	.prepare	= atmel_pcm_prepare,
 	.trigger	= atmel_pcm_trigger,
 	.pointer	= atmel_pcm_pointer,
 -	.mmap		= atmel_pcm_mmap,
 	.pcm_construct	= atmel_pcm_new,
 -	.pcm_destruct	= atmel_pcm_free,
 };
 int atmel_pcm_pdc_platform_register(struct device *dev)
--- a/target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch
+++ b/target/linux/at91/patches-5.10/145-power-reset-at91-sama5d2_shdwc-add-support-for-sama7.patch
@ -1,141 +0,0 @@
 From f39f2312a68ec0843adba08f9c9182ffa5624190 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 16 Dec 2020 14:57:33 +0200
 Subject: [PATCH 145/247] power: reset: at91-sama5d2_shdwc: add support for
 sama7g5
 Add support for SAMA7G5 by adding proper struct reg_config structure
 and since SAMA7G5 is not currently on LPDDR setups the commit also
 avoid the mapping of DDR controller.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
 ---
 drivers/power/reset/at91-sama5d2_shdwc.c | 72 ++++++++++++++++++------
 1 file changed, 54 insertions(+), 18 deletions(-)
 --- a/drivers/power/reset/at91-sama5d2_shdwc.c
 +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
@@ -78,9 +78,15 @@ struct pmc_reg_config {
 	u8 mckr;
 };
 +struct ddrc_reg_config {
 +	u32 type_offset;
 +	u32 type_mask;
 +};
 +
 struct reg_config {
 	struct shdwc_reg_config shdwc;
 	struct pmc_reg_config pmc;
 +	struct ddrc_reg_config ddrc;
 };
 struct shdwc {
@@ -262,6 +268,10 @@ static const struct reg_config sama5d2_r
 	.pmc = {
 		.mckr		= 0x30,
 	},
 +	.ddrc = {
 +		.type_offset	= AT91_DDRSDRC_MDR,
 +		.type_mask	= AT91_DDRSDRC_MD
 +	},
 };
 static const struct reg_config sam9x60_reg_config = {
@@ -275,6 +285,23 @@ static const struct reg_config sam9x60_r
 	.pmc = {
 		.mckr		= 0x28,
 	},
 +	.ddrc = {
 +		.type_offset	= AT91_DDRSDRC_MDR,
 +		.type_mask	= AT91_DDRSDRC_MD
 +	},
 +};
 +
 +static const struct reg_config sama7g5_reg_config = {
 +	.shdwc = {
 +		.wkup_pin_input = 0,
 +		.mr_rtcwk_shift = 17,
 +		.mr_rttwk_shift = 16,
 +		.sr_rtcwk_shift = 5,
 +		.sr_rttwk_shift = 4,
 +	},
 +	.pmc = {
 +		.mckr		= 0x28,
 +	},
 };
 static const struct of_device_id at91_shdwc_of_match[] = {
@@ -285,6 +312,10 @@ static const struct of_device_id at91_sh
 	{
 		.compatible = "microchip,sam9x60-shdwc",
 		.data = &sam9x60_reg_config,
 +	},
 +	{
 +		.compatible = "microchip,sama7g5-shdwc",
 +		.data = &sama7g5_reg_config,
 	}, {
 		/*sentinel*/
 	}
@@ -294,6 +325,7 @@ MODULE_DEVICE_TABLE(of, at91_shdwc_of_ma
 static const struct of_device_id at91_pmc_ids[] = {
 	{ .compatible = "atmel,sama5d2-pmc" },
 	{ .compatible = "microchip,sam9x60-pmc" },
 +	{ .compatible = "microchip,sama7g5-pmc" },
 	{ /* Sentinel. */ }
 };
@@ -355,30 +387,34 @@ static int __init at91_shdwc_probe(struc
 		goto clk_disable;
 	}
 -	np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
 -	if (!np) {
 -		ret = -ENODEV;
 -		goto unmap;
 -	}
 +	if (at91_shdwc->rcfg->ddrc.type_mask) {
 +		np = of_find_compatible_node(NULL, NULL,
 +					     "atmel,sama5d3-ddramc");
 +		if (!np) {
 +			ret = -ENODEV;
 +			goto unmap;
 +		}
 -	at91_shdwc->mpddrc_base = of_iomap(np, 0);
 -	of_node_put(np);
 +		at91_shdwc->mpddrc_base = of_iomap(np, 0);
 +		of_node_put(np);
 -	if (!at91_shdwc->mpddrc_base) {
 -		ret = -ENOMEM;
 -		goto unmap;
 +		if (!at91_shdwc->mpddrc_base) {
 +			ret = -ENOMEM;
 +			goto unmap;
 +		}
 +
 +		ddr_type = readl(at91_shdwc->mpddrc_base +
 +				 at91_shdwc->rcfg->ddrc.type_offset) &
 +				 at91_shdwc->rcfg->ddrc.type_mask;
 +		if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
 +		    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
 +			iounmap(at91_shdwc->mpddrc_base);
 +			at91_shdwc->mpddrc_base = NULL;
 +		}
 	}
 	pm_power_off = at91_poweroff;
 -	ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) &
 -			 AT91_DDRSDRC_MD;
 -	if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
 -	    ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
 -		iounmap(at91_shdwc->mpddrc_base);
 -		at91_shdwc->mpddrc_base = NULL;
 -	}
 -
 	return 0;
 unmap:
--- a/target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch
+++ b/target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch
@ -1,121 +0,0 @@
 From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 27 Jan 2021 13:45:44 +0200
 Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate
 SAMA7G5 supports slew rate configuration. Adapt the driver for this.
 For output switching frequencies lower than 50MHz the slew rate needs to
 be enabled. Since most of the pins on SAMA7G5 fall into this category
 enabled the slew rate by default.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
 Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 ---
 drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 --- a/drivers/pinctrl/pinctrl-at91-pio4.c
 +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -36,6 +36,7 @@
 #define		ATMEL_PIO_DIR_MASK		BIT(8)
 #define		ATMEL_PIO_PUEN_MASK		BIT(9)
 #define		ATMEL_PIO_PDEN_MASK		BIT(10)
 +#define		ATMEL_PIO_SR_MASK		BIT(11)
 #define		ATMEL_PIO_IFEN_MASK		BIT(12)
 #define		ATMEL_PIO_IFSCEN_MASK		BIT(13)
 #define		ATMEL_PIO_OPD_MASK		BIT(14)
@@ -76,10 +77,12 @@
  * @nbanks: number of PIO banks
  * @last_bank_count: number of lines in the last bank (can be less than
  *	the rest of the banks).
 + * @slew_rate_support: slew rate support
  */
 struct atmel_pioctrl_data {
 	unsigned nbanks;
 	unsigned last_bank_count;
 +	unsigned int slew_rate_support;
 };
 struct atmel_group {
@@ -117,6 +120,7 @@ struct atmel_pin {
  * @pm_suspend_backup: backup/restore register values on suspend/resume
  * @dev: device entry for the Atmel PIO controller.
  * @node: node of the Atmel PIO controller.
 + * @slew_rate_support: slew rate support
  */
 struct atmel_pioctrl {
 	void __iomem		*reg_base;
@@ -138,6 +142,7 @@ struct atmel_pioctrl {
 	} *pm_suspend_backup;
 	struct device		*dev;
 	struct device_node	*node;
 +	unsigned int		slew_rate_support;
 };
 static const char * const atmel_functions[] = {
@@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_g
 			return -EINVAL;
 		arg = 1;
 		break;
 +	case PIN_CONFIG_SLEW_RATE:
 +		if (!atmel_pioctrl->slew_rate_support)
 +			return -EOPNOTSUPP;
 +		if (!(res & ATMEL_PIO_SR_MASK))
 +			return -EINVAL;
 +		arg = 1;
 +		break;
 	case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
 		if (!(res & ATMEL_PIO_DRVSTR_MASK))
 			return -EINVAL;
@@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_s
 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
 			__func__, pin_id, configs[i]);
 +		/* Keep slew rate enabled by default. */
 +		if (atmel_pioctrl->slew_rate_support)
 +			conf |= ATMEL_PIO_SR_MASK;
 +
 		switch (param) {
 		case PIN_CONFIG_BIAS_DISABLE:
 			conf &= (~ATMEL_PIO_PUEN_MASK);
@@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_s
 					ATMEL_PIO_SODR);
 			}
 			break;
 +		case PIN_CONFIG_SLEW_RATE:
 +			if (!atmel_pioctrl->slew_rate_support)
 +				break;
 +			/* And remove it if explicitly requested. */
 +			if (arg == 0)
 +				conf &= ~ATMEL_PIO_SR_MASK;
 +			break;
 		case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
 			switch (arg) {
 			case ATMEL_PIO_DRVSTR_LO:
@@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_sh
 		seq_printf(s, "%s ", "open-drain");
 	if (conf & ATMEL_PIO_SCHMITT_MASK)
 		seq_printf(s, "%s ", "schmitt");
 +	if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
 +		seq_printf(s, "%s ", "slew-rate");
 	if (conf & ATMEL_PIO_DRVSTR_MASK) {
 		switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
 		case ATMEL_PIO_DRVSTR_ME:
@@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data a
 static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
 	.nbanks			= 5,
 	.last_bank_count	= 8, /* sama7g5 has only PE0 to PE7 */
 +	.slew_rate_support	= 1,
 };
 static const struct of_device_id atmel_pctrl_of_match[] = {
@@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct pl
 		atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
 		atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
 	}
 +	atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
 	atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(atmel_pioctrl->reg_base))
--- a/target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch
+++ b/target/linux/at91/patches-5.10/147-pinctrl-at91-pio4-fix-Prefer-unsigned-int-to-bare-us.patch
@ -1,340 +0,0 @@
 From 99629d1ad7e4e03ac3324d36b703220555b65566 Mon Sep 17 00:00:00 2001
 From: Claudiu Beznea <claudiu.beznea@microchip.com>
 Date: Wed, 27 Jan 2021 13:45:45 +0200
 Subject: [PATCH 147/247] pinctrl: at91-pio4: fix "Prefer 'unsigned int' to
 bare use of 'unsigned'"
 Fix "Prefer 'unsigned int' to bare use of 'unsigned'" checkpatch.pl
 warning.
 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
 Link: https://lore.kernel.org/r/1611747945-29960-4-git-send-email-claudiu.beznea@microchip.com
 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 ---
 drivers/pinctrl/pinctrl-at91-pio4.c | 110 ++++++++++++++--------------
 1 file changed, 57 insertions(+), 53 deletions(-)
 --- a/drivers/pinctrl/pinctrl-at91-pio4.c
 +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -80,8 +80,8 @@
  * @slew_rate_support: slew rate support
  */
 struct atmel_pioctrl_data {
 -	unsigned nbanks;
 -	unsigned last_bank_count;
 +	unsigned int nbanks;
 +	unsigned int last_bank_count;
 	unsigned int slew_rate_support;
 };
@@ -91,11 +91,11 @@ struct atmel_group {
 };
 struct atmel_pin {
 -	unsigned pin_id;
 -	unsigned mux;
 -	unsigned ioset;
 -	unsigned bank;
 -	unsigned line;
 +	unsigned int pin_id;
 +	unsigned int mux;
 +	unsigned int ioset;
 +	unsigned int bank;
 +	unsigned int line;
 	const char *device;
 };
@@ -125,16 +125,16 @@ struct atmel_pin {
 struct atmel_pioctrl {
 	void __iomem		*reg_base;
 	struct clk		*clk;
 -	unsigned		nbanks;
 +	unsigned int		nbanks;
 	struct pinctrl_dev	*pinctrl_dev;
 	struct atmel_group	*groups;
 	const char * const	*group_names;
 	struct atmel_pin	**pins;
 -	unsigned		npins;
 +	unsigned int		npins;
 	struct gpio_chip	*gpio_chip;
 	struct irq_domain	*irq_domain;
 	int			*irqs;
 -	unsigned		*pm_wakeup_sources;
 +	unsigned int		*pm_wakeup_sources;
 	struct {
 		u32		imr;
 		u32		odsr;
@@ -177,11 +177,11 @@ static void atmel_gpio_irq_ack(struct ir
 	 */
 }
 -static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned type)
 +static int atmel_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
 	struct atmel_pioctrl *atmel_pioctrl = irq_data_get_irq_chip_data(d);
 	struct atmel_pin *pin = atmel_pioctrl->pins[d->hwirq];
 -	unsigned reg;
 +	unsigned int reg;
 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
 			 BIT(pin->line));
@@ -268,7 +268,7 @@ static struct irq_chip atmel_gpio_irq_ch
 	.irq_set_wake	= atmel_gpio_irq_set_wake,
 };
 -static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 +static int atmel_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
 {
 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
@@ -316,11 +316,12 @@ static void atmel_gpio_irq_handler(struc
 	chained_irq_exit(chip, desc);
 }
 -static int atmel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 +static int atmel_gpio_direction_input(struct gpio_chip *chip,
 +				      unsigned int offset)
 {
 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 -	unsigned reg;
 +	unsigned int reg;
 	atmel_gpio_write(atmel_pioctrl, pin->bank, ATMEL_PIO_MSKR,
 			 BIT(pin->line));
@@ -331,11 +332,11 @@ static int atmel_gpio_direction_input(st
 	return 0;
 }
 -static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
 +static int atmel_gpio_get(struct gpio_chip *chip, unsigned int offset)
 {
 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 -	unsigned reg;
 +	unsigned int reg;
 	reg = atmel_gpio_read(atmel_pioctrl, pin->bank, ATMEL_PIO_PDSR);
@@ -369,12 +370,13 @@ static int atmel_gpio_get_multiple(struc
 	return 0;
 }
 -static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 +static int atmel_gpio_direction_output(struct gpio_chip *chip,
 +				       unsigned int offset,
 				       int value)
 {
 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
 -	unsigned reg;
 +	unsigned int reg;
 	atmel_gpio_write(atmel_pioctrl, pin->bank,
 			 value ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
@@ -389,7 +391,7 @@ static int atmel_gpio_direction_output(s
 	return 0;
 }
 -static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 +static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
 {
 	struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
 	struct atmel_pin *pin = atmel_pioctrl->pins[offset];
@@ -445,11 +447,11 @@ static struct gpio_chip atmel_gpio_chip
 /* --- PINCTRL --- */
 static unsigned int atmel_pin_config_read(struct pinctrl_dev *pctldev,
 -					  unsigned pin_id)
 +					  unsigned int pin_id)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 -	unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
 -	unsigned line = atmel_pioctrl->pins[pin_id]->line;
 +	unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
 +	unsigned int line = atmel_pioctrl->pins[pin_id]->line;
 	void __iomem *addr = atmel_pioctrl->reg_base
 			     + bank * ATMEL_PIO_BANK_OFFSET;
@@ -461,11 +463,11 @@ static unsigned int atmel_pin_config_rea
 }
 static void atmel_pin_config_write(struct pinctrl_dev *pctldev,
 -				   unsigned pin_id, u32 conf)
 +				   unsigned int pin_id, u32 conf)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 -	unsigned bank = atmel_pioctrl->pins[pin_id]->bank;
 -	unsigned line = atmel_pioctrl->pins[pin_id]->line;
 +	unsigned int bank = atmel_pioctrl->pins[pin_id]->bank;
 +	unsigned int line = atmel_pioctrl->pins[pin_id]->line;
 	void __iomem *addr = atmel_pioctrl->reg_base
 			     + bank * ATMEL_PIO_BANK_OFFSET;
@@ -483,7 +485,7 @@ static int atmel_pctl_get_groups_count(s
 }
 static const char *atmel_pctl_get_group_name(struct pinctrl_dev *pctldev,
 -					     unsigned selector)
 +					     unsigned int selector)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
@@ -491,19 +493,20 @@ static const char *atmel_pctl_get_group_
 }
 static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
 -				     unsigned selector, const unsigned **pins,
 -				     unsigned *num_pins)
 +				     unsigned int selector,
 +				     const unsigned int **pins,
 +				     unsigned int *num_pins)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 -	*pins = (unsigned *)&atmel_pioctrl->groups[selector].pin;
 +	*pins = (unsigned int *)&atmel_pioctrl->groups[selector].pin;
 	*num_pins = 1;
 	return 0;
 }
 static struct atmel_group *
 -atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
 +atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned int pin)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 	int i;
@@ -524,7 +527,7 @@ static int atmel_pctl_xlate_pinfunc(stru
 				    const char **func_name)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 -	unsigned pin_id, func_id;
 +	unsigned int pin_id, func_id;
 	struct atmel_group *grp;
 	pin_id = ATMEL_GET_PIN_NO(pinfunc);
@@ -554,10 +557,10 @@ static int atmel_pctl_xlate_pinfunc(stru
 static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 					struct device_node *np,
 					struct pinctrl_map **map,
 -					unsigned *reserved_maps,
 -					unsigned *num_maps)
 +					unsigned int *reserved_maps,
 +					unsigned int *num_maps)
 {
 -	unsigned num_pins, num_configs, reserve;
 +	unsigned int num_pins, num_configs, reserve;
 	unsigned long *configs;
 	struct property	*pins;
 	u32 pinfunc;
@@ -628,10 +631,10 @@ exit:
 static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
 				     struct device_node *np_config,
 				     struct pinctrl_map **map,
 -				     unsigned *num_maps)
 +				     unsigned int *num_maps)
 {
 	struct device_node *np;
 -	unsigned reserved_maps;
 +	unsigned int reserved_maps;
 	int ret;
 	*map = NULL;
@@ -679,13 +682,13 @@ static int atmel_pmx_get_functions_count
 }
 static const char *atmel_pmx_get_function_name(struct pinctrl_dev *pctldev,
 -					       unsigned selector)
 +					       unsigned int selector)
 {
 	return atmel_functions[selector];
 }
 static int atmel_pmx_get_function_groups(struct pinctrl_dev *pctldev,
 -					 unsigned selector,
 +					 unsigned int selector,
 					 const char * const **groups,
 					 unsigned * const num_groups)
 {
@@ -698,11 +701,11 @@ static int atmel_pmx_get_function_groups
 }
 static int atmel_pmx_set_mux(struct pinctrl_dev *pctldev,
 -			     unsigned function,
 -			     unsigned group)
 +			     unsigned int function,
 +			     unsigned int group)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 -	unsigned pin;
 +	unsigned int pin;
 	u32 conf;
 	dev_dbg(pctldev->dev, "enable function %s group %s\n",
@@ -726,13 +729,13 @@ static const struct pinmux_ops atmel_pmx
 };
 static int atmel_conf_pin_config_group_get(struct pinctrl_dev *pctldev,
 -					   unsigned group,
 +					   unsigned int group,
 					   unsigned long *config)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 -	unsigned param = pinconf_to_config_param(*config), arg = 0;
 +	unsigned int param = pinconf_to_config_param(*config), arg = 0;
 	struct atmel_group *grp = atmel_pioctrl->groups + group;
 -	unsigned pin_id = grp->pin;
 +	unsigned int pin_id = grp->pin;
 	u32 res;
 	res = atmel_pin_config_read(pctldev, pin_id);
@@ -786,21 +789,21 @@ static int atmel_conf_pin_config_group_g
 }
 static int atmel_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
 -					   unsigned group,
 +					   unsigned int group,
 					   unsigned long *configs,
 -					   unsigned num_configs)
 +					   unsigned int num_configs)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 	struct atmel_group *grp = atmel_pioctrl->groups + group;
 -	unsigned bank, pin, pin_id = grp->pin;
 +	unsigned int bank, pin, pin_id = grp->pin;
 	u32 mask, conf = 0;
 	int i;
 	conf = atmel_pin_config_read(pctldev, pin_id);
 	for (i = 0; i < num_configs; i++) {
 -		unsigned param = pinconf_to_config_param(configs[i]);
 -		unsigned arg = pinconf_to_config_argument(configs[i]);
 +		unsigned int param = pinconf_to_config_param(configs[i]);
 +		unsigned int arg = pinconf_to_config_argument(configs[i]);
 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
 			__func__, pin_id, configs[i]);
@@ -900,7 +903,8 @@ static int atmel_conf_pin_config_group_s
 }
 static void atmel_conf_pin_config_dbg_show(struct pinctrl_dev *pctldev,
 -					   struct seq_file *s, unsigned pin_id)
 +					   struct seq_file *s,
 +					   unsigned int pin_id)
 {
 	struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
 	u32 conf;
@@ -1108,8 +1112,8 @@ static int atmel_pinctrl_probe(struct pl
 		return -ENOMEM;
 	for (i = 0 ; i < atmel_pioctrl->npins; i++) {
 		struct atmel_group *group = atmel_pioctrl->groups + i;
 -		unsigned bank = ATMEL_PIO_BANK(i);
 -		unsigned line = ATMEL_PIO_LINE(i);
 +		unsigned int bank = ATMEL_PIO_BANK(i);
 +		unsigned int line = ATMEL_PIO_LINE(i);
 		atmel_pioctrl->pins[i] = devm_kzalloc(dev,
 				sizeof(**atmel_pioctrl->pins), GFP_KERNEL);
--- a/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch
+++ b/target/linux/at91/patches-5.10/148-net-macb-Add-default-usrio-config-to-default-gem-con.patch
@ -1,58 +0,0 @@
 From 096f58e564aed56936ef6de42a44c3101e9b8ed1 Mon Sep 17 00:00:00 2001
 From: Atish Patra <atish.patra@wdc.com>
 Date: Wed, 3 Mar 2021 11:55:49 -0800
 Subject: [PATCH 148/247] net: macb: Add default usrio config to default gem
 config
 There is no usrio config defined for default gem config leading to
 a kernel panic devices that don't define a data. This issue can be
 reprdouced with microchip polar fire soc where compatible string
 is defined as "cdns,macb".
 Fixes: edac63861db7 ("add userio bits as platform configuration")
 Signed-off-by: Atish Patra <atish.patra@wdc.com>
 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
 Signed-off-by: David S. Miller <davem@davemloft.net>
 ---
 drivers/net/ethernet/cadence/macb_main.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)
 --- a/drivers/net/ethernet/cadence/macb_main.c
 +++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -3865,6 +3865,13 @@ static int macb_init(struct platform_dev
 	return 0;
 }
 +static const struct macb_usrio_config macb_default_usrio = {
 +	.mii = MACB_BIT(MII),
 +	.rmii = MACB_BIT(RMII),
 +	.rgmii = GEM_BIT(RGMII),
 +	.refclk = MACB_BIT(CLKEN),
 +};
 +
 #if defined(CONFIG_OF)
 /* 1518 rounded up */
 #define AT91ETHER_MAX_RBUFF_SZ	0x600
@@ -4380,13 +4387,6 @@ static int fu540_c000_init(struct platfo
 	return macb_init(pdev);
 }
 -static const struct macb_usrio_config macb_default_usrio = {
 -	.mii = MACB_BIT(MII),
 -	.rmii = MACB_BIT(RMII),
 -	.rgmii = GEM_BIT(RGMII),
 -	.refclk = MACB_BIT(CLKEN),
 -};
 -
 static const struct macb_usrio_config sama7g5_usrio = {
 	.mii = 0,
 	.rmii = 1,
@@ -4535,6 +4535,7 @@ static const struct macb_config default_
 	.dma_burst_length = 16,
 	.clk_init = macb_clk_init,
 	.init = macb_init,
 +	.usrio = &macb_default_usrio,
 	.jumbo_max_len = 10240,
 };
--- a/target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch
+++ b/target/linux/at91/patches-5.10/149-ARM-at91-pm-Move-prototypes-to-mutually-included-hea.patch
@ -1,108 +0,0 @@
 From 746aba88c64e409cbc3757a5f81fad5b5c74bbcc Mon Sep 17 00:00:00 2001
 From: Lee Jones <lee.jones@linaro.org>
 Date: Wed, 3 Mar 2021 12:41:49 +0000
 Subject: [PATCH 149/247] ARM: at91: pm: Move prototypes to mutually included
 header
 MIME-Version: 1.0
 Content-Type: text/plain; charset=UTF-8
 Content-Transfer-Encoding: 8bit
 Both the caller and the supplier's source file should have access to
 the include file containing the prototypes.
 Fixes the following W=1 kernel build warning(s):
 drivers/pinctrl/pinctrl-at91.c:1637:6: warning: no previous prototype for ‘at91_pinctrl_gpio_suspend’ [-Wmissing-prototypes]
 1637 | void at91_pinctrl_gpio_suspend(void)
 | ^~~~~~~~~~~~~~~~~~~~~~~~~
 drivers/pinctrl/pinctrl-at91.c:1661:6: warning: no previous prototype for ‘at91_pinctrl_gpio_resume’ [-Wmissing-prototypes]
 1661 | void at91_pinctrl_gpio_resume(void)
 | ^~~~~~~~~~~~~~~~~~~~~~~~
 Cc: Russell King <linux@armlinux.org.uk>
 Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
 Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
 Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
 Signed-off-by: Lee Jones <lee.jones@linaro.org>
 Acked-by: Linus Walleij <linus.walleij@linaro.org>
 Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
 Link: https://lore.kernel.org/r/20210303124149.3149511-1-lee.jones@linaro.org
 ---
 arch/arm/mach-at91/pm.c        | 19 ++++++++-----------
 drivers/pinctrl/pinctrl-at91.c |  2 ++
 include/soc/at91/pm.h          | 16 ++++++++++++++++
 3 files changed, 26 insertions(+), 11 deletions(-)
 create mode 100644 include/soc/at91/pm.h
 --- a/arch/arm/mach-at91/pm.c
 +++ b/arch/arm/mach-at91/pm.c
@@ -17,6 +17,8 @@
 #include <linux/clk/at91_pmc.h>
 #include <linux/platform_data/atmel.h>
 +#include <soc/at91/pm.h>
 +
 #include <asm/cacheflush.h>
 #include <asm/fncpy.h>
 #include <asm/system_misc.h>
@@ -25,17 +27,6 @@
 #include "generic.h"
 #include "pm.h"
 -/*
 - * FIXME: this is needed to communicate between the pinctrl driver and
 - * the PM implementation in the machine. Possibly part of the PM
 - * implementation should be moved down into the pinctrl driver and get
 - * called as part of the generic suspend/resume path.
 - */
 -#ifdef CONFIG_PINCTRL_AT91
 -extern void at91_pinctrl_gpio_suspend(void);
 -extern void at91_pinctrl_gpio_resume(void);
 -#endif
 -
 struct at91_soc_pm {
 	int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
 	int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
@@ -326,6 +317,12 @@ static void at91_pm_suspend(suspend_stat
 static int at91_pm_enter(suspend_state_t state)
 {
 #ifdef CONFIG_PINCTRL_AT91
 +	/*
 +	 * FIXME: this is needed to communicate between the pinctrl driver and
 +	 * the PM implementation in the machine. Possibly part of the PM
 +	 * implementation should be moved down into the pinctrl driver and get
 +	 * called as part of the generic suspend/resume path.
 +	 */
 	at91_pinctrl_gpio_suspend();
 #endif
 --- a/drivers/pinctrl/pinctrl-at91.c
 +++ b/drivers/pinctrl/pinctrl-at91.c
@@ -23,6 +23,8 @@
 /* Since we request GPIOs from ourself */
 #include <linux/pinctrl/consumer.h>
 +#include <soc/at91/pm.h>
 +
 #include "pinctrl-at91.h"
 #include "core.h"
 --- /dev/null
 +++ b/include/soc/at91/pm.h
@@ -0,0 +1,16 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +/*
 + * Atmel Power Management
 + *
 + * Copyright (C) 2020 Atmel
 + *
 + * Author: Lee Jones <lee.jones@linaro.org>
 + */
 +
 +#ifndef __SOC_ATMEL_PM_H
 +#define __SOC_ATMEL_PM_H
 +
 +void at91_pinctrl_gpio_suspend(void);
 +void at91_pinctrl_gpio_resume(void);
 +
 +#endif /* __SOC_ATMEL_PM_H */
--- a/target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch
+++ b/target/linux/at91/patches-5.10/150-ASoC-mchp-i2s-mcc-Add-compatible-for-SAMA7G5.patch
@ -1,46 +0,0 @@
 From d6493e6f1c42f7ad350ea25e11f0e71fc32e6116 Mon Sep 17 00:00:00 2001
 From: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Date: Mon, 1 Mar 2021 19:09:00 +0200
 Subject: [PATCH 150/247] ASoC: mchp-i2s-mcc: Add compatible for SAMA7G5
 Microchip's new SAMA7G5 includes an updated I2S-MCC compatible with the
 previous version found on SAM9X60. The new controller includes 8 (4 * 2)
 input and output data pins for up to 8 channels for I2S and Left-Justified
 formats.
 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20210301170905.835091-3-codrin.ciubotariu@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/Kconfig        | 3 +++
 sound/soc/atmel/mchp-i2s-mcc.c | 3 +++
 2 files changed, 6 insertions(+)
 --- a/sound/soc/atmel/Kconfig
 +++ b/sound/soc/atmel/Kconfig
@@ -126,10 +126,13 @@ config SND_MCHP_SOC_I2S_MCC
 	  Say Y or M if you want to add support for I2S Multi-Channel ASoC
 	  driver on the following Microchip platforms:
 	  - sam9x60
 +	  - sama7g5
 	  The I2SMCC complies with the Inter-IC Sound (I2S) bus specification
 	  and supports a Time Division Multiplexed (TDM) interface with
 	  external multi-channel audio codecs.
 +	  Starting with sama7g5, I2S and Left-Justified multi-channel is
 +	  supported by using multiple data pins, output and input, without TDM.
 config SND_MCHP_SOC_SPDIFTX
 	tristate "Microchip ASoC driver for boards using S/PDIF TX"
 --- a/sound/soc/atmel/mchp-i2s-mcc.c
 +++ b/sound/soc/atmel/mchp-i2s-mcc.c
@@ -873,6 +873,9 @@ static const struct of_device_id mchp_i2
 	{
 		.compatible = "microchip,sam9x60-i2smcc",
 	},
 +	{
 +		.compatible = "microchip,sama7g5-i2smcc",
 +	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
--- a/target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch
+++ b/target/linux/at91/patches-5.10/151-ASoC-mchp-i2s-mcc-Add-multi-channel-support-for-I2S-.patch
@ -1,113 +0,0 @@
 From 5bef4e8125d09443b5486971d5550ed285cde4b1 Mon Sep 17 00:00:00 2001
 From: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Date: Mon, 1 Mar 2021 19:09:01 +0200
 Subject: [PATCH 151/247] ASoC: mchp-i2s-mcc: Add multi-channel support for I2S
 and LEFT_J formats
 The latest I2S-MCC available in SAMA7G5 supports multi-channel for I2S and
 Left-Justified formats. For this, the new version uses 8 (4 * 2) input and
 output pins, with each pin being responsible for 2 channels. This sums up
 to a total of 8 channels for synchronous capture and playback.
 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20210301170905.835091-4-codrin.ciubotariu@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/mchp-i2s-mcc.c | 38 ++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 --- a/sound/soc/atmel/mchp-i2s-mcc.c
 +++ b/sound/soc/atmel/mchp-i2s-mcc.c
@@ -16,6 +16,7 @@
 #include <linux/clk.h>
 #include <linux/mfd/syscon.h>
 #include <linux/lcm.h>
 +#include <linux/of_device.h>
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -225,6 +226,10 @@ static const struct regmap_config mchp_i
 	.max_register = MCHP_I2SMCC_VERSION,
 };
 +struct mchp_i2s_mcc_soc_data {
 +	unsigned int	data_pin_pair_num;
 +};
 +
 struct mchp_i2s_mcc_dev {
 	struct wait_queue_head			wq_txrdy;
 	struct wait_queue_head			wq_rxrdy;
@@ -232,6 +237,7 @@ struct mchp_i2s_mcc_dev {
 	struct regmap				*regmap;
 	struct clk				*pclk;
 	struct clk				*gclk;
 +	const struct mchp_i2s_mcc_soc_data	*soc;
 	struct snd_dmaengine_dai_dma_data	playback;
 	struct snd_dmaengine_dai_dma_data	capture;
 	unsigned int				fmt;
@@ -549,6 +555,17 @@ static int mchp_i2s_mcc_hw_params(struct
 	}
 	if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
 +		/* for I2S and LEFT_J one pin is needed for every 2 channels */
 +		if (channels > dev->soc->data_pin_pair_num * 2) {
 +			dev_err(dev->dev,
 +				"unsupported number of audio channels: %d\n",
 +				channels);
 +			return -EINVAL;
 +		}
 +
 +		/* enable for interleaved format */
 +		mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR;
 +
 		switch (channels) {
 		case 1:
 			if (is_playback)
@@ -558,6 +575,12 @@ static int mchp_i2s_mcc_hw_params(struct
 			break;
 		case 2:
 			break;
 +		case 4:
 +			mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1;
 +			break;
 +		case 8:
 +			mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2;
 +			break;
 		default:
 			dev_err(dev->dev, "unsupported number of audio channels\n");
 			return -EINVAL;
@@ -869,12 +892,22 @@ static const struct snd_soc_component_dr
 };
 #ifdef CONFIG_OF
 +static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = {
 +	.data_pin_pair_num = 1,
 +};
 +
 +static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {
 +	.data_pin_pair_num = 4,
 +};
 +
 static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
 	{
 		.compatible = "microchip,sam9x60-i2smcc",
 +		.data = &mchp_i2s_mcc_sam9x60,
 	},
 	{
 		.compatible = "microchip,sama7g5-i2smcc",
 +		.data = &mchp_i2s_mcc_sama7g5,
 	},
 	{ /* sentinel */ }
 };
@@ -932,6 +965,11 @@ static int mchp_i2s_mcc_probe(struct pla
 		dev->gclk = NULL;
 	}
 +	dev->soc = of_device_get_match_data(&pdev->dev);
 +	if (!dev->soc) {
 +		dev_err(&pdev->dev, "failed to get soc data\n");
 +		return -ENODEV;
 +	}
 	dev->dev = &pdev->dev;
 	dev->regmap = regmap;
 	platform_set_drvdata(pdev, dev);
--- a/target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch
+++ b/target/linux/at91/patches-5.10/152-ASoC-mchp-i2s-mcc-Add-support-to-select-TDM-pins.patch
@ -1,108 +0,0 @@
 From 2bbdc5b38603384996271a8817b0578a2360af2f Mon Sep 17 00:00:00 2001
 From: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Date: Mon, 1 Mar 2021 19:09:03 +0200
 Subject: [PATCH 152/247] ASoC: mchp-i2s-mcc: Add support to select TDM pins
 SAMA7G5's I2S-MCC has 4 pairs of DIN/DOUT pins. Since TDM only uses a
 single pair of pins for synchronous capture and playback, the controller
 needs to be told which of the pair is connected. This can be mentioned
 using the "microchip,tdm-data-pair" property from DT. The property is
 optional, useful only if TDM is used. If it's missing, DIN/DOUT 0 pins
 will be used by default.
 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20210301170905.835091-6-codrin.ciubotariu@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/mchp-i2s-mcc.c | 52 +++++++++++++++++++++++++++++++---
 1 file changed, 48 insertions(+), 4 deletions(-)
 --- a/sound/soc/atmel/mchp-i2s-mcc.c
 +++ b/sound/soc/atmel/mchp-i2s-mcc.c
@@ -100,6 +100,8 @@
 #define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT	(7 << 1)
 #define MCHP_I2SMCC_MRA_WIRECFG_MASK		GENMASK(5, 4)
 +#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin)	(((pin) << 4) & \
 +						 MCHP_I2SMCC_MRA_WIRECFG_MASK)
 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0	(0 << 4)
 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1	(1 << 4)
 #define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2	(2 << 4)
@@ -245,6 +247,7 @@ struct mchp_i2s_mcc_dev {
 	unsigned int				frame_length;
 	int					tdm_slots;
 	int					channels;
 +	u8					tdm_data_pair;
 	unsigned int				gclk_use:1;
 	unsigned int				gclk_running:1;
 	unsigned int				tx_rdy:1;
@@ -589,6 +592,8 @@ static int mchp_i2s_mcc_hw_params(struct
 		if (!frame_length)
 			frame_length = 2 * params_physical_width(params);
 	} else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {
 +		mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair);
 +
 		if (dev->tdm_slots) {
 			if (channels % 2 && channels * 2 <= dev->tdm_slots) {
 				/*
@@ -914,6 +919,45 @@ static const struct of_device_id mchp_i2
 MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);
 #endif
 +static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev,
 +				       struct mchp_i2s_mcc_dev *dev)
 +{
 +	int err;
 +
 +	if (!dev->soc) {
 +		dev_err(&pdev->dev, "failed to get soc data\n");
 +		return -ENODEV;
 +	}
 +
 +	if (dev->soc->data_pin_pair_num == 1)
 +		return 0;
 +
 +	err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair",
 +				  &dev->tdm_data_pair);
 +	if (err < 0 && err != -EINVAL) {
 +		dev_err(&pdev->dev,
 +			"bad property data for 'microchip,tdm-data-pair': %d",
 +			err);
 +		return err;
 +	}
 +	if (err == -EINVAL) {
 +		dev_info(&pdev->dev,
 +			 "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n");
 +		dev->tdm_data_pair = 0;
 +	} else {
 +		if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) {
 +			dev_err(&pdev->dev,
 +				"invalid value for 'microchip,tdm-data-pair': %d\n",
 +				dev->tdm_data_pair);
 +			return -EINVAL;
 +		}
 +		dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n",
 +			dev->tdm_data_pair);
 +	}
 +
 +	return 0;
 +}
 +
 static int mchp_i2s_mcc_probe(struct platform_device *pdev)
 {
 	struct mchp_i2s_mcc_dev *dev;
@@ -966,10 +1010,10 @@ static int mchp_i2s_mcc_probe(struct pla
 	}
 	dev->soc = of_device_get_match_data(&pdev->dev);
 -	if (!dev->soc) {
 -		dev_err(&pdev->dev, "failed to get soc data\n");
 -		return -ENODEV;
 -	}
 +	err = mchp_i2s_mcc_soc_data_parse(pdev, dev);
 +	if (err < 0)
 +		return err;
 +
 	dev->dev = &pdev->dev;
 	dev->regmap = regmap;
 	platform_set_drvdata(pdev, dev);
--- a/target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch
+++ b/target/linux/at91/patches-5.10/153-ASoC-mchp-i2s-mcc-Add-FIFOs-support.patch
@ -1,187 +0,0 @@
 From 36bb4f0ab8e7ef69cc11d4d888aa898223b0e901 Mon Sep 17 00:00:00 2001
 From: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Date: Mon, 1 Mar 2021 19:09:04 +0200
 Subject: [PATCH 153/247] ASoC: mchp-i2s-mcc: Add FIFOs support
 I2S-MCC found on SAMA7G5 includes 2 FIFOs (capture and playback). When
 FIFOs are enabled, bits I2SMCC_ISRA.TXLRDYx and I2SMCC_ISRA.TXRRDYx must
 not be used. Bits I2SMCC_ISRB.TXFFRDY and I2SMCC_ISRB.RXFFRDY must be used
 instead.
 Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20210301170905.835091-7-codrin.ciubotariu@microchip.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/mchp-i2s-mcc.c | 76 +++++++++++++++++++++++++---------
 1 file changed, 56 insertions(+), 20 deletions(-)
 --- a/sound/soc/atmel/mchp-i2s-mcc.c
 +++ b/sound/soc/atmel/mchp-i2s-mcc.c
@@ -176,7 +176,7 @@
  */
 #define MCHP_I2SMCC_MRB_CRAMODE_REGULAR		(1 << 0)
 -#define MCHP_I2SMCC_MRB_FIFOEN			BIT(1)
 +#define MCHP_I2SMCC_MRB_FIFOEN			BIT(4)
 #define MCHP_I2SMCC_MRB_DMACHUNK_MASK		GENMASK(9, 8)
 #define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \
@@ -230,6 +230,7 @@ static const struct regmap_config mchp_i
 struct mchp_i2s_mcc_soc_data {
 	unsigned int	data_pin_pair_num;
 +	bool		has_fifo;
 };
 struct mchp_i2s_mcc_dev {
@@ -257,7 +258,7 @@ struct mchp_i2s_mcc_dev {
 static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)
 {
 	struct mchp_i2s_mcc_dev *dev = dev_id;
 -	u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0;
 +	u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0;
 	irqreturn_t ret = IRQ_NONE;
 	regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);
@@ -275,24 +276,36 @@ static irqreturn_t mchp_i2s_mcc_interrup
 	 * Tx/Rx ready interrupts are enabled when stopping only, to assure
 	 * availability and to disable clocks if necessary
 	 */
 -	idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
 -			    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
 -	if (idra)
 +	if (dev->soc->has_fifo) {
 +		idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY |
 +				    MCHP_I2SMCC_INT_RXFFRDY);
 +	} else {
 +		idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |
 +				    MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
 +	}
 +	if (idra || idrb)
 		ret = IRQ_HANDLED;
 -	if ((imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
 -	    (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
 -	    (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) {
 +	if ((!dev->soc->has_fifo &&
 +	     (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&
 +	     (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==
 +	     (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) ||
 +	    (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) {
 		dev->tx_rdy = 1;
 		wake_up_interruptible(&dev->wq_txrdy);
 	}
 -	if ((imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
 -	    (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
 -	    (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) {
 +	if ((!dev->soc->has_fifo &&
 +	     (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&
 +	     (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==
 +	     (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) ||
 +	    (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) {
 		dev->rx_rdy = 1;
 		wake_up_interruptible(&dev->wq_rxrdy);
 	}
 -	regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
 +	if (dev->soc->has_fifo)
 +		regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb);
 +	else
 +		regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);
 	return ret;
 }
@@ -664,6 +677,10 @@ static int mchp_i2s_mcc_hw_params(struct
 		}
 	}
 +	/* enable FIFO if available */
 +	if (dev->soc->has_fifo)
 +		mrb |= MCHP_I2SMCC_MRB_FIFOEN;
 +
 	/*
 	 * If we are already running, the wanted setup must be
 	 * the same with the one that's currently ongoing
@@ -726,8 +743,13 @@ static int mchp_i2s_mcc_hw_free(struct s
 		if (err == 0) {
 			dev_warn_once(dev->dev,
 				      "Timeout waiting for Tx ready\n");
 -			regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
 -				     MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
 +			if (dev->soc->has_fifo)
 +				regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
 +					     MCHP_I2SMCC_INT_TXFFRDY);
 +			else
 +				regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
 +					     MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));
 +
 			dev->tx_rdy = 1;
 		}
 	} else {
@@ -737,8 +759,12 @@ static int mchp_i2s_mcc_hw_free(struct s
 		if (err == 0) {
 			dev_warn_once(dev->dev,
 				      "Timeout waiting for Rx ready\n");
 -			regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
 -				     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
 +			if (dev->soc->has_fifo)
 +				regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,
 +					     MCHP_I2SMCC_INT_RXFFRDY);
 +			else
 +				regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,
 +					     MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));
 			dev->rx_rdy = 1;
 		}
 	}
@@ -765,7 +791,7 @@ static int mchp_i2s_mcc_trigger(struct s
 	struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);
 	bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 	u32 cr = 0;
 -	u32 iera = 0;
 +	u32 iera = 0, ierb = 0;
 	u32 sr;
 	int err;
@@ -789,7 +815,10 @@ static int mchp_i2s_mcc_trigger(struct s
 			 * Enable Tx Ready interrupts on all channels
 			 * to assure all data is sent
 			 */
 -			iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
 +			if (dev->soc->has_fifo)
 +				ierb = MCHP_I2SMCC_INT_TXFFRDY;
 +			else
 +				iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);
 		} else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {
 			cr = MCHP_I2SMCC_CR_RXDIS;
 			dev->rx_rdy = 0;
@@ -797,7 +826,10 @@ static int mchp_i2s_mcc_trigger(struct s
 			 * Enable Rx Ready interrupts on all channels
 			 * to assure all data is received
 			 */
 -			iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
 +			if (dev->soc->has_fifo)
 +				ierb = MCHP_I2SMCC_INT_RXFFRDY;
 +			else
 +				iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);
 		}
 		break;
 	default:
@@ -815,7 +847,10 @@ static int mchp_i2s_mcc_trigger(struct s
 		}
 	}
 -	regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
 +	if (dev->soc->has_fifo)
 +		regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb);
 +	else
 +		regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);
 	regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);
 	return 0;
@@ -903,6 +938,7 @@ static struct mchp_i2s_mcc_soc_data mchp
 static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {
 	.data_pin_pair_num = 4,
 +	.has_fifo = true,
 };
 static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {
--- a/target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch
+++ b/target/linux/at91/patches-5.10/154-pinctrl-at91-pio4-Fix-slew-rate-disablement.patch
@ -1,49 +0,0 @@
 From dc07cbae6e96843d26e8f10b16e901620bd16462 Mon Sep 17 00:00:00 2001
 From: Tudor Ambarus <tudor.ambarus@microchip.com>
 Date: Fri, 9 Apr 2021 11:25:22 +0300
 Subject: [PATCH 154/247] pinctrl: at91-pio4: Fix slew rate disablement
 The slew rate was enabled by default for each configuration of the
 pin. In case the pin had more than one configuration, even if
 we set the slew rate as disabled in the device tree, the next pin
 configuration would set again the slew rate enabled by default,
 overwriting the slew rate disablement.
 Instead of enabling the slew rate by default for each pin configuration,
 enable the slew rate by default just once per pin, regardless of the
 number of configurations. This way the slew rate disablement will also
 work for cases where pins have multiple configurations.
 Fixes: c709135e576b ("pinctrl: at91-pio4: add support for slew-rate")
 Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
 Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
 Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
 Link: https://lore.kernel.org/r/20210409082522.625168-1-tudor.ambarus@microchip.com
 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 ---
 drivers/pinctrl/pinctrl-at91-pio4.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
 --- a/drivers/pinctrl/pinctrl-at91-pio4.c
 +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -801,6 +801,10 @@ static int atmel_conf_pin_config_group_s
 	conf = atmel_pin_config_read(pctldev, pin_id);
 +	/* Keep slew rate enabled by default. */
 +	if (atmel_pioctrl->slew_rate_support)
 +		conf |= ATMEL_PIO_SR_MASK;
 +
 	for (i = 0; i < num_configs; i++) {
 		unsigned int param = pinconf_to_config_param(configs[i]);
 		unsigned int arg = pinconf_to_config_argument(configs[i]);
@@ -808,10 +812,6 @@ static int atmel_conf_pin_config_group_s
 		dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
 			__func__, pin_id, configs[i]);
 -		/* Keep slew rate enabled by default. */
 -		if (atmel_pioctrl->slew_rate_support)
 -			conf |= ATMEL_PIO_SR_MASK;
 -
 		switch (param) {
 		case PIN_CONFIG_BIAS_DISABLE:
 			conf &= (~ATMEL_PIO_PUEN_MASK);
--- a/target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch
+++ b/target/linux/at91/patches-5.10/155-media-atmel-properly-get-pm_runtime.patch
@ -1,159 +0,0 @@
 From c7660cc977621c4a14d870d523918df067f0db39 Mon Sep 17 00:00:00 2001
 From: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 Date: Fri, 23 Apr 2021 16:47:42 +0200
 Subject: [PATCH 155/247] media: atmel: properly get pm_runtime
 There are several issues in the way the atmel driver handles
 pm_runtime_get_sync():
 - it doesn't check return codes;
 - it doesn't properly decrement the usage_count on all places;
 - it starts streaming even if pm_runtime_get_sync() fails.
 - while it tries to get pm_runtime at the clock enable logic,
  it doesn't check if the operation was suceeded.
 Replace all occurrences of it to use the new kAPI:
 pm_runtime_resume_and_get(), which ensures that, if the
 return code is not negative, the usage_count was incremented.
 With that, add additional checks when this is called, in order
 to ensure that errors will be properly addressed.
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 30 ++++++++++++++-----
 drivers/media/platform/atmel/atmel-isi.c      | 19 +++++++++---
 2 files changed, 38 insertions(+), 11 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -294,9 +294,13 @@ static int isc_wait_clk_stable(struct cl
 static int isc_clk_prepare(struct clk_hw *hw)
 {
 	struct isc_clk *isc_clk = to_isc_clk(hw);
 +	int ret;
 -	if (isc_clk->id == ISC_ISPCK)
 -		pm_runtime_get_sync(isc_clk->dev);
 +	if (isc_clk->id == ISC_ISPCK) {
 +		ret = pm_runtime_resume_and_get(isc_clk->dev);
 +		if (ret < 0)
 +			return ret;
 +	}
 	return isc_wait_clk_stable(hw);
 }
@@ -353,9 +357,13 @@ static int isc_clk_is_enabled(struct clk
 {
 	struct isc_clk *isc_clk = to_isc_clk(hw);
 	u32 status;
 +	int ret;
 -	if (isc_clk->id == ISC_ISPCK)
 -		pm_runtime_get_sync(isc_clk->dev);
 +	if (isc_clk->id == ISC_ISPCK) {
 +		ret = pm_runtime_resume_and_get(isc_clk->dev);
 +		if (ret < 0)
 +			return 0;
 +	}
 	regmap_read(isc_clk->regmap, ISC_CLKSR, &status);
@@ -807,7 +815,12 @@ static int isc_start_streaming(struct vb
 		goto err_start_stream;
 	}
 -	pm_runtime_get_sync(isc->dev);
 +	ret = pm_runtime_resume_and_get(isc->dev);
 +	if (ret < 0) {
 +		v4l2_err(&isc->v4l2_dev, "RPM resume failed in subdev %d\n",
 +			 ret);
 +		goto err_pm_get;
 +	}
 	ret = isc_configure(isc);
 	if (unlikely(ret))
@@ -838,7 +851,7 @@ static int isc_start_streaming(struct vb
 err_configure:
 	pm_runtime_put_sync(isc->dev);
 -
 +err_pm_get:
 	v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
 err_start_stream:
@@ -1809,6 +1822,7 @@ static void isc_awb_work(struct work_str
 	u32 baysel;
 	unsigned long flags;
 	u32 min, max;
 +	int ret;
 	/* streaming is not active anymore */
 	if (isc->stop)
@@ -1831,7 +1845,9 @@ static void isc_awb_work(struct work_str
 	ctrls->hist_id = hist_id;
 	baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
 -	pm_runtime_get_sync(isc->dev);
 +	ret = pm_runtime_resume_and_get(isc->dev);
 +	if (ret < 0)
 +		return;
 	/*
 	 * only update if we have all the required histograms and controls
 --- a/drivers/media/platform/atmel/atmel-isi.c
 +++ b/drivers/media/platform/atmel/atmel-isi.c
@@ -423,7 +423,9 @@ static int start_streaming(struct vb2_qu
 	struct frame_buffer *buf, *node;
 	int ret;
 -	pm_runtime_get_sync(isi->dev);
 +	ret = pm_runtime_resume_and_get(isi->dev);
 +	if (ret < 0)
 +		return ret;
 	/* Enable stream on the sub device */
 	ret = v4l2_subdev_call(isi->entity.subdev, video, s_stream, 1);
@@ -783,9 +785,10 @@ static int isi_enum_frameintervals(struc
 	return 0;
 }
 -static void isi_camera_set_bus_param(struct atmel_isi *isi)
 +static int isi_camera_set_bus_param(struct atmel_isi *isi)
 {
 	u32 cfg1 = 0;
 +	int ret;
 	/* set bus param for ISI */
 	if (isi->pdata.hsync_act_low)
@@ -802,12 +805,16 @@ static void isi_camera_set_bus_param(str
 	cfg1 |= ISI_CFG1_THMASK_BEATS_16;
 	/* Enable PM and peripheral clock before operate isi registers */
 -	pm_runtime_get_sync(isi->dev);
 +	ret = pm_runtime_resume_and_get(isi->dev);
 +	if (ret < 0)
 +		return ret;
 	isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
 	isi_writel(isi, ISI_CFG1, cfg1);
 	pm_runtime_put(isi->dev);
 +
 +	return 0;
 }
 /* -----------------------------------------------------------------------*/
@@ -1086,7 +1093,11 @@ static int isi_graph_notify_complete(str
 		dev_err(isi->dev, "No supported mediabus format found\n");
 		return ret;
 	}
 -	isi_camera_set_bus_param(isi);
 +	ret = isi_camera_set_bus_param(isi);
 +	if (ret) {
 +		dev_err(isi->dev, "Can't wake up device\n");
 +		return ret;
 +	}
 	ret = isi_set_default_fmt(isi);
 	if (ret) {
--- a/target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch
+++ b/target/linux/at91/patches-5.10/156-media-atmel-atmel-isc-Remove-redundant-assignment-to.patch
@ -1,32 +0,0 @@
 From b074b4695004b793a9199716295cb76da6c41686 Mon Sep 17 00:00:00 2001
 From: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
 Date: Mon, 17 May 2021 12:07:48 +0200
 Subject: [PATCH 156/247] media: atmel: atmel-isc: Remove redundant assignment
 to i
 Variable i is being assigned a value however the assignment is
 never read, so this redundant assignment can be removed.
 Clean up the following clang-analyzer warning:
 drivers/media/platform/atmel/atmel-isc-base.c:975:2: warning: Value
 stored to 'i' is never read [clang-analyzer-deadcode.DeadStores].
 Reported-by: Abaci Robot <abaci@linux.alibaba.com>
 Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 1 -
 1 file changed, 1 deletion(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -972,7 +972,6 @@ static int isc_enum_fmt_vid_cap(struct f
 	index -= ARRAY_SIZE(controller_formats);
 -	i = 0;
 	supported_index = 0;
 	for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
--- a/target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch
+++ b/target/linux/at91/patches-5.10/157-media-atmel-atmel-isc-specialize-gamma-table-into-pr.patch
@ -1,187 +0,0 @@
 From c3f54d192dc7344c5216a3628b67c4bbccbf8c3c Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:56:59 +0200
 Subject: [PATCH 157/247] media: atmel: atmel-isc: specialize gamma table into
 product specific
 Separate the gamma table from the isc base file into the specific sama5d2
 product file.
 Add a pointer to the gamma table and entries count inside the platform
 driver specific struct.
 [hverkuil: made isc_sama5d2_gamma_table static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 47 ++-----------------
 drivers/media/platform/atmel/atmel-isc.h      | 11 +++--
 .../media/platform/atmel/atmel-sama5d2-isc.c  | 45 ++++++++++++++++++
 3 files changed, 56 insertions(+), 47 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -176,48 +176,6 @@ struct isc_format formats_list[] = {
 };
 -/* Gamma table with gamma 1/2.2 */
 -const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = {
 -	/* 0 --> gamma 1/1.8 */
 -	{      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,
 -	  0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
 -	  0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
 -	  0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
 -	  0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
 -	  0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
 -	  0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
 -	  0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
 -	  0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
 -	  0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
 -	  0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
 -
 -	/* 1 --> gamma 1/2 */
 -	{      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,
 -	  0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
 -	  0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
 -	  0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
 -	  0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
 -	  0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
 -	  0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
 -	  0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
 -	  0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
 -	  0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
 -	  0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
 -
 -	/* 2 --> gamma 1/2.2 */
 -	{      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,
 -	  0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
 -	  0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
 -	  0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
 -	  0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
 -	  0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
 -	  0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
 -	  0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
 -	  0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
 -	  0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
 -	  0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
 -};
 -
 #define ISC_IS_FORMAT_RAW(mbus_code) \
 	(((mbus_code) & 0xf000) == 0x3000)
@@ -691,7 +649,7 @@ static void isc_set_pipeline(struct isc_
 	regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
 -	gamma = &isc_gamma_table[ctrls->gamma_index][0];
 +	gamma = &isc->gamma_table[ctrls->gamma_index][0];
 	regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
 	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
@@ -2085,7 +2043,8 @@ static int isc_ctrl_init(struct isc_devi
 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
 -	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2);
 +	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
 +			  isc->gamma_max);
 	isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
 					  V4L2_CID_AUTO_WHITE_BALANCE,
 					  0, 1, 1, 1);
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -186,6 +186,10 @@ struct isc_ctrls {
  *
  * @current_subdev:	current subdevice: the sensor
  * @subdev_entities:	list of subdevice entitites
 + *
 + * @gamma_table:	pointer to the table with gamma values, has
 + *			gamma_max sets of GAMMA_ENTRIES entries each
 + * @gamma_max:		maximum number of sets of inside the gamma_table
  */
 struct isc_device {
 	struct regmap		*regmap;
@@ -244,16 +248,17 @@ struct isc_device {
 		struct v4l2_ctrl	*gr_off_ctrl;
 		struct v4l2_ctrl	*gb_off_ctrl;
 	};
 -};
 -#define GAMMA_MAX	2
 #define GAMMA_ENTRIES	64
 +	/* pointer to the defined gamma table */
 +	const u32	(*gamma_table)[GAMMA_ENTRIES];
 +	u32		gamma_max;
 +};
 #define ATMEL_ISC_NAME "atmel-isc"
 extern struct isc_format formats_list[];
 extern const struct isc_format controller_formats[];
 -extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES];
 extern const struct regmap_config isc_regmap_config;
 extern const struct v4l2_async_notifier_operations isc_async_ops;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -54,6 +54,48 @@
 #define ISC_CLK_MAX_DIV		255
 +/* Gamma table with gamma 1/2.2 */
 +static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 +	/* 0 --> gamma 1/1.8 */
 +	{      0x65,  0x66002F,  0x950025,  0xBB0020,  0xDB001D,  0xF8001A,
 +	  0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012,
 +	  0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F,
 +	  0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E,
 +	  0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C,
 +	  0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B,
 +	  0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A,
 +	  0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A,
 +	  0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A,
 +	  0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009,
 +	  0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 },
 +
 +	/* 1 --> gamma 1/2 */
 +	{      0x7F,  0x800034,  0xB50028,  0xDE0021, 0x100001E, 0x11E001B,
 +	  0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013,
 +	  0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F,
 +	  0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D,
 +	  0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B,
 +	  0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A,
 +	  0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A,
 +	  0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009,
 +	  0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009,
 +	  0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009,
 +	  0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 },
 +
 +	/* 2 --> gamma 1/2.2 */
 +	{      0x99,  0x9B0038,  0xD4002A,  0xFF0023, 0x122001F, 0x141001B,
 +	  0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012,
 +	  0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F,
 +	  0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C,
 +	  0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B,
 +	  0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A,
 +	  0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009,
 +	  0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009,
 +	  0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008,
 +	  0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007,
 +	  0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 },
 +};
 +
 static int isc_parse_dt(struct device *dev, struct isc_device *isc)
 {
 	struct device_node *np = dev->of_node;
@@ -171,6 +213,9 @@ static int atmel_isc_probe(struct platfo
 		return ret;
 	}
 +	isc->gamma_table = isc_sama5d2_gamma_table;
 +	isc->gamma_max = 2;
 +
 	ret = isc_pipeline_init(isc);
 	if (ret)
 		return ret;
--- a/target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch
+++ b/target/linux/at91/patches-5.10/158-media-atmel-atmel-isc-specialize-driver-name-constan.patch
@ -1,70 +0,0 @@
 From 0576e163d93d08a1ed112bd23f40478ef3fd323d Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:00 +0200
 Subject: [PATCH 158/247] media: atmel: atmel-isc: specialize driver name
 constant
 The driver name constant must defined based on product driver, thus moving
 the constant directly where it's required. This will allow each ISC based
 product to define it's own name.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--
 drivers/media/platform/atmel/atmel-isc.h         | 2 --
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++--
 3 files changed, 4 insertions(+), 6 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -909,7 +909,7 @@ static int isc_querycap(struct file *fil
 {
 	struct isc_device *isc = video_drvdata(file);
 -	strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver));
 +	strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
 	strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card));
 	snprintf(cap->bus_info, sizeof(cap->bus_info),
 		 "platform:%s", isc->v4l2_dev.name);
@@ -2261,7 +2261,7 @@ static int isc_async_complete(struct v4l
 	}
 	/* Register video device */
 -	strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name));
 +	strscpy(vdev->name, "microchip-isc", sizeof(vdev->name));
 	vdev->release		= video_device_release_empty;
 	vdev->fops		= &isc_fops;
 	vdev->ioctl_ops		= &isc_ioctl_ops;
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -255,8 +255,6 @@ struct isc_device {
 	u32		gamma_max;
 };
 -#define ATMEL_ISC_NAME "atmel-isc"
 -
 extern struct isc_format formats_list[];
 extern const struct isc_format controller_formats[];
 extern const struct regmap_config isc_regmap_config;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -206,7 +206,7 @@ static int atmel_isc_probe(struct platfo
 		return irq;
 	ret = devm_request_irq(dev, irq, isc_interrupt, 0,
 -			       ATMEL_ISC_NAME, isc);
 +			       "atmel-sama5d2-isc", isc);
 	if (ret < 0) {
 		dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
 			irq, ret);
@@ -378,7 +378,7 @@ static struct platform_driver atmel_isc_
 	.probe	= atmel_isc_probe,
 	.remove	= atmel_isc_remove,
 	.driver	= {
 -		.name		= ATMEL_ISC_NAME,
 +		.name		= "atmel-sama5d2-isc",
 		.pm		= &atmel_isc_dev_pm_ops,
 		.of_match_table = of_match_ptr(atmel_isc_of_match),
 	},
--- a/target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch
+++ b/target/linux/at91/patches-5.10/159-media-atmel-atmel-isc-add-checks-for-limiting-frame-.patch
@ -1,45 +0,0 @@
 From de8fa25cdf3726c83ac0d7b3b1e28bcb6334aadd Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:01 +0200
 Subject: [PATCH 159/247] media: atmel: atmel-isc: add checks for limiting
 frame sizes
 When calling the subdev, certain subdev drivers will overwrite the
 frame size and adding sizes which are beyond the ISC's capabilities.
 Thus we need to ensure the frame size is cropped to the maximum caps.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -1338,6 +1338,12 @@ static int isc_try_fmt(struct isc_device
 	v4l2_fill_pix_format(pixfmt, &format.format);
 +	/* Limit to Atmel ISC hardware capabilities */
 +	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
 +		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
 +	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
 +		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
 +
 	pixfmt->field = V4L2_FIELD_NONE;
 	pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
 	pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height;
@@ -1373,6 +1379,12 @@ static int isc_set_fmt(struct isc_device
 	if (ret < 0)
 		return ret;
 +	/* Limit to Atmel ISC hardware capabilities */
 +	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
 +		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
 +	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
 +		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
 +
 	isc->fmt = *f;
 	if (isc->try_config.sd_format && isc->config.sd_format &&
--- a/target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch
+++ b/target/linux/at91/patches-5.10/160-media-atmel-atmel-isc-specialize-max-width-and-max-h.patch
@ -1,131 +0,0 @@
 From b51819e17260af2ecc152b7dcd61e63bcaa35edf Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:02 +0200
 Subject: [PATCH 160/247] media: atmel: atmel-isc: specialize max width and max
 height
 Move the max width and max height constants to the product specific driver
 and have them in the device struct.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++----------
 drivers/media/platform/atmel/atmel-isc.h      |  9 ++++--
 .../media/platform/atmel/atmel-sama5d2-isc.c  |  7 +++--
 3 files changed, 25 insertions(+), 19 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -1216,8 +1216,8 @@ static void isc_try_fse(struct isc_devic
 	 * just use the maximum ISC can receive.
 	 */
 	if (ret) {
 -		pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH;
 -		pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT;
 +		pad_cfg->try_crop.width = isc->max_width;
 +		pad_cfg->try_crop.height = isc->max_height;
 	} else {
 		pad_cfg->try_crop.width = fse.max_width;
 		pad_cfg->try_crop.height = fse.max_height;
@@ -1294,10 +1294,10 @@ static int isc_try_fmt(struct isc_device
 	isc->try_config.sd_format = sd_fmt;
 	/* Limit to Atmel ISC hardware capabilities */
 -	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
 -		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
 -	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
 -		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
 +	if (pixfmt->width > isc->max_width)
 +		pixfmt->width = isc->max_width;
 +	if (pixfmt->height > isc->max_height)
 +		pixfmt->height = isc->max_height;
 	/*
 	 * The mbus format is the one the subdev outputs.
@@ -1339,10 +1339,10 @@ static int isc_try_fmt(struct isc_device
 	v4l2_fill_pix_format(pixfmt, &format.format);
 	/* Limit to Atmel ISC hardware capabilities */
 -	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
 -		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
 -	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
 -		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
 +	if (pixfmt->width > isc->max_width)
 +		pixfmt->width = isc->max_width;
 +	if (pixfmt->height > isc->max_height)
 +		pixfmt->height = isc->max_height;
 	pixfmt->field = V4L2_FIELD_NONE;
 	pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3;
@@ -1380,10 +1380,10 @@ static int isc_set_fmt(struct isc_device
 		return ret;
 	/* Limit to Atmel ISC hardware capabilities */
 -	if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH)
 -		pixfmt->width = ISC_MAX_SUPPORT_WIDTH;
 -	if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT)
 -		pixfmt->height = ISC_MAX_SUPPORT_HEIGHT;
 +	if (f->fmt.pix.width > isc->max_width)
 +		f->fmt.pix.width = isc->max_width;
 +	if (f->fmt.pix.height > isc->max_height)
 +		f->fmt.pix.height = isc->max_height;
 	isc->fmt = *f;
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -10,9 +10,6 @@
  */
 #ifndef _ATMEL_ISC_H_
 -#define ISC_MAX_SUPPORT_WIDTH   2592
 -#define ISC_MAX_SUPPORT_HEIGHT  1944
 -
 #define ISC_CLK_MAX_DIV		255
 enum isc_clk_id {
@@ -190,6 +187,9 @@ struct isc_ctrls {
  * @gamma_table:	pointer to the table with gamma values, has
  *			gamma_max sets of GAMMA_ENTRIES entries each
  * @gamma_max:		maximum number of sets of inside the gamma_table
 + *
 + * @max_width:		maximum frame width, dependent on the internal RAM
 + * @max_height:		maximum frame height, dependent on the internal RAM
  */
 struct isc_device {
 	struct regmap		*regmap;
@@ -253,6 +253,9 @@ struct isc_device {
 	/* pointer to the defined gamma table */
 	const u32	(*gamma_table)[GAMMA_ENTRIES];
 	u32		gamma_max;
 +
 +	u32		max_width;
 +	u32		max_height;
 };
 extern struct isc_format formats_list[];
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -49,8 +49,8 @@
 #include "atmel-isc-regs.h"
 #include "atmel-isc.h"
 -#define ISC_MAX_SUPPORT_WIDTH   2592
 -#define ISC_MAX_SUPPORT_HEIGHT  1944
 +#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH   2592
 +#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT  1944
 #define ISC_CLK_MAX_DIV		255
@@ -216,6 +216,9 @@ static int atmel_isc_probe(struct platfo
 	isc->gamma_table = isc_sama5d2_gamma_table;
 	isc->gamma_max = 2;
 +	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
 +	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
 +
 	ret = isc_pipeline_init(isc);
 	if (ret)
 		return ret;
--- a/target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch
+++ b/target/linux/at91/patches-5.10/161-media-atmel-atmel-isc-specialize-dma-cfg.patch
@ -1,60 +0,0 @@
 From c42305f52560a1be6fc25a2f23579c7b323de654 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:03 +0200
 Subject: [PATCH 161/247] media: atmel: atmel-isc: specialize dma cfg
 The dma configuration (DCFG) is specific to the product.
 Move this configuration in the product specific driver, and add the
 field inside the driver struct.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 3 +--
 drivers/media/platform/atmel/atmel-isc.h         | 2 ++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++
 3 files changed, 6 insertions(+), 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -724,8 +724,7 @@ static int isc_configure(struct isc_devi
 	rlp_mode = isc->config.rlp_cfg_mode;
 	pipeline = isc->config.bits_pipeline;
 -	dcfg = isc->config.dcfg_imode |
 -		       ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
 +	dcfg = isc->config.dcfg_imode | isc->dcfg;
 	pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
 	mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -149,6 +149,7 @@ struct isc_ctrls {
  * @hclock:		Hclock clock input (refer datasheet)
  * @ispck:		iscpck clock (refer datasheet)
  * @isc_clks:		ISC clocks
 + * @dcfg:		DMA master configuration, architecture dependent
  *
  * @dev:		Registered device driver
  * @v4l2_dev:		v4l2 registered device
@@ -196,6 +197,7 @@ struct isc_device {
 	struct clk		*hclock;
 	struct clk		*ispck;
 	struct isc_clk		isc_clks[2];
 +	u32			dcfg;
 	struct device		*dev;
 	struct v4l2_device	v4l2_dev;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -219,6 +219,9 @@ static int atmel_isc_probe(struct platfo
 	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
 +	/* sama5d2-isc - 8 bits per beat */
 +	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
 +
 	ret = isc_pipeline_init(isc);
 	if (ret)
 		return ret;
--- a/target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch
+++ b/target/linux/at91/patches-5.10/162-media-atmel-atmel-isc-extract-CSC-submodule-config-i.patch
@ -1,94 +0,0 @@
 From 6ccda3cf6a102ac4f6e21386d0dd0fedfb066525 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:04 +0200
 Subject: [PATCH 162/247] media: atmel: atmel-isc: extract CSC submodule config
 into separate function
 The CSC submodule is a part of the atmel-isc pipeline, and stands for
 Color Space Conversion. It is used to apply a matrix transformation to
 RGB pixels to convert them to the YUV components.
 The CSC submodule should be initialized in the product specific driver
 as it's product specific. Other products can implement it differently.
 [hverkuil: made isc_sama5d2_config_csc static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    |  8 +-------
 drivers/media/platform/atmel/atmel-isc.h         |  7 +++++++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++
 3 files changed, 23 insertions(+), 7 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -654,13 +654,7 @@ static void isc_set_pipeline(struct isc_
 	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 -	/* Convert RGB to YUV */
 -	regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
 -	regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
 -	regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
 -	regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
 -	regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
 -	regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
 +	isc->config_csc(isc);
 	regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
 	regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -191,6 +191,9 @@ struct isc_ctrls {
  *
  * @max_width:		maximum frame width, dependent on the internal RAM
  * @max_height:		maximum frame height, dependent on the internal RAM
 + *
 + * @config_csc:		pointer to a function that initializes product
 + *			specific CSC module
  */
 struct isc_device {
 	struct regmap		*regmap;
@@ -258,6 +261,10 @@ struct isc_device {
 	u32		max_width;
 	u32		max_height;
 +
 +	struct {
 +		void (*config_csc)(struct isc_device *isc);
 +	};
 };
 extern struct isc_format formats_list[];
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -54,6 +54,19 @@
 #define ISC_CLK_MAX_DIV		255
 +static void isc_sama5d2_config_csc(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	/* Convert RGB to YUV */
 +	regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
 +	regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
 +	regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
 +	regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
 +	regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
 +	regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -219,6 +232,8 @@ static int atmel_isc_probe(struct platfo
 	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
 +	isc->config_csc = isc_sama5d2_config_csc;
 +
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch
+++ b/target/linux/at91/patches-5.10/163-media-atmel-atmel-isc-base-add-id-to-clock-debug-mes.patch
@ -1,28 +0,0 @@
 From 19dd7c72c6c457c147133a7dad8ab28d35538f99 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:05 +0200
 Subject: [PATCH 163/247] media: atmel: atmel-isc-base: add id to clock debug
 message
 Add the clock id to the debug message regarding clock setup
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -281,8 +281,8 @@ static int isc_clk_enable(struct clk_hw
 	unsigned long flags;
 	unsigned int status;
 -	dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n",
 -		__func__, isc_clk->div, isc_clk->parent_id);
 +	dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n",
 +		__func__, id, isc_clk->div, isc_clk->parent_id);
 	spin_lock_irqsave(&isc_clk->lock, flags);
 	regmap_update_bits(regmap, ISC_CLKCFG,
--- a/target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch
+++ b/target/linux/at91/patches-5.10/164-media-atmel-atmel-isc-create-register-offsets-struct.patch
@ -1,115 +0,0 @@
 From 7a1b082cd81a2496e2687cee7ea1ef04a3020f48 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:06 +0200
 Subject: [PATCH 164/247] media: atmel: atmel-isc: create register offsets
 struct
 Create a struct that holds register offsets that are product specific.
 Add initially the CSC register.
 This allows each product that contains a variant of the ISC to add their
 own register offset.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c |  2 +-
 drivers/media/platform/atmel/atmel-isc-regs.h |  3 +++
 drivers/media/platform/atmel/atmel-isc.h      | 12 +++++++++++
 .../media/platform/atmel/atmel-sama5d2-isc.c  | 20 +++++++++++++------
 4 files changed, 30 insertions(+), 7 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -2326,7 +2326,7 @@ int isc_pipeline_init(struct isc_device
 		REG_FIELD(ISC_GAM_CTRL, 1, 1),
 		REG_FIELD(ISC_GAM_CTRL, 2, 2),
 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
 -		REG_FIELD(ISC_CSC_CTRL, 0, 0),
 +		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
 		REG_FIELD(ISC_CBC_CTRL, 0, 0),
 		REG_FIELD(ISC_SUB422_CTRL, 0, 0),
 		REG_FIELD(ISC_SUB420_CTRL, 0, 0),
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -153,6 +153,9 @@
 /* ISC_Gamma Correction Green Entry Register */
 #define ISC_GAM_RENTRY	0x00000298
 +/* Offset for CSC register specific to sama5d2 product */
 +#define ISC_SAMA5D2_CSC_OFFSET	0
 +
 /* Color Space Conversion Control Register */
 #define ISC_CSC_CTRL    0x00000398
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -144,6 +144,14 @@ struct isc_ctrls {
 #define ISC_PIPE_LINE_NODE_NUM	11
 /*
 + * struct isc_reg_offsets - ISC device register offsets
 + * @csc:		Offset for the CSC register
 + */
 +struct isc_reg_offsets {
 +	u32 csc;
 +};
 +
 +/*
  * struct isc_device - ISC device driver data/config struct
  * @regmap:		Register map
  * @hclock:		Hclock clock input (refer datasheet)
@@ -194,6 +202,8 @@ struct isc_ctrls {
  *
  * @config_csc:		pointer to a function that initializes product
  *			specific CSC module
 + *
 + * @offsets:		struct holding the product specific register offsets
  */
 struct isc_device {
 	struct regmap		*regmap;
@@ -265,6 +275,8 @@ struct isc_device {
 	struct {
 		void (*config_csc)(struct isc_device *isc);
 	};
 +
 +	struct isc_reg_offsets		offsets;
 };
 extern struct isc_format formats_list[];
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -59,12 +59,18 @@ static void isc_sama5d2_config_csc(struc
 	struct regmap *regmap = isc->regmap;
 	/* Convert RGB to YUV */
 -	regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16));
 -	regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16));
 -	regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16));
 -	regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16));
 -	regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16));
 -	regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16));
 +	regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,
 +		     0x42 | (0x81 << 16));
 +	regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,
 +		     0x19 | (0x10 << 16));
 +	regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,
 +		     0xFDA | (0xFB6 << 16));
 +	regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,
 +		     0x70 | (0x80 << 16));
 +	regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,
 +		     0x70 | (0xFA2 << 16));
 +	regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,
 +		     0xFEE | (0x80 << 16));
 }
 /* Gamma table with gamma 1/2.2 */
@@ -234,6 +240,8 @@ static int atmel_isc_probe(struct platfo
 	isc->config_csc = isc_sama5d2_config_csc;
 +	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
 +
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch
+++ b/target/linux/at91/patches-5.10/165-media-atmel-atmel-isc-extract-CBC-submodule-config-i.patch
@ -1,80 +0,0 @@
 From aa31e58d80d233385fa3b972e6b85f293e2a9093 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:07 +0200
 Subject: [PATCH 165/247] media: atmel: atmel-isc: extract CBC submodule config
 into separate function
 The CBC submodule is a part of the atmel-isc pipeline, and stands for
 Contrast Brightness Control. It is used to apply gains and offsets to the
 luma (Y) and chroma (U, V) components of the YUV elements.
 The CBC submodule should be initialized in the product specific driver
 as it's product specific. Other products can implement it differently
 [hverkuil: made isc_sama5d2_config_cbc static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 4 +---
 drivers/media/platform/atmel/atmel-isc.h         | 3 +++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++
 3 files changed, 13 insertions(+), 3 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -655,9 +655,7 @@ static void isc_set_pipeline(struct isc_
 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 	isc->config_csc(isc);
 -
 -	regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness);
 -	regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast);
 +	isc->config_cbc(isc);
 }
 static int isc_update_profile(struct isc_device *isc)
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -202,6 +202,8 @@ struct isc_reg_offsets {
  *
  * @config_csc:		pointer to a function that initializes product
  *			specific CSC module
 + * @config_cbc:		pointer to a function that initializes product
 + *			specific CBC module
  *
  * @offsets:		struct holding the product specific register offsets
  */
@@ -274,6 +276,7 @@ struct isc_device {
 	struct {
 		void (*config_csc)(struct isc_device *isc);
 +		void (*config_cbc)(struct isc_device *isc);
 	};
 	struct isc_reg_offsets		offsets;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -73,6 +73,14 @@ static void isc_sama5d2_config_csc(struc
 		     0xFEE | (0x80 << 16));
 }
 +static void isc_sama5d2_config_cbc(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness);
 +	regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast);
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -239,6 +247,7 @@ static int atmel_isc_probe(struct platfo
 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
 	isc->config_csc = isc_sama5d2_config_csc;
 +	isc->config_cbc = isc_sama5d2_config_cbc;
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
--- a/target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch
+++ b/target/linux/at91/patches-5.10/166-media-atmel-atmel-isc-add-CBC-to-the-reg-offsets-str.patch
@ -1,82 +0,0 @@
 From 52e4b779ae1af3e322d0c673375dcd51315739d4 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:08 +0200
 Subject: [PATCH 166/247] media: atmel: atmel-isc: add CBC to the reg offsets
 struct
 The CBC submodule is a part of the atmel-isc pipeline, and stands for
 Contrast Brightness Control. It is used to apply gains and offsets to the
 luma (Y) and chroma (U, V) components of the YUV elements.
 Add cbc to the reg offsets struct. This will allow different products
 to have a different reg offset for this particular module.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 2 +-
 drivers/media/platform/atmel/atmel-isc-regs.h    | 3 +++
 drivers/media/platform/atmel/atmel-isc.h         | 2 ++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++--
 4 files changed, 11 insertions(+), 3 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -2325,7 +2325,7 @@ int isc_pipeline_init(struct isc_device
 		REG_FIELD(ISC_GAM_CTRL, 2, 2),
 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
 		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
 -		REG_FIELD(ISC_CBC_CTRL, 0, 0),
 +		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
 		REG_FIELD(ISC_SUB422_CTRL, 0, 0),
 		REG_FIELD(ISC_SUB420_CTRL, 0, 0),
 	};
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -177,6 +177,9 @@
 /* Color Space Conversion CRB OCR Register */
 #define ISC_CSC_CRB_OCR	0x000003b0
 +/* Offset for CBC register specific to sama5d2 product */
 +#define ISC_SAMA5D2_CBC_OFFSET	0
 +
 /* Contrast And Brightness Control Register */
 #define ISC_CBC_CTRL    0x000003b4
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -146,9 +146,11 @@ struct isc_ctrls {
 /*
  * struct isc_reg_offsets - ISC device register offsets
  * @csc:		Offset for the CSC register
 + * @cbc:		Offset for the CBC register
  */
 struct isc_reg_offsets {
 	u32 csc;
 +	u32 cbc;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -77,8 +77,10 @@ static void isc_sama5d2_config_cbc(struc
 {
 	struct regmap *regmap = isc->regmap;
 -	regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness);
 -	regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast);
 +	regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc,
 +		     isc->ctrls.brightness);
 +	regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc,
 +		     isc->ctrls.contrast);
 }
 /* Gamma table with gamma 1/2.2 */
@@ -250,6 +252,7 @@ static int atmel_isc_probe(struct platfo
 	isc->config_cbc = isc_sama5d2_config_cbc;
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
 +	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch
+++ b/target/linux/at91/patches-5.10/167-media-atmel-atmel-isc-add-SUB422-and-SUB420-to-regis.patch
@ -1,80 +0,0 @@
 From aebb741058a63c3493f4139d11d6f290d5691e9b Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:09 +0200
 Subject: [PATCH 167/247] media: atmel: atmel-isc: add SUB422 and SUB420 to
 register offsets
 The SUB submodules are a part of the atmel-isc pipeline, and stand for
 Subsampling. They are used to subsample the original YUV 4:4:4 pixel ratio
 aspect to either 4:2:2 or 4:2:0.
 Add sub420 and sub422 to the reg offsets struct.
 This will allow different products to have a different reg offset for these
 particular modules.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--
 drivers/media/platform/atmel/atmel-isc-regs.h    | 4 ++++
 drivers/media/platform/atmel/atmel-isc.h         | 4 ++++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++
 4 files changed, 12 insertions(+), 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -2326,8 +2326,8 @@ int isc_pipeline_init(struct isc_device
 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
 		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
 		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
 -		REG_FIELD(ISC_SUB422_CTRL, 0, 0),
 -		REG_FIELD(ISC_SUB420_CTRL, 0, 0),
 +		REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
 +		REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
 	};
 	for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -194,9 +194,13 @@
 #define ISC_CBC_CONTRAST	0x000003c0
 #define ISC_CBC_CONTRAST_MASK	GENMASK(11, 0)
 +/* Offset for SUB422 register specific to sama5d2 product */
 +#define ISC_SAMA5D2_SUB422_OFFSET	0
 /* Subsampling 4:4:4 to 4:2:2 Control Register */
 #define ISC_SUB422_CTRL 0x000003c4
 +/* Offset for SUB420 register specific to sama5d2 product */
 +#define ISC_SAMA5D2_SUB420_OFFSET	0
 /* Subsampling 4:2:2 to 4:2:0 Control Register */
 #define ISC_SUB420_CTRL 0x000003cc
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -147,10 +147,14 @@ struct isc_ctrls {
  * struct isc_reg_offsets - ISC device register offsets
  * @csc:		Offset for the CSC register
  * @cbc:		Offset for the CBC register
 + * @sub422:		Offset for the SUB422 register
 + * @sub420:		Offset for the SUB420 register
  */
 struct isc_reg_offsets {
 	u32 csc;
 	u32 cbc;
 +	u32 sub422;
 +	u32 sub420;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -253,6 +253,8 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
 +	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
 +	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch
+++ b/target/linux/at91/patches-5.10/168-media-atmel-atmel-isc-add-RLP-to-register-offsets.patch
@ -1,74 +0,0 @@
 From b432a8b0fc88de5b49236482053d8d372c68ee55 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:10 +0200
 Subject: [PATCH 168/247] media: atmel: atmel-isc: add RLP to register offsets
 The RLP submodule is a part of the atmel-isc pipeline, and stands for
 Rounding,Limiting and Packaging. It used to extract specific data from the
 ISC pipeline. For example if we want to output greyscale 8 bit, we would
 use limiting to 8 bits, and packaging to Luma component only.
 Add rlp to the reg offsets struct.
 This will allow different products to have a different reg offset for this
 particular module.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 4 ++--
 drivers/media/platform/atmel/atmel-isc-regs.h    | 2 ++
 drivers/media/platform/atmel/atmel-isc.h         | 2 ++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 +
 4 files changed, 7 insertions(+), 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -726,8 +726,8 @@ static int isc_configure(struct isc_devi
 	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 -	regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK,
 -			   rlp_mode);
 +	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 +			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
 	regmap_write(regmap, ISC_DCFG, dcfg);
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -204,6 +204,8 @@
 /* Subsampling 4:2:2 to 4:2:0 Control Register */
 #define ISC_SUB420_CTRL 0x000003cc
 +/* Offset for RLP register specific to sama5d2 product */
 +#define ISC_SAMA5D2_RLP_OFFSET	0
 /* Rounding, Limiting and Packing Configuration Register */
 #define ISC_RLP_CFG     0x000003d0
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -149,12 +149,14 @@ struct isc_ctrls {
  * @cbc:		Offset for the CBC register
  * @sub422:		Offset for the SUB422 register
  * @sub420:		Offset for the SUB420 register
 + * @rlp:		Offset for the RLP register
  */
 struct isc_reg_offsets {
 	u32 csc;
 	u32 cbc;
 	u32 sub422;
 	u32 sub420;
 +	u32 rlp;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -255,6 +255,7 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
 	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
 	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
 +	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch
+++ b/target/linux/at91/patches-5.10/169-media-atmel-atmel-isc-add-HIS-to-register-offsets.patch
@ -1,99 +0,0 @@
 From 8c19aa14b8303a0e7c4bae42f3f00f9a2a65b0db Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:11 +0200
 Subject: [PATCH 169/247] media: atmel: atmel-isc: add HIS to register offsets
 The HIS submodule is a part of the atmel-isc pipeline, and stands for
 Histogram. This module performs a color histogram that can be read and used
 by the main processor.
 Add his to the reg offsets struct.
 This will allow different products to have a different reg offset for this
 particular module.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 11 +++++++----
 drivers/media/platform/atmel/atmel-isc-regs.h    |  2 ++
 drivers/media/platform/atmel/atmel-isc.h         |  2 ++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c |  1 +
 4 files changed, 12 insertions(+), 4 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -686,12 +686,13 @@ static void isc_set_histogram(struct isc
 	struct isc_ctrls *ctrls = &isc->ctrls;
 	if (enable) {
 -		regmap_write(regmap, ISC_HIS_CFG,
 +		regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
 			     ISC_HIS_CFG_MODE_GR |
 			     (isc->config.sd_format->cfa_baycfg
 					<< ISC_HIS_CFG_BAYSEL_SHIFT) |
 					ISC_HIS_CFG_RAR);
 -		regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);
 +		regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 +			     ISC_HIS_CTRL_EN);
 		regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
 		ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
 		isc_update_profile(isc);
@@ -700,7 +701,8 @@ static void isc_set_histogram(struct isc
 		ctrls->hist_stat = HIST_ENABLED;
 	} else {
 		regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
 -		regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS);
 +		regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
 +			     ISC_HIS_CTRL_DIS);
 		ctrls->hist_stat = HIST_DISABLED;
 	}
@@ -1836,7 +1838,8 @@ static void isc_awb_work(struct work_str
 			ctrls->awb = ISC_WB_NONE;
 		}
 	}
 -	regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR);
 +	regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
 +		     hist_id | baysel | ISC_HIS_CFG_RAR);
 	isc_update_profile(isc);
 	/* if awb has been disabled, we don't need to start another histogram */
 	if (ctrls->awb)
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -224,6 +224,8 @@
 #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
 #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
 +/* Offset for HIS register specific to sama5d2 product */
 +#define ISC_SAMA5D2_HIS_OFFSET	0
 /* Histogram Control Register */
 #define ISC_HIS_CTRL	0x000003d4
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -150,6 +150,7 @@ struct isc_ctrls {
  * @sub422:		Offset for the SUB422 register
  * @sub420:		Offset for the SUB420 register
  * @rlp:		Offset for the RLP register
 + * @his:		Offset for the HIS related registers
  */
 struct isc_reg_offsets {
 	u32 csc;
@@ -157,6 +158,7 @@ struct isc_reg_offsets {
 	u32 sub422;
 	u32 sub420;
 	u32 rlp;
 +	u32 his;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -256,6 +256,7 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
 	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
 	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
 +	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch
+++ b/target/linux/at91/patches-5.10/170-media-atmel-atmel-isc-add-DMA-to-register-offsets.patch
@ -1,110 +0,0 @@
 From 7173e54070a9b530c8c16e0a507be71385133abd Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:12 +0200
 Subject: [PATCH 170/247] media: atmel: atmel-isc: add DMA to register offsets
 The DMA submodule is a part of the atmel-isc pipeline, and stands for
 Direct Memory Access. It acts like a master on the AXI bus of the SoC, and
 can directly write the RAM area with the pixel data from the ISC internal
 sram.
 Add dma to the reg offsets struct.
 This will allow different products to have a different reg offset for this
 particular module.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++-------
 drivers/media/platform/atmel/atmel-isc-regs.h |  3 +++
 drivers/media/platform/atmel/atmel-isc.h      |  2 ++
 .../media/platform/atmel/atmel-sama5d2-isc.c  |  1 +
 4 files changed, 18 insertions(+), 7 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -601,16 +601,20 @@ static void isc_start_dma(struct isc_dev
 			   ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
 	addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
 -	regmap_write(regmap, ISC_DAD0, addr0);
 +	regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
 	switch (isc->config.fourcc) {
 	case V4L2_PIX_FMT_YUV420:
 -		regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3);
 -		regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6);
 +		regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 +			     addr0 + (sizeimage * 2) / 3);
 +		regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 +			     addr0 + (sizeimage * 5) / 6);
 		break;
 	case V4L2_PIX_FMT_YUV422P:
 -		regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2);
 -		regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4);
 +		regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
 +			     addr0 + sizeimage / 2);
 +		regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
 +			     addr0 + (sizeimage * 3) / 4);
 		break;
 	default:
 		break;
@@ -618,7 +622,8 @@ static void isc_start_dma(struct isc_dev
 	dctrl_dview = isc->config.dctrl_dview;
 -	regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);
 +	regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
 +		     dctrl_dview | ISC_DCTRL_IE_IS);
 	spin_lock(&isc->awb_lock);
 	regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
 	spin_unlock(&isc->awb_lock);
@@ -731,7 +736,7 @@ static int isc_configure(struct isc_devi
 	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
 -	regmap_write(regmap, ISC_DCFG, dcfg);
 +	regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 	/* Set the pipeline */
 	isc_set_pipeline(isc, pipeline);
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -247,6 +247,9 @@
 #define ISC_HIS_CFG_RAR			BIT(8)
 +/* Offset for DMA register specific to sama5d2 product */
 +#define ISC_SAMA5D2_DMA_OFFSET	0
 +
 /* DMA Configuration Register */
 #define ISC_DCFG        0x000003e0
 #define ISC_DCFG_IMODE_PACKED8          0x0
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -151,6 +151,7 @@ struct isc_ctrls {
  * @sub420:		Offset for the SUB420 register
  * @rlp:		Offset for the RLP register
  * @his:		Offset for the HIS related registers
 + * @dma:		Offset for the DMA related registers
  */
 struct isc_reg_offsets {
 	u32 csc;
@@ -159,6 +160,7 @@ struct isc_reg_offsets {
 	u32 sub420;
 	u32 rlp;
 	u32 his;
 +	u32 dma;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -257,6 +257,7 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET;
 	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
 	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
 +	isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch
+++ b/target/linux/at91/patches-5.10/171-media-atmel-atmel-isc-add-support-for-version-regist.patch
@ -1,77 +0,0 @@
 From 0939b0a92acca11a5a3b0de5dd70434e17e40ed3 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:13 +0200
 Subject: [PATCH 171/247] media: atmel: atmel-isc: add support for version
 register
 Add support for version register and print it at probe time.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-regs.h    | 5 +++++
 drivers/media/platform/atmel/atmel-isc.h         | 2 ++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++
 3 files changed, 12 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -295,6 +295,11 @@
 /* DMA Address 2 Register */
 #define ISC_DAD2        0x000003fc
 +/* Offset for version register specific to sama5d2 product */
 +#define ISC_SAMA5D2_VERSION_OFFSET	0
 +/* Version Register */
 +#define ISC_VERSION	0x0000040c
 +
 /* Histogram Entry */
 #define ISC_HIS_ENTRY	0x00000410
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -152,6 +152,7 @@ struct isc_ctrls {
  * @rlp:		Offset for the RLP register
  * @his:		Offset for the HIS related registers
  * @dma:		Offset for the DMA related registers
 + * @version:		Offset for the version register
  */
 struct isc_reg_offsets {
 	u32 csc;
@@ -161,6 +162,7 @@ struct isc_reg_offsets {
 	u32 rlp;
 	u32 his;
 	u32 dma;
 +	u32 version;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -210,6 +210,7 @@ static int atmel_isc_probe(struct platfo
 	struct isc_subdev_entity *subdev_entity;
 	int irq;
 	int ret;
 +	u32 ver;
 	isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
 	if (!isc)
@@ -258,6 +259,7 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET;
 	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
 	isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;
 +	isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
@@ -346,6 +348,9 @@ static int atmel_isc_probe(struct platfo
 	pm_runtime_enable(dev);
 	pm_request_idle(dev);
 +	regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);
 +	dev_info(dev, "Microchip ISC version %x\n", ver);
 +
 	return 0;
 cleanup_subdev:
--- a/target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch
+++ b/target/linux/at91/patches-5.10/172-media-atmel-atmel-isc-add-his_entry-to-register-offs.patch
@ -1,71 +0,0 @@
 From bce46a8a620a796ca3cfe5bff61baf6744074986 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:14 +0200
 Subject: [PATCH 172/247] media: atmel: atmel-isc: add his_entry to register
 offsets
 Add his_entry to the reg offsets struct.
 This will allow different products to have a different reg offset for this
 particular module.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 3 ++-
 drivers/media/platform/atmel/atmel-isc-regs.h    | 2 ++
 drivers/media/platform/atmel/atmel-isc.h         | 2 ++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 +
 4 files changed, 7 insertions(+), 1 deletion(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -1684,7 +1684,8 @@ static void isc_hist_count(struct isc_de
 	*min = 0;
 	*max = HIST_ENTRIES;
 -	regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES);
 +	regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
 +			 hist_entry, HIST_ENTRIES);
 	*hist_count = 0;
 	/*
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -300,6 +300,8 @@
 /* Version Register */
 #define ISC_VERSION	0x0000040c
 +/* Offset for version register specific to sama5d2 product */
 +#define ISC_SAMA5D2_HIS_ENTRY_OFFSET	0
 /* Histogram Entry */
 #define ISC_HIS_ENTRY	0x00000410
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -153,6 +153,7 @@ struct isc_ctrls {
  * @his:		Offset for the HIS related registers
  * @dma:		Offset for the DMA related registers
  * @version:		Offset for the version register
 + * @his_entry:		Offset for the HIS entries registers
  */
 struct isc_reg_offsets {
 	u32 csc;
@@ -163,6 +164,7 @@ struct isc_reg_offsets {
 	u32 his;
 	u32 dma;
 	u32 version;
 +	u32 his_entry;
 };
 /*
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -260,6 +260,7 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET;
 	isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET;
 	isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
 +	isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch
+++ b/target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch
@ -1,99 +0,0 @@
 From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:15 +0200
 Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for
 additional modules
 Add register description for additional pipeline modules: the
 Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS)
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++
 1 file changed, 67 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -90,6 +90,46 @@
 #define ISC_INT_DDONE		BIT(8)
 #define ISC_INT_HISDONE		BIT(12)
 +/* ISC DPC Control Register */
 +#define ISC_DPC_CTRL	0x40
 +
 +#define ISC_DPC_CTRL_DPCEN	BIT(0)
 +#define ISC_DPC_CTRL_GDCEN	BIT(1)
 +#define ISC_DPC_CTRL_BLCEN	BIT(2)
 +
 +/* ISC DPC Config Register */
 +#define ISC_DPC_CFG	0x44
 +
 +#define ISC_DPC_CFG_BAYSEL_SHIFT	0
 +
 +#define ISC_DPC_CFG_EITPOL		BIT(4)
 +
 +#define ISC_DPC_CFG_TA_ENABLE		BIT(14)
 +#define ISC_DPC_CFG_TC_ENABLE		BIT(13)
 +#define ISC_DPC_CFG_TM_ENABLE		BIT(12)
 +
 +#define ISC_DPC_CFG_RE_MODE		BIT(17)
 +
 +#define ISC_DPC_CFG_GDCCLP_SHIFT	20
 +#define ISC_DPC_CFG_GDCCLP_MASK		GENMASK(22, 20)
 +
 +#define ISC_DPC_CFG_BLOFF_SHIFT		24
 +#define ISC_DPC_CFG_BLOFF_MASK		GENMASK(31, 24)
 +
 +#define ISC_DPC_CFG_BAYCFG_SHIFT	0
 +#define ISC_DPC_CFG_BAYCFG_MASK		GENMASK(1, 0)
 +/* ISC DPC Threshold Median Register */
 +#define ISC_DPC_THRESHM	0x48
 +
 +/* ISC DPC Threshold Closest Register */
 +#define ISC_DPC_THRESHC	0x4C
 +
 +/* ISC DPC Threshold Average Register */
 +#define ISC_DPC_THRESHA	0x50
 +
 +/* ISC DPC STatus Register */
 +#define ISC_DPC_SR	0x54
 +
 /* ISC White Balance Control Register */
 #define ISC_WB_CTRL     0x00000058
@@ -153,6 +193,33 @@
 /* ISC_Gamma Correction Green Entry Register */
 #define ISC_GAM_RENTRY	0x00000298
 +/* ISC VHXS Control Register */
 +#define ISC_VHXS_CTRL	0x398
 +
 +/* ISC VHXS Source Size Register */
 +#define ISC_VHXS_SS	0x39C
 +
 +/* ISC VHXS Destination Size Register */
 +#define ISC_VHXS_DS	0x3A0
 +
 +/* ISC Vertical Factor Register */
 +#define ISC_VXS_FACT	0x3a4
 +
 +/* ISC Horizontal Factor Register */
 +#define ISC_HXS_FACT	0x3a8
 +
 +/* ISC Vertical Config Register */
 +#define ISC_VXS_CFG	0x3ac
 +
 +/* ISC Horizontal Config Register */
 +#define ISC_HXS_CFG	0x3b0
 +
 +/* ISC Vertical Tap Register */
 +#define ISC_VXS_TAP	0x3b4
 +
 +/* ISC Horizontal Tap Register */
 +#define ISC_HXS_TAP	0x434
 +
 /* Offset for CSC register specific to sama5d2 product */
 #define ISC_SAMA5D2_CSC_OFFSET	0
--- a/target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch
+++ b/target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch
@ -1,104 +0,0 @@
 From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:16 +0200
 Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra
 modules
 Newer ISC pipelines have the additional modules of
 Defective Pixel Correction -> DPC itself,
 Defective Pixel Correction -> Green Disparity Correction (DPC_GDC)
 Defective Pixel Correction -> Black Level Correction (DPC_BLC)
 Vertical and Horizontal Scaler -> VHXS
 Some products have this full pipeline (sama7g5), other products do not (sama5d2)
 Add the modules to the isc base, and also extend the register range to include
 the modules.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++--
 drivers/media/platform/atmel/atmel-isc.h      | 28 +++++++++++--------
 2 files changed, 25 insertions(+), 14 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device
 	struct regmap_field *regs;
 	unsigned int i;
 -	/* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
 +	/*
 +	 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
 +	 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
 +	 */
 	const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
 +		REG_FIELD(ISC_DPC_CTRL, 0, 0),
 +		REG_FIELD(ISC_DPC_CTRL, 1, 1),
 +		REG_FIELD(ISC_DPC_CTRL, 2, 2),
 		REG_FIELD(ISC_WB_CTRL, 0, 0),
 		REG_FIELD(ISC_CFA_CTRL, 0, 0),
 		REG_FIELD(ISC_CC_CTRL, 0, 0),
@@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device
 		REG_FIELD(ISC_GAM_CTRL, 1, 1),
 		REG_FIELD(ISC_GAM_CTRL, 2, 2),
 		REG_FIELD(ISC_GAM_CTRL, 3, 3),
 +		REG_FIELD(ISC_VHXS_CTRL, 0, 0),
 		REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
 		REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
 		REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
@@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device
 }
 /* regmap configuration */
 -#define ATMEL_ISC_REG_MAX    0xbfc
 +#define ATMEL_ISC_REG_MAX    0xd5c
 const struct regmap_config isc_regmap_config = {
 	.reg_bits       = 32,
 	.reg_stride     = 4,
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -67,17 +67,21 @@ struct isc_format {
 };
 /* Pipeline bitmap */
 -#define WB_ENABLE	BIT(0)
 -#define CFA_ENABLE	BIT(1)
 -#define CC_ENABLE	BIT(2)
 -#define GAM_ENABLE	BIT(3)
 -#define GAM_BENABLE	BIT(4)
 -#define GAM_GENABLE	BIT(5)
 -#define GAM_RENABLE	BIT(6)
 -#define CSC_ENABLE	BIT(7)
 -#define CBC_ENABLE	BIT(8)
 -#define SUB422_ENABLE	BIT(9)
 -#define SUB420_ENABLE	BIT(10)
 +#define DPC_DPCENABLE	BIT(0)
 +#define DPC_GDCENABLE	BIT(1)
 +#define DPC_BLCENABLE	BIT(2)
 +#define WB_ENABLE	BIT(3)
 +#define CFA_ENABLE	BIT(4)
 +#define CC_ENABLE	BIT(5)
 +#define GAM_ENABLE	BIT(6)
 +#define GAM_BENABLE	BIT(7)
 +#define GAM_GENABLE	BIT(8)
 +#define GAM_RENABLE	BIT(9)
 +#define VHXS_ENABLE	BIT(10)
 +#define CSC_ENABLE	BIT(11)
 +#define CBC_ENABLE	BIT(12)
 +#define SUB422_ENABLE	BIT(13)
 +#define SUB420_ENABLE	BIT(14)
 #define GAM_ENABLES	(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
@@ -141,7 +145,7 @@ struct isc_ctrls {
 	u32 hist_minmax[HIST_BAYER][2];
 };
 -#define ISC_PIPE_LINE_NODE_NUM	11
 +#define ISC_PIPE_LINE_NODE_NUM	15
 /*
  * struct isc_reg_offsets - ISC device register offsets
--- a/target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch
+++ b/target/linux/at91/patches-5.10/175-media-atmel-atmel-isc-add-CC-initialization-function.patch
@ -1,83 +0,0 @@
 From 0db91d2a803221c313c9f2cd1d71050d7c5a7b5b Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:17 +0200
 Subject: [PATCH 175/247] media: atmel: atmel-isc: add CC initialization
 function
 The CC submodule is a part of the atmel-isc pipeline, and stands for
 Color Correction. It is used to apply gains and offsets to the
 chroma (U, V) components of the YUV elements.
 Implement the CC submodule initialization, as a product
 specific function, which currently configures the neutral point in color
 correction.
 [hverkuil: made isc_sama5d2_config_cc static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    |  1 +
 drivers/media/platform/atmel/atmel-isc.h         |  3 +++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++
 3 files changed, 18 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -661,6 +661,7 @@ static void isc_set_pipeline(struct isc_
 	isc->config_csc(isc);
 	isc->config_cbc(isc);
 +	isc->config_cc(isc);
 }
 static int isc_update_profile(struct isc_device *isc)
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -224,6 +224,8 @@ struct isc_reg_offsets {
  *			specific CSC module
  * @config_cbc:		pointer to a function that initializes product
  *			specific CBC module
 + * @config_cc:		pointer to a function that initializes product
 + *			specific CC module
  *
  * @offsets:		struct holding the product specific register offsets
  */
@@ -297,6 +299,7 @@ struct isc_device {
 	struct {
 		void (*config_csc)(struct isc_device *isc);
 		void (*config_cbc)(struct isc_device *isc);
 +		void (*config_cc)(struct isc_device *isc);
 	};
 	struct isc_reg_offsets		offsets;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -83,6 +83,19 @@ static void isc_sama5d2_config_cbc(struc
 		     isc->ctrls.contrast);
 }
 +static void isc_sama5d2_config_cc(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	/* Configure each register at the neutral fixed point 1.0 or 0.0 */
 +	regmap_write(regmap, ISC_CC_RR_RG, (1 << 8));
 +	regmap_write(regmap, ISC_CC_RB_OR, 0);
 +	regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);
 +	regmap_write(regmap, ISC_CC_GB_OG, 0);
 +	regmap_write(regmap, ISC_CC_BR_BG, 0);
 +	regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -251,6 +264,7 @@ static int atmel_isc_probe(struct platfo
 	isc->config_csc = isc_sama5d2_config_csc;
 	isc->config_cbc = isc_sama5d2_config_cbc;
 +	isc->config_cc = isc_sama5d2_config_cc;
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
--- a/target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch
+++ b/target/linux/at91/patches-5.10/176-media-atmel-atmel-isc-create-product-specific-v4l2-c.patch
@ -1,86 +0,0 @@
 From 0a75c502eac4f2ef71b6c3e0b3a01db1b3c37ba9 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:18 +0200
 Subject: [PATCH 176/247] media: atmel: atmel-isc: create product specific v4l2
 controls config
 Create product specific callback for initializing v4l2 controls.
 Call this from v4l2 controls init function.
 [hverkuil: made isc_sama5d2_config_ctrls static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    |  5 +++--
 drivers/media/platform/atmel/atmel-isc.h         |  5 +++++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++
 3 files changed, 20 insertions(+), 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -2051,11 +2051,12 @@ static int isc_ctrl_init(struct isc_devi
 	if (ret < 0)
 		return ret;
 +	/* Initialize product specific controls. For example, contrast */
 +	isc->config_ctrls(isc, ops);
 +
 	ctrls->brightness = 0;
 -	ctrls->contrast = 256;
 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
 -	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
 			  isc->gamma_max);
 	isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -226,6 +226,8 @@ struct isc_reg_offsets {
  *			specific CBC module
  * @config_cc:		pointer to a function that initializes product
  *			specific CC module
 + * @config_ctrls:	pointer to a functoin that initializes product
 + *			specific v4l2 controls.
  *
  * @offsets:		struct holding the product specific register offsets
  */
@@ -300,6 +302,9 @@ struct isc_device {
 		void (*config_csc)(struct isc_device *isc);
 		void (*config_cbc)(struct isc_device *isc);
 		void (*config_cc)(struct isc_device *isc);
 +
 +		void (*config_ctrls)(struct isc_device *isc,
 +				     const struct v4l2_ctrl_ops *ops);
 	};
 	struct isc_reg_offsets		offsets;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -96,6 +96,17 @@ static void isc_sama5d2_config_cc(struct
 	regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
 }
 +static void isc_sama5d2_config_ctrls(struct isc_device *isc,
 +				     const struct v4l2_ctrl_ops *ops)
 +{
 +	struct isc_ctrls *ctrls = &isc->ctrls;
 +	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
 +
 +	ctrls->contrast = 256;
 +
 +	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -265,6 +276,7 @@ static int atmel_isc_probe(struct platfo
 	isc->config_csc = isc_sama5d2_config_csc;
 	isc->config_cbc = isc_sama5d2_config_cbc;
 	isc->config_cc = isc_sama5d2_config_cc;
 +	isc->config_ctrls = isc_sama5d2_config_ctrls;
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
--- a/target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch
+++ b/target/linux/at91/patches-5.10/177-media-atmel-atmel-isc-create-callback-for-DPC-submod.patch
@ -1,75 +0,0 @@
 From d53eb90044c19ba22b51978fcb007d9b5200b83a Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:19 +0200
 Subject: [PATCH 177/247] media: atmel: atmel-isc: create callback for DPC
 submodule product specific
 The DPC submodule is a part of the atmel-isc pipeline, and stands for
 Defective Pixel Correction. Its purpose is to detect defective pixels and
 correct them if possible with the help of adjacent pixels.
 Create a product specific callback for initializing the DPC submodule
 of the pipeline.
 For sama5d2 product, this module does not exist, thus this function is a noop.
 [hverkuil: made isc_sama5d2_config_dpc static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 1 +
 drivers/media/platform/atmel/atmel-isc.h         | 3 +++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++
 3 files changed, 10 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -659,6 +659,7 @@ static void isc_set_pipeline(struct isc_
 	regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
 	regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
 +	isc->config_dpc(isc);
 	isc->config_csc(isc);
 	isc->config_cbc(isc);
 	isc->config_cc(isc);
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -220,6 +220,8 @@ struct isc_reg_offsets {
  * @max_width:		maximum frame width, dependent on the internal RAM
  * @max_height:		maximum frame height, dependent on the internal RAM
  *
 + * @config_dpc:		pointer to a function that initializes product
 + *			specific DPC module
  * @config_csc:		pointer to a function that initializes product
  *			specific CSC module
  * @config_cbc:		pointer to a function that initializes product
@@ -299,6 +301,7 @@ struct isc_device {
 	u32		max_height;
 	struct {
 +		void (*config_dpc)(struct isc_device *isc);
 		void (*config_csc)(struct isc_device *isc);
 		void (*config_cbc)(struct isc_device *isc);
 		void (*config_cc)(struct isc_device *isc);
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -107,6 +107,11 @@ static void isc_sama5d2_config_ctrls(str
 	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256);
 }
 +static void isc_sama5d2_config_dpc(struct isc_device *isc)
 +{
 +	/* This module is not present on sama5d2 pipeline */
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -273,6 +278,7 @@ static int atmel_isc_probe(struct platfo
 	isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH;
 	isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT;
 +	isc->config_dpc = isc_sama5d2_config_dpc;
 	isc->config_csc = isc_sama5d2_config_csc;
 	isc->config_cbc = isc_sama5d2_config_cbc;
 	isc->config_cc = isc_sama5d2_config_cc;
--- a/target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch
+++ b/target/linux/at91/patches-5.10/178-media-atmel-atmel-isc-create-callback-for-GAM-submod.patch
@ -1,75 +0,0 @@
 From 96936a6753a13dea5a8f66de949e6594dd82ce22 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:20 +0200
 Subject: [PATCH 178/247] media: atmel: atmel-isc: create callback for GAM
 submodule product specific
 The GAM submodule is a part of the atmel-isc pipeline, and stands for
 Gamma Correction. It is used to apply the gamma curve to the incoming pixels.
 Create a product specific callback for initializing the GAM submodule
 of the pipeline.
 For sama5d2 product, there is no special configuration at this moment,
 thus this function is a noop.
 [hverkuil: made isc_sama5d2_config_gam static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    | 1 +
 drivers/media/platform/atmel/atmel-isc.h         | 3 +++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++
 3 files changed, 10 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -663,6 +663,7 @@ static void isc_set_pipeline(struct isc_
 	isc->config_csc(isc);
 	isc->config_cbc(isc);
 	isc->config_cc(isc);
 +	isc->config_gam(isc);
 }
 static int isc_update_profile(struct isc_device *isc)
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -228,6 +228,8 @@ struct isc_reg_offsets {
  *			specific CBC module
  * @config_cc:		pointer to a function that initializes product
  *			specific CC module
 + * @config_gam:		pointer to a function that initializes product
 + *			specific GAMMA module
  * @config_ctrls:	pointer to a functoin that initializes product
  *			specific v4l2 controls.
  *
@@ -305,6 +307,7 @@ struct isc_device {
 		void (*config_csc)(struct isc_device *isc);
 		void (*config_cbc)(struct isc_device *isc);
 		void (*config_cc)(struct isc_device *isc);
 +		void (*config_gam)(struct isc_device *isc);
 		void (*config_ctrls)(struct isc_device *isc,
 				     const struct v4l2_ctrl_ops *ops);
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -112,6 +112,11 @@ static void isc_sama5d2_config_dpc(struc
 	/* This module is not present on sama5d2 pipeline */
 }
 +static void isc_sama5d2_config_gam(struct isc_device *isc)
 +{
 +	/* No specific gamma configuration */
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -282,6 +287,7 @@ static int atmel_isc_probe(struct platfo
 	isc->config_csc = isc_sama5d2_config_csc;
 	isc->config_cbc = isc_sama5d2_config_cbc;
 	isc->config_cc = isc_sama5d2_config_cc;
 +	isc->config_gam = isc_sama5d2_config_gam;
 	isc->config_ctrls = isc_sama5d2_config_ctrls;
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
--- a/target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch
+++ b/target/linux/at91/patches-5.10/179-media-atmel-atmel-isc-create-callback-for-RLP-submod.patch
@ -1,95 +0,0 @@
 From ece1d7059731e31875e6eb464da4fb4a16465305 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:21 +0200
 Subject: [PATCH 179/247] media: atmel: atmel-isc: create callback for RLP
 submodule product specific
 The RLP submodule is a part of the atmel-isc pipeline, and stands for
 Rounding,Limiting and Packaging. It used to extract specific data from the
 ISC pipeline. For example if we want to output greyscale 8 bit, we would
 use limiting to 8 bits, and packaging to Luma component only.
 Create a product specific callback for initializing the RLP submodule
 of the pipeline
 [hverkuil: made isc_sama5d2_config_rlp static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    |  6 ++----
 drivers/media/platform/atmel/atmel-isc.h         |  3 +++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++
 3 files changed, 15 insertions(+), 4 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -719,11 +719,10 @@ static void isc_set_histogram(struct isc
 static int isc_configure(struct isc_device *isc)
 {
 	struct regmap *regmap = isc->regmap;
 -	u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;
 +	u32 pfe_cfg0, dcfg, mask, pipeline;
 	struct isc_subdev_entity *subdev = isc->current_subdev;
 	pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
 -	rlp_mode = isc->config.rlp_cfg_mode;
 	pipeline = isc->config.bits_pipeline;
 	dcfg = isc->config.dcfg_imode | isc->dcfg;
@@ -736,8 +735,7 @@ static int isc_configure(struct isc_devi
 	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 -	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 -			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
 +	isc->config_rlp(isc);
 	regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -230,6 +230,8 @@ struct isc_reg_offsets {
  *			specific CC module
  * @config_gam:		pointer to a function that initializes product
  *			specific GAMMA module
 + * @config_rlp:		pointer to a function that initializes product
 + *			specific RLP module
  * @config_ctrls:	pointer to a functoin that initializes product
  *			specific v4l2 controls.
  *
@@ -308,6 +310,7 @@ struct isc_device {
 		void (*config_cbc)(struct isc_device *isc);
 		void (*config_cc)(struct isc_device *isc);
 		void (*config_gam)(struct isc_device *isc);
 +		void (*config_rlp)(struct isc_device *isc);
 		void (*config_ctrls)(struct isc_device *isc,
 				     const struct v4l2_ctrl_ops *ops);
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -117,6 +117,15 @@ static void isc_sama5d2_config_gam(struc
 	/* No specific gamma configuration */
 }
 +static void isc_sama5d2_config_rlp(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +	u32 rlp_mode = isc->config.rlp_cfg_mode;
 +
 +	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 +			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -288,6 +297,7 @@ static int atmel_isc_probe(struct platfo
 	isc->config_cbc = isc_sama5d2_config_cbc;
 	isc->config_cc = isc_sama5d2_config_cc;
 	isc->config_gam = isc_sama5d2_config_gam;
 +	isc->config_rlp = isc_sama5d2_config_rlp;
 	isc->config_ctrls = isc_sama5d2_config_ctrls;
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
--- a/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch
+++ b/target/linux/at91/patches-5.10/180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch
@ -1,440 +0,0 @@
 From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:22 +0200
 Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into
 product specific code
 The list of input and output formats has to be product specific.
 Move this list into the product specific code.
 Have pointers to these arrays inside the device struct.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 167 ++----------------
 drivers/media/platform/atmel/atmel-isc.h      |  12 +-
 .../media/platform/atmel/atmel-sama5d2-isc.c  | 136 ++++++++++++++
 3 files changed, 165 insertions(+), 150 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 064
 MODULE_PARM_DESC(sensor_preferred,
 		 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
 -/* This is a list of the formats that the ISC can *output* */
 -const struct isc_format controller_formats[] = {
 -	{
 -		.fourcc		= V4L2_PIX_FMT_ARGB444,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_ARGB555,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_RGB565,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_ABGR32,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_XBGR32,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_YUV420,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_YUYV,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_YUV422P,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_GREY,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_Y10,
 -	},
 -};
 -
 -/* This is a list of formats that the ISC can receive as *input* */
 -struct isc_format formats_list[] = {
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SBGGR8,
 -		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SGBRG8,
 -		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SGRBG8,
 -		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SRGGB8,
 -		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SBGGR10,
 -		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 -		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SGBRG10,
 -		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 -		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SGRBG10,
 -		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 -		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SRGGB10,
 -		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 -		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SBGGR12,
 -		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 -		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SGBRG12,
 -		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 -		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SGRBG12,
 -		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 -		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_SRGGB12,
 -		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 -		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_GREY,
 -		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_YUYV,
 -		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_RGB565,
 -		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
 -		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 -	},
 -	{
 -		.fourcc		= V4L2_PIX_FMT_Y10,
 -		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
 -		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 -	},
 -
 -};
 -
 #define ISC_IS_FORMAT_RAW(mbus_code) \
 	(((mbus_code) & 0xf000) == 0x3000)
@@ -919,24 +788,25 @@ static int isc_querycap(struct file *fil
 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
 				 struct v4l2_fmtdesc *f)
 {
 +	struct isc_device *isc = video_drvdata(file);
 	u32 index = f->index;
 	u32 i, supported_index;
 -	if (index < ARRAY_SIZE(controller_formats)) {
 -		f->pixelformat = controller_formats[index].fourcc;
 +	if (index < isc->controller_formats_size) {
 +		f->pixelformat = isc->controller_formats[index].fourcc;
 		return 0;
 	}
 -	index -= ARRAY_SIZE(controller_formats);
 +	index -= isc->controller_formats_size;
 	supported_index = 0;
 -	for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
 -		if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
 -		    !formats_list[i].sd_support)
 +	for (i = 0; i < isc->formats_list_size; i++) {
 +		if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
 +		    !isc->formats_list[i].sd_support)
 			continue;
 		if (supported_index == index) {
 -			f->pixelformat = formats_list[i].fourcc;
 +			f->pixelformat = isc->formats_list[i].fourcc;
 			return 0;
 		}
 		supported_index++;
@@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct fi
 		if (isc->user_formats[i]->fourcc == fsize->pixel_format)
 			ret = 0;
 -	for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
 -		if (controller_formats[i].fourcc == fsize->pixel_format)
 +	for (i = 0; i < isc->controller_formats_size; i++)
 +		if (isc->controller_formats[i].fourcc == fsize->pixel_format)
 			ret = 0;
 	if (ret)
@@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struc
 		if (isc->user_formats[i]->fourcc == fival->pixel_format)
 			ret = 0;
 -	for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
 -		if (controller_formats[i].fourcc == fival->pixel_format)
 +	for (i = 0; i < isc->controller_formats_size; i++)
 +		if (isc->controller_formats[i].fourcc == fival->pixel_format)
 			ret = 0;
 	if (ret)
@@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2
 	v4l2_ctrl_handler_free(&isc->ctrls.handler);
 }
 -static struct isc_format *find_format_by_code(unsigned int code, int *index)
 +static struct isc_format *find_format_by_code(struct isc_device *isc,
 +					      unsigned int code, int *index)
 {
 -	struct isc_format *fmt = &formats_list[0];
 +	struct isc_format *fmt = &isc->formats_list[0];
 	unsigned int i;
 -	for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
 +	for (i = 0; i < isc->formats_list_size; i++) {
 		if (fmt->mbus_code == code) {
 			*index = i;
 			return fmt;
@@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_d
 	struct isc_format *fmt;
 	struct v4l2_subdev *subdev = isc->current_subdev->sd;
 	unsigned int num_fmts, i, j;
 -	u32 list_size = ARRAY_SIZE(formats_list);
 +	u32 list_size = isc->formats_list_size;
 	struct v4l2_subdev_mbus_code_enum mbus_code = {
 		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
 	};
@@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_d
 	       NULL, &mbus_code)) {
 		mbus_code.index++;
 -		fmt = find_format_by_code(mbus_code.code, &i);
 +		fmt = find_format_by_code(isc, mbus_code.code, &i);
 		if (!fmt) {
 			v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
 				  mbus_code.code);
@@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_d
 	if (!isc->user_formats)
 		return -ENOMEM;
 -	fmt = &formats_list[0];
 +	fmt = &isc->formats_list[0];
 	for (i = 0, j = 0; i < list_size; i++) {
 		if (fmt->sd_support)
 			isc->user_formats[j++] = fmt;
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -236,6 +236,12 @@ struct isc_reg_offsets {
  *			specific v4l2 controls.
  *
  * @offsets:		struct holding the product specific register offsets
 + * @controller_formats:	pointer to the array of possible formats that the
 + *			controller can output
 + * @formats_list:	pointer to the array of possible formats that can
 + *			be used as an input to the controller
 + * @controller_formats_size:	size of controller_formats array
 + * @formats_list_size:	size of formats_list array
  */
 struct isc_device {
 	struct regmap		*regmap;
@@ -317,10 +323,12 @@ struct isc_device {
 	};
 	struct isc_reg_offsets		offsets;
 +	const struct isc_format		*controller_formats;
 +	struct isc_format		*formats_list;
 +	u32				controller_formats_size;
 +	u32				formats_list_size;
 };
 -extern struct isc_format formats_list[];
 -extern const struct isc_format controller_formats[];
 extern const struct regmap_config isc_regmap_config;
 extern const struct v4l2_async_notifier_operations isc_async_ops;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -54,6 +54,137 @@
 #define ISC_CLK_MAX_DIV		255
 +/* This is a list of the formats that the ISC can *output* */
 +static const struct isc_format sama5d2_controller_formats[] = {
 +	{
 +		.fourcc		= V4L2_PIX_FMT_ARGB444,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_ARGB555,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_RGB565,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_ABGR32,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_XBGR32,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUV420,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUYV,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUV422P,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_GREY,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_Y10,
 +	},
 +};
 +
 +/* This is a list of formats that the ISC can receive as *input* */
 +static struct isc_format sama5d2_formats_list[] = {
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SBGGR8,
 +		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGBRG8,
 +		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGRBG8,
 +		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SRGGB8,
 +		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SBGGR10,
 +		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGBRG10,
 +		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGRBG10,
 +		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SRGGB10,
 +		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SBGGR12,
 +		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGBRG12,
 +		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGRBG12,
 +		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SRGGB12,
 +		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_GREY,
 +		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUYV,
 +		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_RGB565,
 +		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_Y10,
 +		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +	},
 +
 +};
 +
 static void isc_sama5d2_config_csc(struct isc_device *isc)
 {
 	struct regmap *regmap = isc->regmap;
@@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platfo
 	isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
 	isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;
 +	isc->controller_formats = sama5d2_controller_formats;
 +	isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats);
 +	isc->formats_list = sama5d2_formats_list;
 +	isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list);
 +
 	/* sama5d2-isc - 8 bits per beat */
 	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
--- a/target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch
+++ b/target/linux/at91/patches-5.10/181-media-atmel-atmel-isc-create-an-adapt-pipeline-callb.patch
@ -1,89 +0,0 @@
 From 8601f1fc0a9a22788bfa6369fbbf83b3828a5b42 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:23 +0200
 Subject: [PATCH 181/247] media: atmel: atmel-isc: create an adapt pipeline
 callback for product specific
 Once the pipeline is set in the base code, create a callback that will adapt
 the ISC pipeline to each product.
 Create the adapt_pipeline callback that will be used in this fashion.
 [hverkuil: made isc_sama5d2_adapt_pipeline static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c    |  4 ++++
 drivers/media/platform/atmel/atmel-isc.h         |  5 +++++
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++
 3 files changed, 20 insertions(+)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -1059,6 +1059,10 @@ static int isc_try_configure_pipeline(st
 	default:
 		isc->try_config.bits_pipeline = 0x0;
 	}
 +
 +	/* Tune the pipeline to product specific */
 +	isc->adapt_pipeline(isc);
 +
 	return 0;
 }
 --- a/drivers/media/platform/atmel/atmel-isc.h
 +++ b/drivers/media/platform/atmel/atmel-isc.h
@@ -235,6 +235,9 @@ struct isc_reg_offsets {
  * @config_ctrls:	pointer to a functoin that initializes product
  *			specific v4l2 controls.
  *
 + * @adapt_pipeline:	pointer to a function that adapts the pipeline bits
 + *			to the product specific pipeline
 + *
  * @offsets:		struct holding the product specific register offsets
  * @controller_formats:	pointer to the array of possible formats that the
  *			controller can output
@@ -320,6 +323,8 @@ struct isc_device {
 		void (*config_ctrls)(struct isc_device *isc,
 				     const struct v4l2_ctrl_ops *ops);
 +
 +		void (*adapt_pipeline)(struct isc_device *isc);
 	};
 	struct isc_reg_offsets		offsets;
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -54,6 +54,10 @@
 #define ISC_CLK_MAX_DIV		255
 +#define ISC_SAMA5D2_PIPELINE \
 +	(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
 +	CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
 +
 /* This is a list of the formats that the ISC can *output* */
 static const struct isc_format sama5d2_controller_formats[] = {
 	{
@@ -257,6 +261,11 @@ static void isc_sama5d2_config_rlp(struc
 			   ISC_RLP_CFG_MODE_MASK, rlp_mode);
 }
 +static void isc_sama5d2_adapt_pipeline(struct isc_device *isc)
 +{
 +	isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE;
 +}
 +
 /* Gamma table with gamma 1/2.2 */
 static const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = {
 	/* 0 --> gamma 1/1.8 */
@@ -431,6 +440,8 @@ static int atmel_isc_probe(struct platfo
 	isc->config_rlp = isc_sama5d2_config_rlp;
 	isc->config_ctrls = isc_sama5d2_config_ctrls;
 +	isc->adapt_pipeline = isc_sama5d2_adapt_pipeline;
 +
 	isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET;
 	isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET;
 	isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET;
--- a/target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch
+++ b/target/linux/at91/patches-5.10/182-media-atmel-atmel-isc-regs-add-additional-fields-for.patch
@ -1,55 +0,0 @@
 From bf032d1a0105939b90072914d88181fbe6187f43 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:24 +0200
 Subject: [PATCH 182/247] media: atmel: atmel-isc-regs: add additional fields
 for sama7g5 type pipeline
 Add additional fields for registers present in sama7g5 type pipeline.
 Extend register masks for additional bits in sama7g5 type pipeline registers.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -289,8 +289,18 @@
 #define ISC_RLP_CFG_MODE_ARGB32         0xa
 #define ISC_RLP_CFG_MODE_YYCC           0xb
 #define ISC_RLP_CFG_MODE_YYCC_LIMITED   0xc
 +#define ISC_RLP_CFG_MODE_YCYC           0xd
 #define ISC_RLP_CFG_MODE_MASK           GENMASK(3, 0)
 +#define ISC_RLP_CFG_LSH			BIT(5)
 +
 +#define ISC_RLP_CFG_YMODE_YUYV		(3 << 6)
 +#define ISC_RLP_CFG_YMODE_YVYU		(2 << 6)
 +#define ISC_RLP_CFG_YMODE_VYUY		(0 << 6)
 +#define ISC_RLP_CFG_YMODE_UYVY		(1 << 6)
 +
 +#define ISC_RLP_CFG_YMODE_MASK		GENMASK(7, 6)
 +
 /* Offset for HIS register specific to sama5d2 product */
 #define ISC_SAMA5D2_HIS_OFFSET	0
 /* Histogram Control Register */
@@ -332,13 +342,15 @@
 #define ISC_DCFG_YMBSIZE_BEATS4         (0x1 << 4)
 #define ISC_DCFG_YMBSIZE_BEATS8         (0x2 << 4)
 #define ISC_DCFG_YMBSIZE_BEATS16        (0x3 << 4)
 -#define ISC_DCFG_YMBSIZE_MASK           GENMASK(5, 4)
 +#define ISC_DCFG_YMBSIZE_BEATS32        (0x4 << 4)
 +#define ISC_DCFG_YMBSIZE_MASK           GENMASK(6, 4)
 #define ISC_DCFG_CMBSIZE_SINGLE         (0x0 << 8)
 #define ISC_DCFG_CMBSIZE_BEATS4         (0x1 << 8)
 #define ISC_DCFG_CMBSIZE_BEATS8         (0x2 << 8)
 #define ISC_DCFG_CMBSIZE_BEATS16        (0x3 << 8)
 -#define ISC_DCFG_CMBSIZE_MASK           GENMASK(9, 8)
 +#define ISC_DCFG_CMBSIZE_BEATS32        (0x4 << 8)
 +#define ISC_DCFG_CMBSIZE_MASK           GENMASK(10, 8)
 /* DMA Control Register */
 #define ISC_DCTRL       0x000003e4
--- a/target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch
+++ b/target/linux/at91/patches-5.10/183-media-atmel-atmel-isc-base-add-support-for-more-form.patch
@ -1,145 +0,0 @@
 From fa9e6cd8f3ba4a277c06e4c1fb01cd69b3a57234 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:25 +0200
 Subject: [PATCH 183/247] media: atmel: atmel-isc-base: add support for more
 formats and additional pipeline modules
 Add support for additional formats supported by newer pipelines, and for
 additional pipeline modules.
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++----
 1 file changed, 38 insertions(+), 10 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -855,6 +855,8 @@ static int isc_try_validate_formats(stru
 	case V4L2_PIX_FMT_YUV420:
 	case V4L2_PIX_FMT_YUV422P:
 	case V4L2_PIX_FMT_YUYV:
 +	case V4L2_PIX_FMT_UYVY:
 +	case V4L2_PIX_FMT_VYUY:
 		ret = 0;
 		yuv = true;
 		break;
@@ -869,6 +871,7 @@ static int isc_try_validate_formats(stru
 		break;
 	case V4L2_PIX_FMT_GREY:
 	case V4L2_PIX_FMT_Y10:
 +	case V4L2_PIX_FMT_Y16:
 		ret = 0;
 		grey = true;
 		break;
@@ -899,6 +902,8 @@ static int isc_try_validate_formats(stru
  */
 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
 {
 +	isc->try_config.rlp_cfg_mode = 0;
 +
 	switch (isc->try_config.fourcc) {
 	case V4L2_PIX_FMT_SBGGR8:
 	case V4L2_PIX_FMT_SGBRG8:
@@ -965,7 +970,19 @@ static int isc_try_configure_rlp_dma(str
 		isc->try_config.bpp = 16;
 		break;
 	case V4L2_PIX_FMT_YUYV:
 -		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
 +		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
 +		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 +		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 +		isc->try_config.bpp = 16;
 +		break;
 +	case V4L2_PIX_FMT_UYVY:
 +		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
 +		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 +		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 +		isc->try_config.bpp = 16;
 +		break;
 +	case V4L2_PIX_FMT_VYUY:
 +		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
 		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
 		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 		isc->try_config.bpp = 16;
@@ -976,8 +993,11 @@ static int isc_try_configure_rlp_dma(str
 		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 		isc->try_config.bpp = 8;
 		break;
 +	case V4L2_PIX_FMT_Y16:
 +		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
 +		fallthrough;
 	case V4L2_PIX_FMT_Y10:
 -		isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10;
 +		isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
 		isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
 		isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
 		isc->try_config.bpp = 16;
@@ -1011,7 +1031,8 @@ static int isc_try_configure_pipeline(st
 		/* if sensor format is RAW, we convert inside ISC */
 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 			isc->try_config.bits_pipeline = CFA_ENABLE |
 -				WB_ENABLE | GAM_ENABLES;
 +				WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
 +				CC_ENABLE;
 		} else {
 			isc->try_config.bits_pipeline = 0x0;
 		}
@@ -1020,8 +1041,9 @@ static int isc_try_configure_pipeline(st
 		/* if sensor format is RAW, we convert inside ISC */
 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 			isc->try_config.bits_pipeline = CFA_ENABLE |
 -				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 -				SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE;
 +				CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
 +				SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
 +				DPC_BLCENABLE;
 		} else {
 			isc->try_config.bits_pipeline = 0x0;
 		}
@@ -1031,33 +1053,39 @@ static int isc_try_configure_pipeline(st
 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 			isc->try_config.bits_pipeline = CFA_ENABLE |
 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 -				SUB422_ENABLE | CBC_ENABLE;
 +				SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 		} else {
 			isc->try_config.bits_pipeline = 0x0;
 		}
 		break;
 	case V4L2_PIX_FMT_YUYV:
 +	case V4L2_PIX_FMT_UYVY:
 +	case V4L2_PIX_FMT_VYUY:
 		/* if sensor format is RAW, we convert inside ISC */
 		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 			isc->try_config.bits_pipeline = CFA_ENABLE |
 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 -				SUB422_ENABLE | CBC_ENABLE;
 +				SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
 		} else {
 			isc->try_config.bits_pipeline = 0x0;
 		}
 		break;
 	case V4L2_PIX_FMT_GREY:
 -		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 +	case V4L2_PIX_FMT_Y16:
 		/* if sensor format is RAW, we convert inside ISC */
 +		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
 			isc->try_config.bits_pipeline = CFA_ENABLE |
 				CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
 -				CBC_ENABLE;
 +				CBC_ENABLE | DPC_BLCENABLE;
 		} else {
 			isc->try_config.bits_pipeline = 0x0;
 		}
 		break;
 	default:
 -		isc->try_config.bits_pipeline = 0x0;
 +		if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
 +			isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
 +		else
 +			isc->try_config.bits_pipeline = 0x0;
 	}
 	/* Tune the pipeline to product specific */
--- a/target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch
+++ b/target/linux/at91/patches-5.10/184-media-atmel-atmel-isc-sama5d2-remove-duplicate-defin.patch
@ -1,26 +0,0 @@
 From b36d11efc134f9f1e2804270d08b9dbefdee4a0d Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:26 +0200
 Subject: [PATCH 184/247] media: atmel: atmel-isc-sama5d2: remove duplicate
 define
 Remove a duplicate definition of clock max divider
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 --
 1 file changed, 2 deletions(-)
 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
@@ -52,8 +52,6 @@
 #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH   2592
 #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT  1944
 -#define ISC_CLK_MAX_DIV		255
 -
 #define ISC_SAMA5D2_PIPELINE \
 	(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
 	CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
--- a/target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch
+++ b/target/linux/at91/patches-5.10/185-media-atmel-atmel-isc-add-microchip-xisc-driver.patch
@ -1,810 +0,0 @@
 From 74fd7ea680cb1a3a43b51a7279aea45efdf9ec42 Mon Sep 17 00:00:00 2001
 From: Eugen Hristev <eugen.hristev@microchip.com>
 Date: Tue, 13 Apr 2021 12:57:29 +0200
 Subject: [PATCH 185/247] media: atmel: atmel-isc: add microchip-xisc driver
 Add driver for the extended variant of the isc, the microchip XISC
 present on sama7g5 product.
 [hverkuil: drop MODULE_SUPPORTED_DEVICE, no longer exists]
 [hverkuil: made isc_sama7g5_config_csc et al static]
 [hverkuil: made sama7g5_controller_formats et al static]
 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 ---
 drivers/media/platform/Makefile               |   1 +
 drivers/media/platform/atmel/Kconfig          |  11 +
 drivers/media/platform/atmel/Makefile         |   2 +
 drivers/media/platform/atmel/atmel-isc-base.c |   2 +-
 drivers/media/platform/atmel/atmel-isc-regs.h |  26 +
 .../media/platform/atmel/atmel-sama7g5-isc.c  | 630 ++++++++++++++++++
 6 files changed, 671 insertions(+), 1 deletion(-)
 create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c
 --- a/drivers/media/platform/Makefile
 +++ b/drivers/media/platform/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN)		+= rcar-vi
 obj-$(CONFIG_VIDEO_ATMEL_ISC)		+= atmel/
 obj-$(CONFIG_VIDEO_ATMEL_ISI)		+= atmel/
 +obj-$(CONFIG_VIDEO_ATMEL_XISC)		+= atmel/
 obj-$(CONFIG_VIDEO_STM32_DCMI)		+= stm32/
 --- a/drivers/media/platform/atmel/Kconfig
 +++ b/drivers/media/platform/atmel/Kconfig
@@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC
 	   This module makes the ATMEL Image Sensor Controller available
 	   as a v4l2 device.
 +config VIDEO_ATMEL_XISC
 +	tristate "ATMEL eXtended Image Sensor Controller (XISC) support"
 +	depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API
 +	depends on ARCH_AT91 || COMPILE_TEST
 +	select VIDEOBUF2_DMA_CONTIG
 +	select REGMAP_MMIO
 +	select V4L2_FWNODE
 +	help
 +	   This module makes the ATMEL eXtended Image Sensor Controller
 +	   available as a v4l2 device.
 +
 config VIDEO_ATMEL_ISI
 	tristate "ATMEL Image Sensor Interface (ISI) support"
 	depends on VIDEO_V4L2 && OF
 --- a/drivers/media/platform/atmel/Makefile
 +++ b/drivers/media/platform/atmel/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o
 +atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o
 obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
 obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o
 +obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o
 --- a/drivers/media/platform/atmel/atmel-isc-base.c
 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
@@ -600,7 +600,7 @@ static int isc_configure(struct isc_devi
 	mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
 	       ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
 	       ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
 -		   ISC_PFE_CFG0_CCIR656;
 +	       ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
 	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
@@ -26,6 +26,7 @@
 #define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
 #define ISC_PFE_CFG0_CCIR656    BIT(9)
 #define ISC_PFE_CFG0_CCIR_CRC   BIT(10)
 +#define ISC_PFE_CFG0_MIPI	BIT(14)
 #define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
 #define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
@@ -184,6 +185,8 @@
 /* ISC Gamma Correction Control Register */
 #define ISC_GAM_CTRL    0x00000094
 +#define ISC_GAM_CTRL_BIPART	BIT(4)
 +
 /* ISC_Gamma Correction Blue Entry Register */
 #define ISC_GAM_BENTRY	0x00000098
@@ -222,6 +225,8 @@
 /* Offset for CSC register specific to sama5d2 product */
 #define ISC_SAMA5D2_CSC_OFFSET	0
 +/* Offset for CSC register specific to sama7g5 product */
 +#define ISC_SAMA7G5_CSC_OFFSET	0x11c
 /* Color Space Conversion Control Register */
 #define ISC_CSC_CTRL    0x00000398
@@ -246,6 +251,8 @@
 /* Offset for CBC register specific to sama5d2 product */
 #define ISC_SAMA5D2_CBC_OFFSET	0
 +/* Offset for CBC register specific to sama7g5 product */
 +#define ISC_SAMA7G5_CBC_OFFSET	0x11c
 /* Contrast And Brightness Control Register */
 #define ISC_CBC_CTRL    0x000003b4
@@ -261,18 +268,30 @@
 #define ISC_CBC_CONTRAST	0x000003c0
 #define ISC_CBC_CONTRAST_MASK	GENMASK(11, 0)
 +/* Hue Register */
 +#define ISC_CBCHS_HUE	0x4e0
 +/* Saturation Register */
 +#define ISC_CBCHS_SAT	0x4e4
 +
 /* Offset for SUB422 register specific to sama5d2 product */
 #define ISC_SAMA5D2_SUB422_OFFSET	0
 +/* Offset for SUB422 register specific to sama7g5 product */
 +#define ISC_SAMA7G5_SUB422_OFFSET	0x124
 +
 /* Subsampling 4:4:4 to 4:2:2 Control Register */
 #define ISC_SUB422_CTRL 0x000003c4
 /* Offset for SUB420 register specific to sama5d2 product */
 #define ISC_SAMA5D2_SUB420_OFFSET	0
 +/* Offset for SUB420 register specific to sama7g5 product */
 +#define ISC_SAMA7G5_SUB420_OFFSET	0x124
 /* Subsampling 4:2:2 to 4:2:0 Control Register */
 #define ISC_SUB420_CTRL 0x000003cc
 /* Offset for RLP register specific to sama5d2 product */
 #define ISC_SAMA5D2_RLP_OFFSET	0
 +/* Offset for RLP register specific to sama7g5 product */
 +#define ISC_SAMA7G5_RLP_OFFSET	0x124
 /* Rounding, Limiting and Packing Configuration Register */
 #define ISC_RLP_CFG     0x000003d0
@@ -303,6 +322,8 @@
 /* Offset for HIS register specific to sama5d2 product */
 #define ISC_SAMA5D2_HIS_OFFSET	0
 +/* Offset for HIS register specific to sama7g5 product */
 +#define ISC_SAMA7G5_HIS_OFFSET	0x124
 /* Histogram Control Register */
 #define ISC_HIS_CTRL	0x000003d4
@@ -326,6 +347,8 @@
 /* Offset for DMA register specific to sama5d2 product */
 #define ISC_SAMA5D2_DMA_OFFSET	0
 +/* Offset for DMA register specific to sama7g5 product */
 +#define ISC_SAMA7G5_DMA_OFFSET	0x13c
 /* DMA Configuration Register */
 #define ISC_DCFG        0x000003e0
@@ -376,11 +399,14 @@
 /* Offset for version register specific to sama5d2 product */
 #define ISC_SAMA5D2_VERSION_OFFSET	0
 +#define ISC_SAMA7G5_VERSION_OFFSET	0x13c
 /* Version Register */
 #define ISC_VERSION	0x0000040c
 /* Offset for version register specific to sama5d2 product */
 #define ISC_SAMA5D2_HIS_ENTRY_OFFSET	0
 +/* Offset for version register specific to sama7g5 product */
 +#define ISC_SAMA7G5_HIS_ENTRY_OFFSET	0x14c
 /* Histogram Entry */
 #define ISC_HIS_ENTRY	0x00000410
 --- /dev/null
 +++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c
@@ -0,0 +1,630 @@
 +// SPDX-License-Identifier: GPL-2.0
 +/*
 + * Microchip eXtended Image Sensor Controller (XISC) driver
 + *
 + * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries
 + *
 + * Author: Eugen Hristev <eugen.hristev@microchip.com>
 + *
 + * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS
 + *
 + * ISC video pipeline integrates the following submodules:
 + * PFE: Parallel Front End to sample the camera sensor input stream
 + * DPC: Defective Pixel Correction with black offset correction, green disparity
 + *      correction and defective pixel correction (3 modules total)
 + *  WB: Programmable white balance in the Bayer domain
 + * CFA: Color filter array interpolation module
 + *  CC: Programmable color correction
 + * GAM: Gamma correction
 + *VHXS: Vertical and Horizontal Scaler
 + * CSC: Programmable color space conversion
 + *CBHS: Contrast Brightness Hue and Saturation control
 + * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling
 + * RLP: This module performs rounding, range limiting
 + *      and packing of the incoming data
 + * DMA: This module performs DMA master accesses to write frames to external RAM
 + * HIS: Histogram module performs statistic counters on the frames
 + */
 +
 +#include <linux/clk.h>
 +#include <linux/clkdev.h>
 +#include <linux/clk-provider.h>
 +#include <linux/delay.h>
 +#include <linux/interrupt.h>
 +#include <linux/math64.h>
 +#include <linux/module.h>
 +#include <linux/of.h>
 +#include <linux/of_graph.h>
 +#include <linux/platform_device.h>
 +#include <linux/pm_runtime.h>
 +#include <linux/regmap.h>
 +#include <linux/videodev2.h>
 +
 +#include <media/v4l2-ctrls.h>
 +#include <media/v4l2-device.h>
 +#include <media/v4l2-event.h>
 +#include <media/v4l2-image-sizes.h>
 +#include <media/v4l2-ioctl.h>
 +#include <media/v4l2-fwnode.h>
 +#include <media/v4l2-subdev.h>
 +#include <media/videobuf2-dma-contig.h>
 +
 +#include "atmel-isc-regs.h"
 +#include "atmel-isc.h"
 +
 +#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH   3264
 +#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT  2464
 +
 +#define ISC_SAMA7G5_PIPELINE \
 +	(WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \
 +	CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE)
 +
 +/* This is a list of the formats that the ISC can *output* */
 +static const struct isc_format sama7g5_controller_formats[] = {
 +	{
 +		.fourcc		= V4L2_PIX_FMT_ARGB444,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_ARGB555,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_RGB565,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_ABGR32,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_XBGR32,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUV420,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_UYVY,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_VYUY,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUYV,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUV422P,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_GREY,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_Y10,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_Y16,
 +	},
 +};
 +
 +/* This is a list of formats that the ISC can receive as *input* */
 +static struct isc_format sama7g5_formats_list[] = {
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SBGGR8,
 +		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGBRG8,
 +		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGRBG8,
 +		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SRGGB8,
 +		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SBGGR10,
 +		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGBRG10,
 +		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGRBG10,
 +		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SRGGB10,
 +		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SBGGR12,
 +		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_BGBG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGBRG12,
 +		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_GBGB,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SGRBG12,
 +		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_GRGR,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_SRGGB12,
 +		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TWELVE,
 +		.cfa_baycfg	= ISC_BAY_CFG_RGRG,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_GREY,
 +		.mbus_code	= MEDIA_BUS_FMT_Y8_1X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_YUYV,
 +		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_UYVY,
 +		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_RGB565,
 +		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
 +		.pfe_cfg0_bps	= ISC_PFE_CFG0_BPS_EIGHT,
 +	},
 +	{
 +		.fourcc		= V4L2_PIX_FMT_Y10,
 +		.mbus_code	= MEDIA_BUS_FMT_Y10_1X10,
 +		.pfe_cfg0_bps	= ISC_PFG_CFG0_BPS_TEN,
 +	},
 +
 +};
 +
 +static void isc_sama7g5_config_csc(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	/* Convert RGB to YUV */
 +	regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,
 +		     0x42 | (0x81 << 16));
 +	regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,
 +		     0x19 | (0x10 << 16));
 +	regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,
 +		     0xFDA | (0xFB6 << 16));
 +	regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,
 +		     0x70 | (0x80 << 16));
 +	regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,
 +		     0x70 | (0xFA2 << 16));
 +	regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,
 +		     0xFEE | (0x80 << 16));
 +}
 +
 +static void isc_sama7g5_config_cbc(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	/* Configure what is set via v4l2 ctrls */
 +	regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness);
 +	regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast);
 +	/* Configure Hue and Saturation as neutral midpoint */
 +	regmap_write(regmap, ISC_CBCHS_HUE, 0);
 +	regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4));
 +}
 +
 +static void isc_sama7g5_config_cc(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	/* Configure each register at the neutral fixed point 1.0 or 0.0 */
 +	regmap_write(regmap, ISC_CC_RR_RG, (1 << 8));
 +	regmap_write(regmap, ISC_CC_RB_OR, 0);
 +	regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16);
 +	regmap_write(regmap, ISC_CC_GB_OG, 0);
 +	regmap_write(regmap, ISC_CC_BR_BG, 0);
 +	regmap_write(regmap, ISC_CC_BB_OB, (1 << 8));
 +}
 +
 +static void isc_sama7g5_config_ctrls(struct isc_device *isc,
 +				     const struct v4l2_ctrl_ops *ops)
 +{
 +	struct isc_ctrls *ctrls = &isc->ctrls;
 +	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
 +
 +	ctrls->contrast = 16;
 +
 +	v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16);
 +}
 +
 +static void isc_sama7g5_config_dpc(struct isc_device *isc)
 +{
 +	u32 bay_cfg = isc->config.sd_format->cfa_baycfg;
 +	struct regmap *regmap = isc->regmap;
 +
 +	regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK,
 +			   (64 << ISC_DPC_CFG_BLOFF_SHIFT));
 +	regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK,
 +			   (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT));
 +}
 +
 +static void isc_sama7g5_config_gam(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +
 +	regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART,
 +			   ISC_GAM_CTRL_BIPART);
 +}
 +
 +static void isc_sama7g5_config_rlp(struct isc_device *isc)
 +{
 +	struct regmap *regmap = isc->regmap;
 +	u32 rlp_mode = isc->config.rlp_cfg_mode;
 +
 +	regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
 +			   ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH |
 +			   ISC_RLP_CFG_YMODE_MASK, rlp_mode);
 +}
 +
 +static void isc_sama7g5_adapt_pipeline(struct isc_device *isc)
 +{
 +	isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE;
 +}
 +
 +/* Gamma table with gamma 1/2.2 */
 +static const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = {
 +	/* index 0 --> gamma bipartite */
 +	{
 +	      0x980,  0x4c0320,  0x650260,  0x7801e0,  0x8701a0,  0x940180,
 +	   0xa00160,  0xab0120,  0xb40120,  0xbd0120,  0xc60100,  0xce0100,
 +	   0xd600e0,  0xdd00e0,  0xe400e0,  0xeb00c0,  0xf100c0,  0xf700c0,
 +	   0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0,
 +	  0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080,
 +	  0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a,
 +	  0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030,
 +	  0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026,
 +	  0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020,
 +	  0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c,
 +	  0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a },
 +};
 +
 +static int xisc_parse_dt(struct device *dev, struct isc_device *isc)
 +{
 +	struct device_node *np = dev->of_node;
 +	struct device_node *epn = NULL;
 +	struct isc_subdev_entity *subdev_entity;
 +	unsigned int flags;
 +	int ret;
 +	bool mipi_mode;
 +
 +	INIT_LIST_HEAD(&isc->subdev_entities);
 +
 +	mipi_mode = of_property_read_bool(np, "microchip,mipi-mode");
 +
 +	while (1) {
 +		struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 };
 +
 +		epn = of_graph_get_next_endpoint(np, epn);
 +		if (!epn)
 +			return 0;
 +
 +		ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn),
 +						 &v4l2_epn);
 +		if (ret) {
 +			ret = -EINVAL;
 +			dev_err(dev, "Could not parse the endpoint\n");
 +			break;
 +		}
 +
 +		subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity),
 +					     GFP_KERNEL);
 +		if (!subdev_entity) {
 +			ret = -ENOMEM;
 +			break;
 +		}
 +		subdev_entity->epn = epn;
 +
 +		flags = v4l2_epn.bus.parallel.flags;
 +
 +		if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
 +			subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW;
 +
 +		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
 +			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW;
 +
 +		if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
 +			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;
 +
 +		if (v4l2_epn.bus_type == V4L2_MBUS_BT656)
 +			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC |
 +					ISC_PFE_CFG0_CCIR656;
 +
 +		if (mipi_mode)
 +			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI;
 +
 +		list_add_tail(&subdev_entity->list, &isc->subdev_entities);
 +	}
 +	of_node_put(epn);
 +
 +	return ret;
 +}
 +
 +static int microchip_xisc_probe(struct platform_device *pdev)
 +{
 +	struct device *dev = &pdev->dev;
 +	struct isc_device *isc;
 +	struct resource *res;
 +	void __iomem *io_base;
 +	struct isc_subdev_entity *subdev_entity;
 +	int irq;
 +	int ret;
 +	u32 ver;
 +
 +	isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
 +	if (!isc)
 +		return -ENOMEM;
 +
 +	platform_set_drvdata(pdev, isc);
 +	isc->dev = dev;
 +
 +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 +	io_base = devm_ioremap_resource(dev, res);
 +	if (IS_ERR(io_base))
 +		return PTR_ERR(io_base);
 +
 +	isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config);
 +	if (IS_ERR(isc->regmap)) {
 +		ret = PTR_ERR(isc->regmap);
 +		dev_err(dev, "failed to init register map: %d\n", ret);
 +		return ret;
 +	}
 +
 +	irq = platform_get_irq(pdev, 0);
 +	if (irq < 0)
 +		return irq;
 +
 +	ret = devm_request_irq(dev, irq, isc_interrupt, 0,
 +			       "microchip-sama7g5-xisc", isc);
 +	if (ret < 0) {
 +		dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
 +			irq, ret);
 +		return ret;
 +	}
 +
 +	isc->gamma_table = isc_sama7g5_gamma_table;
 +	isc->gamma_max = 0;
 +
 +	isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH;
 +	isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT;
 +
 +	isc->config_dpc = isc_sama7g5_config_dpc;
 +	isc->config_csc = isc_sama7g5_config_csc;
 +	isc->config_cbc = isc_sama7g5_config_cbc;
 +	isc->config_cc = isc_sama7g5_config_cc;
 +	isc->config_gam = isc_sama7g5_config_gam;
 +	isc->config_rlp = isc_sama7g5_config_rlp;
 +	isc->config_ctrls = isc_sama7g5_config_ctrls;
 +
 +	isc->adapt_pipeline = isc_sama7g5_adapt_pipeline;
 +
 +	isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET;
 +	isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET;
 +	isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET;
 +	isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET;
 +	isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET;
 +	isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET;
 +	isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET;
 +	isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET;
 +	isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET;
 +
 +	isc->controller_formats = sama7g5_controller_formats;
 +	isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats);
 +	isc->formats_list = sama7g5_formats_list;
 +	isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list);
 +
 +	/* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */
 +	isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32;
 +
 +	ret = isc_pipeline_init(isc);
 +	if (ret)
 +		return ret;
 +
 +	isc->hclock = devm_clk_get(dev, "hclock");
 +	if (IS_ERR(isc->hclock)) {
 +		ret = PTR_ERR(isc->hclock);
 +		dev_err(dev, "failed to get hclock: %d\n", ret);
 +		return ret;
 +	}
 +
 +	ret = clk_prepare_enable(isc->hclock);
 +	if (ret) {
 +		dev_err(dev, "failed to enable hclock: %d\n", ret);
 +		return ret;
 +	}
 +
 +	ret = isc_clk_init(isc);
 +	if (ret) {
 +		dev_err(dev, "failed to init isc clock: %d\n", ret);
 +		goto unprepare_hclk;
 +	}
 +
 +	isc->ispck = isc->isc_clks[ISC_ISPCK].clk;
 +
 +	ret = clk_prepare_enable(isc->ispck);
 +	if (ret) {
 +		dev_err(dev, "failed to enable ispck: %d\n", ret);
 +		goto unprepare_hclk;
 +	}
 +
 +	/* ispck should be greater or equal to hclock */
 +	ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock));
 +	if (ret) {
 +		dev_err(dev, "failed to set ispck rate: %d\n", ret);
 +		goto unprepare_clk;
 +	}
 +
 +	ret = v4l2_device_register(dev, &isc->v4l2_dev);
 +	if (ret) {
 +		dev_err(dev, "unable to register v4l2 device.\n");
 +		goto unprepare_clk;
 +	}
 +
 +	ret = xisc_parse_dt(dev, isc);
 +	if (ret) {
 +		dev_err(dev, "fail to parse device tree\n");
 +		goto unregister_v4l2_device;
 +	}
 +
 +	if (list_empty(&isc->subdev_entities)) {
 +		dev_err(dev, "no subdev found\n");
 +		ret = -ENODEV;
 +		goto unregister_v4l2_device;
 +	}
 +
 +	list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
 +		struct v4l2_async_subdev *asd;
 +
 +		v4l2_async_notifier_init(&subdev_entity->notifier);
 +
 +		asd = v4l2_async_notifier_add_fwnode_remote_subdev(
 +					&subdev_entity->notifier,
 +					of_fwnode_handle(subdev_entity->epn),
 +					struct v4l2_async_subdev);
 +
 +		of_node_put(subdev_entity->epn);
 +		subdev_entity->epn = NULL;
 +
 +		if (IS_ERR(asd)) {
 +			ret = PTR_ERR(asd);
 +			goto cleanup_subdev;
 +		}
 +
 +		subdev_entity->notifier.ops = &isc_async_ops;
 +
 +		ret = v4l2_async_notifier_register(&isc->v4l2_dev,
 +						   &subdev_entity->notifier);
 +		if (ret) {
 +			dev_err(dev, "fail to register async notifier\n");
 +			goto cleanup_subdev;
 +		}
 +
 +		if (video_is_registered(&isc->video_dev))
 +			break;
 +	}
 +
 +	pm_runtime_set_active(dev);
 +	pm_runtime_enable(dev);
 +	pm_request_idle(dev);
 +
 +	regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);
 +	dev_info(dev, "Microchip XISC version %x\n", ver);
 +
 +	return 0;
 +
 +cleanup_subdev:
 +	isc_subdev_cleanup(isc);
 +
 +unregister_v4l2_device:
 +	v4l2_device_unregister(&isc->v4l2_dev);
 +
 +unprepare_clk:
 +	clk_disable_unprepare(isc->ispck);
 +unprepare_hclk:
 +	clk_disable_unprepare(isc->hclock);
 +
 +	isc_clk_cleanup(isc);
 +
 +	return ret;
 +}
 +
 +static int microchip_xisc_remove(struct platform_device *pdev)
 +{
 +	struct isc_device *isc = platform_get_drvdata(pdev);
 +
 +	pm_runtime_disable(&pdev->dev);
 +
 +	isc_subdev_cleanup(isc);
 +
 +	v4l2_device_unregister(&isc->v4l2_dev);
 +
 +	clk_disable_unprepare(isc->ispck);
 +	clk_disable_unprepare(isc->hclock);
 +
 +	isc_clk_cleanup(isc);
 +
 +	return 0;
 +}
 +
 +static int __maybe_unused xisc_runtime_suspend(struct device *dev)
 +{
 +	struct isc_device *isc = dev_get_drvdata(dev);
 +
 +	clk_disable_unprepare(isc->ispck);
 +	clk_disable_unprepare(isc->hclock);
 +
 +	return 0;
 +}
 +
 +static int __maybe_unused xisc_runtime_resume(struct device *dev)
 +{
 +	struct isc_device *isc = dev_get_drvdata(dev);
 +	int ret;
 +
 +	ret = clk_prepare_enable(isc->hclock);
 +	if (ret)
 +		return ret;
 +
 +	ret = clk_prepare_enable(isc->ispck);
 +	if (ret)
 +		clk_disable_unprepare(isc->hclock);
 +
 +	return ret;
 +}
 +
 +static const struct dev_pm_ops microchip_xisc_dev_pm_ops = {
 +	SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL)
 +};
 +
 +static const struct of_device_id microchip_xisc_of_match[] = {
 +	{ .compatible = "microchip,sama7g5-isc" },
 +	{ }
 +};
 +MODULE_DEVICE_TABLE(of, microchip_xisc_of_match);
 +
 +static struct platform_driver microchip_xisc_driver = {
 +	.probe	= microchip_xisc_probe,
 +	.remove	= microchip_xisc_remove,
 +	.driver	= {
 +		.name		= "microchip-sama7g5-xisc",
 +		.pm		= &microchip_xisc_dev_pm_ops,
 +		.of_match_table = of_match_ptr(microchip_xisc_of_match),
 +	},
 +};
 +
 +module_platform_driver(microchip_xisc_driver);
 +
 +MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com>");
 +MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC");
 +MODULE_LICENSE("GPL v2");
--- a/target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch
+++ b/target/linux/at91/patches-5.10/186-ASoC-atmel-fix-shadowed-variable.patch
@ -1,48 +0,0 @@
 From 1b41c69264d7233a3e9a0aa36333ee22a5a049e9 Mon Sep 17 00:00:00 2001
 From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
 Date: Fri, 26 Mar 2021 16:59:12 -0500
 Subject: [PATCH 186/247] ASoC: atmel: fix shadowed variable
 Fix cppcheck warning:
 sound/soc/atmel/atmel-classd.c:51:14: style: Local variable 'pwm_type'
 shadows outer variable [shadowVariable]
 const char *pwm_type;
             ^
 sound/soc/atmel/atmel-classd.c:226:27: note: Shadowed declaration
 static const char * const pwm_type[] = {
                          ^
 sound/soc/atmel/atmel-classd.c:51:14: note: Shadow variable
 const char *pwm_type;
             ^
 Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
 Reviewed-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 Link: https://lore.kernel.org/r/20210326215927.936377-3-pierre-louis.bossart@linux.intel.com
 Signed-off-by: Mark Brown <broonie@kernel.org>
 ---
 sound/soc/atmel/atmel-classd.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
 --- a/sound/soc/atmel/atmel-classd.c
 +++ b/sound/soc/atmel/atmel-classd.c
@@ -48,7 +48,7 @@ static struct atmel_classd_pdata *atmel_
 {
 	struct device_node *np = dev->of_node;
 	struct atmel_classd_pdata *pdata;
 -	const char *pwm_type;
 +	const char *pwm_type_s;
 	int ret;
 	if (!np) {
@@ -60,8 +60,8 @@ static struct atmel_classd_pdata *atmel_
 	if (!pdata)
 		return ERR_PTR(-ENOMEM);
 -	ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type);
 -	if ((ret == 0) && (strcmp(pwm_type, "diff") == 0))
 +	ret = of_property_read_string(np, "atmel,pwm-type", &pwm_type_s);
 +	if ((ret == 0) && (strcmp(pwm_type_s, "diff") == 0))
 		pdata->pwm_type = CLASSD_MR_PWMTYP_DIFF;
 	else
 		pdata->pwm_type = CLASSD_MR_PWMTYP_SINGLE;
--- a/Show More
+++ b/Show More
		`@ -1,2 +0,0 @@`
			`LINUX_VERSION-5.10 = .179`
			`LINUX_KERNEL_HASH-5.10.179 = 1bbd445c154b053eea46acc883be548a98179988a9ed3a0b81bddfbf30a37e29`