diff --git a/target/linux/stm32/base-files/etc/board.d/02_network b/target/linux/stm32/base-files/etc/board.d/02_network index a96fada9a4e..c21d8c329eb 100644 --- a/target/linux/stm32/base-files/etc/board.d/02_network +++ b/target/linux/stm32/base-files/etc/board.d/02_network @@ -11,6 +11,10 @@ case "$board" in st,stm32mp135f-dk) ucidef_set_interfaces_lan_wan "eth0" "eth1" ;; +st,stm32mp157c-dk2 | \ +st,stm32mp157c-dk2-scmi) + ucidef_set_interface_lan "eth0" + ;; esac board_config_flush diff --git a/target/linux/stm32/image/Makefile b/target/linux/stm32/image/Makefile index 77c25edaf89..016d86bf95d 100644 --- a/target/linux/stm32/image/Makefile +++ b/target/linux/stm32/image/Makefile @@ -58,6 +58,23 @@ define Device/stm32mp135f-dk SUPPORTED_DEVICES := st,stm32mp135f-dk endef -TARGET_DEVICES += stm32mp135f-dk +define Device/stm32mp157c-dk2 + DEVICE_MODEL := STM32MP157C-DK2 + DEVICE_DTS := stm32mp157c-dk2 + SUPPORTED_DEVICES := st,stm32mp157c-dk2 \ + st,stm32mp157f-dk2 +endef + +define Device/stm32mp157c-dk2-scmi + DEVICE_MODEL := STM32MP157C-DK2 + DEVICE_VARIANT := SCMI + DEVICE_DTS := stm32mp157c-dk2-scmi + SUPPORTED_DEVICES := st,stm32mp157c-dk2-scmi \ + st,stm32mp157f-dk2-scmi +endef + +TARGET_DEVICES += stm32mp135f-dk \ + stm32mp157c-dk2 \ + stm32mp157c-dk2-scmi $(eval $(call BuildImage)) diff --git a/target/linux/stm32/patches-6.6/009-net-stmmac-dwmac-stm32-Add-test-to-verify-if-ETHCK-i.patch b/target/linux/stm32/patches-6.6/009-net-stmmac-dwmac-stm32-Add-test-to-verify-if-ETHCK-i.patch new file mode 100644 index 00000000000..8cec988556e --- /dev/null +++ b/target/linux/stm32/patches-6.6/009-net-stmmac-dwmac-stm32-Add-test-to-verify-if-ETHCK-i.patch @@ -0,0 +1,32 @@ +From 3cd1d4651cebe9776a0142ade36ff9f2e3545436 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 1 Jul 2024 08:48:37 +0200 +Subject: [PATCH] net: stmmac: dwmac-stm32: Add test to verify if ETHCK is used + before checking clk rate + +When we want to use clock from RCC to clock Ethernet PHY (with ETHCK) +we need to check if value of clock rate is authorized. +If ETHCK is unused, the ETHCK frequency is 0Hz and validation fails. +It makes no sense to validate unused ETHCK, so skip the validation. + +Fixes: 582ac134963e ("net: stmmac: dwmac-stm32: Separate out external clock rate validation") +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Tested-by: Mark Brown +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -195,6 +195,9 @@ static int stm32mp1_validate_ethck_rate( + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck); + ++ if (!dwmac->enable_eth_ck) ++ return 0; ++ + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: diff --git a/target/linux/stm32/patches-6.6/010-net-stmmac-dwmac-stm32-update-err-status-in-case-dif.patch b/target/linux/stm32/patches-6.6/010-net-stmmac-dwmac-stm32-update-err-status-in-case-dif.patch new file mode 100644 index 00000000000..c9d6356e492 --- /dev/null +++ b/target/linux/stm32/patches-6.6/010-net-stmmac-dwmac-stm32-update-err-status-in-case-dif.patch @@ -0,0 +1,39 @@ +From f8dbe58e2f1a3c091531b3f8ef86b393ceee67d1 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 1 Jul 2024 08:48:38 +0200 +Subject: [PATCH] net: stmmac: dwmac-stm32: update err status in case different + of stm32mp13 + +The mask parameter of syscfg property is mandatory for MP13 but +optional for all other cases. +The function should not return error code because for non-MP13 +the missing syscfg phandle in DT is not considered an error. +So reset err to 0 in that case to support existing DTs without +syscfg phandle. + +Fixes: 50bbc0393114 ("net: stmmac: dwmac-stm32: add management of stm32mp13 for stm32") +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Tested-by: Mark Brown +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -371,10 +371,12 @@ static int stm32_dwmac_parse_data(struct + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; + err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); + if (err) { +- if (dwmac->ops->is_mp13) ++ if (dwmac->ops->is_mp13) { + dev_err(dev, "Sysconfig register mask must be set (%d)\n", err); +- else ++ } else { + dev_dbg(dev, "Warning sysconfig register mask not set\n"); ++ err = 0; ++ } + } + + return err; diff --git a/target/linux/stm32/patches-6.6/009-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch b/target/linux/stm32/patches-6.6/020-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch similarity index 100% rename from target/linux/stm32/patches-6.6/009-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch rename to target/linux/stm32/patches-6.6/020-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch diff --git a/target/linux/stm32/patches-6.6/010-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch b/target/linux/stm32/patches-6.6/021-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch similarity index 100% rename from target/linux/stm32/patches-6.6/010-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch rename to target/linux/stm32/patches-6.6/021-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch diff --git a/target/linux/stm32/patches-6.6/011-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch b/target/linux/stm32/patches-6.6/022-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch similarity index 100% rename from target/linux/stm32/patches-6.6/011-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch rename to target/linux/stm32/patches-6.6/022-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch diff --git a/target/linux/stm32/patches-6.6/012-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch b/target/linux/stm32/patches-6.6/023-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch similarity index 100% rename from target/linux/stm32/patches-6.6/012-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch rename to target/linux/stm32/patches-6.6/023-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch diff --git a/target/linux/stm32/patches-6.6/013-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch b/target/linux/stm32/patches-6.6/024-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch similarity index 100% rename from target/linux/stm32/patches-6.6/013-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch rename to target/linux/stm32/patches-6.6/024-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch diff --git a/target/linux/stm32/patches-6.6/035-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch b/target/linux/stm32/patches-6.6/035-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch new file mode 100644 index 00000000000..2e8d7010eeb --- /dev/null +++ b/target/linux/stm32/patches-6.6/035-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch @@ -0,0 +1,30 @@ +From d6b0d7a941c4fc9241d9cca66db5d8ff9d81cc8b Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Tue, 27 Aug 2024 16:04:47 +0200 +Subject: [PATCH] ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15 + +Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin +for RTC OUT2_RMP, in stm32mp15-pinctrl.dtsi. + +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +@@ -1467,6 +1467,13 @@ + }; + }; + ++ /omit-if-no-ref/ ++ rtc_rsvd_pins_a: rtc-rsvd-0 { ++ pins { ++ pinmux = ; /* RTC_OUT2_RMP */ ++ }; ++ }; ++ + sai2a_pins_a: sai2a-0 { + pins { + pinmux = , /* SAI2_SCK_A */ diff --git a/target/linux/stm32/patches-6.6/036-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch b/target/linux/stm32/patches-6.6/036-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch new file mode 100644 index 00000000000..338f61be0d6 --- /dev/null +++ b/target/linux/stm32/patches-6.6/036-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch @@ -0,0 +1,36 @@ +From c24e7ae60d3e97799998466a4220ef6ffa0e4c94 Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Tue, 27 Aug 2024 16:04:49 +0200 +Subject: [PATCH] ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on + stm32mp157c-dk2 + +On stm32mp157c-dk2 board, WLAN/BT module LPO_IN pin is wired to +RTC OUT2_RMP pin. + +Provide a pinctrl configuration to enable LSCO on OUT2_RMP. + +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +@@ -84,6 +84,16 @@ + }; + }; + ++&rtc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_rsvd_pins_a>; ++ ++ rtc_lsco_pins_a: rtc-lsco-0 { ++ pins = "out2_rmp"; ++ function = "lsco"; ++ }; ++}; ++ + &usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; diff --git a/target/linux/stm32/patches-6.6/037-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp157c-.patch b/target/linux/stm32/patches-6.6/037-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp157c-.patch new file mode 100644 index 00000000000..50e2fbcae20 --- /dev/null +++ b/target/linux/stm32/patches-6.6/037-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp157c-.patch @@ -0,0 +1,76 @@ +From 315fe7667c03c1f853e1a7038c28f23621a44a3d Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Tue, 27 Aug 2024 16:04:51 +0200 +Subject: [PATCH] ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2 + +Add support of WLAN/BT Murata Type 1DX module: +- usart2 is used for Bluetooth interface +- sdmmc2 is used for WLAN (sdio) interface + +Signed-off-by: Christophe Roullier +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 41 +++++++++++++++++++++++- + 1 file changed, 40 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +@@ -24,6 +24,11 @@ + chosen { + stdout-path = "serial0:115200n8"; + }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; ++ }; + }; + + &cryp1 { +@@ -94,10 +99,44 @@ + }; + }; + ++/* Wifi */ ++&sdmmc2 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; ++ non-removable; ++ cap-sdio-irq; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_lsco_pins_a>; ++ }; ++}; ++ ++/* Bluetooth */ + &usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; +- status = "disabled"; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3>; ++ vddio-supply = <&v3v3>; ++ }; + }; diff --git a/target/linux/stm32/patches-6.6/040-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch b/target/linux/stm32/patches-6.6/040-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch new file mode 100644 index 00000000000..543ca1a8e3f --- /dev/null +++ b/target/linux/stm32/patches-6.6/040-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch @@ -0,0 +1,2974 @@ +From ad95b569993b0735a58b08c00cd4131fa5e83376 Mon Sep 17 00:00:00 2001 +From: Gatien Chevallier +Date: Fri, 5 Jan 2024 14:04:01 +0100 +Subject: [PATCH] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x + boards + +ETZPC is a firewall controller. Put all peripherals filtered by the +ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for +backward compatibility. + +Signed-off-by: Gatien Chevallier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp151.dtsi | 2676 +++++++++++++------------ + arch/arm/boot/dts/st/stm32mp153.dtsi | 50 +- + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 18 +- + 3 files changed, 1375 insertions(+), 1369 deletions(-) + +--- a/arch/arm/boot/dts/st/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi +@@ -123,1541 +123,1549 @@ + interrupt-parent = <&intc>; + ranges; + +- timers2: timer@40000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM2_K>; +- clock-names = "int"; +- dmas = <&dmamux1 18 0x400 0x1>, +- <&dmamux1 19 0x400 0x1>, +- <&dmamux1 20 0x400 0x1>, +- <&dmamux1 21 0x400 0x1>, +- <&dmamux1 22 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up"; ++ ipcc: mailbox@4c001000 { ++ compatible = "st,stm32mp1-ipcc"; ++ #mbox-cells = <1>; ++ reg = <0x4c001000 0x400>; ++ st,proc-id = <0>; ++ interrupts-extended = ++ <&exti 61 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "rx", "tx"; ++ clocks = <&rcc IPCC>; ++ wakeup-source; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@1 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; + }; + +- timers3: timer@40001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM3_K>; +- clock-names = "int"; +- dmas = <&dmamux1 23 0x400 0x1>, +- <&dmamux1 24 0x400 0x1>, +- <&dmamux1 25 0x400 0x1>, +- <&dmamux1 26 0x400 0x1>, +- <&dmamux1 27 0x400 0x1>, +- <&dmamux1 28 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@2 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; ++ rcc: rcc@50000000 { ++ compatible = "st,stm32mp1-rcc", "syscon"; ++ reg = <0x50000000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; + }; + +- timers4: timer@40002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40002000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM4_K>; +- clock-names = "int"; +- dmas = <&dmamux1 29 0x400 0x1>, +- <&dmamux1 30 0x400 0x1>, +- <&dmamux1 31 0x400 0x1>, +- <&dmamux1 32 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4"; +- status = "disabled"; ++ pwr_regulators: pwr@50001000 { ++ compatible = "st,stm32mp1,pwr-reg"; ++ reg = <0x50001000 0x10>; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; ++ reg11: reg11 { ++ regulator-name = "reg11"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; + }; + +- timer@3 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <3>; +- status = "disabled"; ++ reg18: reg18 { ++ regulator-name = "reg18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; + }; + +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; ++ usb33: usb33 { ++ regulator-name = "usb33"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + }; + }; + +- timers5: timer@40003000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40003000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM5_K>; +- clock-names = "int"; +- dmas = <&dmamux1 55 0x400 0x1>, +- <&dmamux1 56 0x400 0x1>, +- <&dmamux1 57 0x400 0x1>, +- <&dmamux1 58 0x400 0x1>, +- <&dmamux1 59 0x400 0x1>, +- <&dmamux1 60 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@4 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <4>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; ++ pwr_mcu: pwr_mcu@50001014 { ++ compatible = "st,stm32mp151-pwr-mcu", "syscon"; ++ reg = <0x50001014 0x4>; + }; + +- timers6: timer@40004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40004000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM6_K>; +- clock-names = "int"; +- dmas = <&dmamux1 69 0x400 0x1>; +- dma-names = "up"; +- status = "disabled"; +- +- timer@5 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <5>; +- status = "disabled"; +- }; ++ exti: interrupt-controller@5000d000 { ++ compatible = "st,stm32mp1-exti", "syscon"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ reg = <0x5000d000 0x400>; + }; + +- timers7: timer@40005000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40005000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM7_K>; +- clock-names = "int"; +- dmas = <&dmamux1 70 0x400 0x1>; +- dma-names = "up"; +- status = "disabled"; +- +- timer@6 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <6>; +- status = "disabled"; +- }; ++ syscfg: syscon@50020000 { ++ compatible = "st,stm32mp157-syscfg", "syscon"; ++ reg = <0x50020000 0x400>; ++ clocks = <&rcc SYSCFG>; + }; + +- timers12: timer@40006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40006000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM12_K>; +- clock-names = "int"; ++ dts: thermal@50028000 { ++ compatible = "st,stm32-thermal"; ++ reg = <0x50028000 0x100>; ++ interrupts = ; ++ clocks = <&rcc TMPSENS>; ++ clock-names = "pclk"; ++ #thermal-sensor-cells = <0>; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@11 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <11>; +- status = "disabled"; +- }; + }; + +- timers13: timer@40007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40007000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM13_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@12 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <12>; +- status = "disabled"; +- }; ++ mdma1: dma-controller@58000000 { ++ compatible = "st,stm32h7-mdma"; ++ reg = <0x58000000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc MDMA>; ++ resets = <&rcc MDMA_R>; ++ #dma-cells = <5>; ++ dma-channels = <32>; ++ dma-requests = <48>; + }; + +- timers14: timer@40008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40008000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM14_K>; +- clock-names = "int"; ++ sdmmc1: mmc@58005000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x00253180>; ++ reg = <0x58005000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc SDMMC1_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC1_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <120000000>; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@13 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <13>; +- status = "disabled"; +- }; + }; + +- lptimer1: timer@40009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x40009000 0x400>; +- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM1_K>; +- clock-names = "mux"; +- wakeup-source; ++ sdmmc2: mmc@58007000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x00253180>; ++ reg = <0x58007000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc SDMMC2_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC2_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <120000000>; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@0 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; + }; + +- spi2: spi@4000b000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI2_K>; +- resets = <&rcc SPI2_R>; +- dmas = <&dmamux1 39 0x400 0x05>, +- <&dmamux1 40 0x400 0x05>; +- dma-names = "rx", "tx"; ++ crc1: crc@58009000 { ++ compatible = "st,stm32f7-crc"; ++ reg = <0x58009000 0x400>; ++ clocks = <&rcc CRC1>; + status = "disabled"; + }; + +- i2s2: audio-controller@4000b000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 39 0x400 0x01>, +- <&dmamux1 40 0x400 0x01>; +- dma-names = "rx", "tx"; ++ usbh_ohci: usb@5800c000 { ++ compatible = "generic-ohci"; ++ reg = <0x5800c000 0x1000>; ++ clocks = <&usbphyc>, <&rcc USBH>; ++ resets = <&rcc USBH_R>; ++ interrupts = ; + status = "disabled"; + }; + +- spi3: spi@4000c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI3_K>; +- resets = <&rcc SPI3_R>; +- dmas = <&dmamux1 61 0x400 0x05>, +- <&dmamux1 62 0x400 0x05>; +- dma-names = "rx", "tx"; ++ usbh_ehci: usb@5800d000 { ++ compatible = "generic-ehci"; ++ reg = <0x5800d000 0x1000>; ++ clocks = <&usbphyc>, <&rcc USBH>; ++ resets = <&rcc USBH_R>; ++ interrupts = ; ++ companion = <&usbh_ohci>; + status = "disabled"; + }; + +- i2s3: audio-controller@4000c000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 61 0x400 0x01>, +- <&dmamux1 62 0x400 0x01>; +- dma-names = "rx", "tx"; ++ ltdc: display-controller@5a001000 { ++ compatible = "st,stm32-ltdc"; ++ reg = <0x5a001000 0x400>; ++ interrupts = , ++ ; ++ clocks = <&rcc LTDC_PX>; ++ clock-names = "lcd"; ++ resets = <&rcc LTDC_R>; + status = "disabled"; + }; + +- spdifrx: audio-controller@4000d000 { +- compatible = "st,stm32h7-spdifrx"; +- #sound-dai-cells = <0>; +- reg = <0x4000d000 0x400>; +- clocks = <&rcc SPDIF_K>; +- clock-names = "kclk"; +- interrupts = ; +- dmas = <&dmamux1 93 0x400 0x01>, +- <&dmamux1 94 0x400 0x01>; +- dma-names = "rx", "rx-ctrl"; ++ iwdg2: watchdog@5a002000 { ++ compatible = "st,stm32mp1-iwdg"; ++ reg = <0x5a002000 0x400>; ++ clocks = <&rcc IWDG2>, <&rcc CK_LSI>; ++ clock-names = "pclk", "lsi"; + status = "disabled"; + }; + +- usart2: serial@4000e000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4000e000 0x400>; +- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART2_K>; +- wakeup-source; +- dmas = <&dmamux1 43 0x400 0x15>, +- <&dmamux1 44 0x400 0x11>; +- dma-names = "rx", "tx"; ++ usbphyc: usbphyc@5a006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "st,stm32mp1-usbphyc"; ++ reg = <0x5a006000 0x1000>; ++ clocks = <&rcc USBPHY_K>; ++ resets = <&rcc USBPHY_R>; ++ vdda1v1-supply = <®11>; ++ vdda1v8-supply = <®18>; + status = "disabled"; +- }; + +- usart3: serial@4000f000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4000f000 0x400>; +- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART3_K>; +- wakeup-source; +- dmas = <&dmamux1 45 0x400 0x15>, +- <&dmamux1 46 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ usbphyc_port0: usb-phy@0 { ++ #phy-cells = <0>; ++ reg = <0>; ++ }; + +- uart4: serial@40010000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40010000 0x400>; +- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART4_K>; +- wakeup-source; +- dmas = <&dmamux1 63 0x400 0x15>, +- <&dmamux1 64 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; ++ usbphyc_port1: usb-phy@1 { ++ #phy-cells = <1>; ++ reg = <1>; ++ }; + }; + +- uart5: serial@40011000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40011000 0x400>; +- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART5_K>; +- wakeup-source; +- dmas = <&dmamux1 65 0x400 0x15>, +- <&dmamux1 66 0x400 0x11>; +- dma-names = "rx", "tx"; ++ rtc: rtc@5c004000 { ++ compatible = "st,stm32mp1-rtc"; ++ reg = <0x5c004000 0x400>; ++ clocks = <&rcc RTCAPB>, <&rcc RTC>; ++ clock-names = "pclk", "rtc_ck"; ++ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + +- i2c1: i2c@40012000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40012000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C1_K>; +- resets = <&rcc I2C1_R>; ++ bsec: efuse@5c005000 { ++ compatible = "st,stm32mp15-bsec"; ++ reg = <0x5c005000 0x400>; + #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x1>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; ++ #size-cells = <1>; ++ part_number_otp: part-number-otp@4 { ++ reg = <0x4 0x1>; ++ }; ++ vrefint: vrefin-cal@52 { ++ reg = <0x52 0x2>; ++ }; ++ ts_cal1: calib@5c { ++ reg = <0x5c 0x2>; ++ }; ++ ts_cal2: calib@5e { ++ reg = <0x5e 0x2>; ++ }; + }; + +- i2c2: i2c@40013000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40013000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C2_K>; +- resets = <&rcc I2C2_R>; ++ etzpc: bus@5c007000 { ++ compatible = "simple-bus"; ++ reg = <0x5c007000 0x400>; + #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x2>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ #size-cells = <1>; ++ ranges; + +- i2c3: i2c@40014000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40014000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C3_K>; +- resets = <&rcc I2C3_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x4>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ timers2: timer@40000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40000000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM2_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 18 0x400 0x1>, ++ <&dmamux1 19 0x400 0x1>, ++ <&dmamux1 20 0x400 0x1>, ++ <&dmamux1 21 0x400 0x1>, ++ <&dmamux1 22 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", "up"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- i2c5: i2c@40015000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40015000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C5_K>; +- resets = <&rcc I2C5_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x10>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ timer@1 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <1>; ++ status = "disabled"; ++ }; + +- cec: cec@40016000 { +- compatible = "st,stm32-cec"; +- reg = <0x40016000 0x400>; +- interrupts = ; +- clocks = <&rcc CEC_K>, <&rcc CEC>; +- clock-names = "cec", "hdmi-cec"; +- status = "disabled"; +- }; ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; ++ }; + +- dac: dac@40017000 { +- compatible = "st,stm32h7-dac-core"; +- reg = <0x40017000 0x400>; +- clocks = <&rcc DAC12>; +- clock-names = "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; ++ timers3: timer@40001000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40001000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM3_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 23 0x400 0x1>, ++ <&dmamux1 24 0x400 0x1>, ++ <&dmamux1 25 0x400 0x1>, ++ <&dmamux1 26 0x400 0x1>, ++ <&dmamux1 27 0x400 0x1>, ++ <&dmamux1 28 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- dac1: dac@1 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <1>; +- status = "disabled"; ++ timer@2 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; + +- dac2: dac@2 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <2>; +- status = "disabled"; ++ timers4: timer@40002000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40002000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM4_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 29 0x400 0x1>, ++ <&dmamux1 30 0x400 0x1>, ++ <&dmamux1 31 0x400 0x1>, ++ <&dmamux1 32 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@3 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <3>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; +- }; + +- uart7: serial@40018000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40018000 0x400>; +- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART7_K>; +- wakeup-source; +- dmas = <&dmamux1 79 0x400 0x15>, +- <&dmamux1 80 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ timers5: timer@40003000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40003000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM5_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 55 0x400 0x1>, ++ <&dmamux1 56 0x400 0x1>, ++ <&dmamux1 57 0x400 0x1>, ++ <&dmamux1 58 0x400 0x1>, ++ <&dmamux1 59 0x400 0x1>, ++ <&dmamux1 60 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- uart8: serial@40019000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40019000 0x400>; +- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART8_K>; +- wakeup-source; +- dmas = <&dmamux1 81 0x400 0x15>, +- <&dmamux1 82 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ timer@4 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <4>; ++ status = "disabled"; ++ }; + +- timers1: timer@44000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44000000 0x400>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "brk", "up", "trg-com", "cc"; +- clocks = <&rcc TIM1_K>; +- clock-names = "int"; +- dmas = <&dmamux1 11 0x400 0x1>, +- <&dmamux1 12 0x400 0x1>, +- <&dmamux1 13 0x400 0x1>, +- <&dmamux1 14 0x400 0x1>, +- <&dmamux1 15 0x400 0x1>, +- <&dmamux1 16 0x400 0x1>, +- <&dmamux1 17 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", +- "up", "trig", "com"; +- status = "disabled"; ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; ++ }; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; ++ timers6: timer@40004000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40004000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM6_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 69 0x400 0x1>; ++ dma-names = "up"; + status = "disabled"; ++ ++ timer@5 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <5>; ++ status = "disabled"; ++ }; + }; + +- timer@0 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <0>; ++ timers7: timer@40005000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40005000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM7_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 70 0x400 0x1>; ++ dma-names = "up"; + status = "disabled"; ++ ++ timer@6 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <6>; ++ status = "disabled"; ++ }; + }; + +- counter { +- compatible = "st,stm32-timer-counter"; ++ timers12: timer@40006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40006000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM12_K>; ++ clock-names = "int"; + status = "disabled"; +- }; +- }; + +- timers8: timer@44001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44001000 0x400>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "brk", "up", "trg-com", "cc"; +- clocks = <&rcc TIM8_K>; +- clock-names = "int"; +- dmas = <&dmamux1 47 0x400 0x1>, +- <&dmamux1 48 0x400 0x1>, +- <&dmamux1 49 0x400 0x1>, +- <&dmamux1 50 0x400 0x1>, +- <&dmamux1 51 0x400 0x1>, +- <&dmamux1 52 0x400 0x1>, +- <&dmamux1 53 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", +- "up", "trig", "com"; +- status = "disabled"; ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; ++ timer@11 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <11>; ++ status = "disabled"; ++ }; + }; + +- timer@7 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <7>; ++ timers13: timer@40007000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40007000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM13_K>; ++ clock-names = "int"; + status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@12 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <12>; ++ status = "disabled"; ++ }; + }; + +- counter { +- compatible = "st,stm32-timer-counter"; ++ timers14: timer@40008000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40008000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM14_K>; ++ clock-names = "int"; + status = "disabled"; +- }; +- }; + +- usart6: serial@44003000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x44003000 0x400>; +- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART6_K>; +- wakeup-source; +- dmas = <&dmamux1 71 0x400 0x15>, +- <&dmamux1 72 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- spi1: spi@44004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44004000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI1_K>; +- resets = <&rcc SPI1_R>; +- dmas = <&dmamux1 37 0x400 0x05>, +- <&dmamux1 38 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ timer@13 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <13>; ++ status = "disabled"; ++ }; ++ }; + +- i2s1: audio-controller@44004000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x44004000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 37 0x400 0x01>, +- <&dmamux1 38 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ lptimer1: timer@40009000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x40009000 0x400>; ++ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM1_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; + +- spi4: spi@44005000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44005000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI4_K>; +- resets = <&rcc SPI4_R>; +- dmas = <&dmamux1 83 0x400 0x05>, +- <&dmamux1 84 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- timers15: timer@44006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44006000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM15_K>; +- clock-names = "int"; +- dmas = <&dmamux1 105 0x400 0x1>, +- <&dmamux1 106 0x400 0x1>, +- <&dmamux1 107 0x400 0x1>, +- <&dmamux1 108 0x400 0x1>; +- dma-names = "ch1", "up", "trig", "com"; +- status = "disabled"; ++ trigger@0 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <0>; ++ status = "disabled"; ++ }; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; ++ counter { ++ compatible = "st,stm32-lptimer-counter"; ++ status = "disabled"; ++ }; + }; + +- timer@14 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <14>; ++ i2s2: audio-controller@4000b000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x4000b000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 39 0x400 0x01>, ++ <&dmamux1 40 0x400 0x01>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; +- +- timers16: timer@44007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44007000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM16_K>; +- clock-names = "int"; +- dmas = <&dmamux1 109 0x400 0x1>, +- <&dmamux1 110 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- timer@15 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <15>; ++ spi2: spi@4000b000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x4000b000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI2_K>; ++ resets = <&rcc SPI2_R>; ++ dmas = <&dmamux1 39 0x400 0x05>, ++ <&dmamux1 40 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- timers17: timer@44008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44008000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM17_K>; +- clock-names = "int"; +- dmas = <&dmamux1 111 0x400 0x1>, +- <&dmamux1 112 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; ++ i2s3: audio-controller@4000c000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x4000c000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 61 0x400 0x01>, ++ <&dmamux1 62 0x400 0x01>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- timer@16 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <16>; ++ spi3: spi@4000c000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x4000c000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI3_K>; ++ resets = <&rcc SPI3_R>; ++ dmas = <&dmamux1 61 0x400 0x05>, ++ <&dmamux1 62 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- spi5: spi@44009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44009000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI5_K>; +- resets = <&rcc SPI5_R>; +- dmas = <&dmamux1 85 0x400 0x05>, +- <&dmamux1 86 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai1: sai@4400a000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400a000 0x400>; +- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI1_R>; +- status = "disabled"; +- +- sai1a: audio-controller@4400a004 { ++ spdifrx: audio-controller@4000d000 { ++ compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; +- +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x20>; +- clocks = <&rcc SAI1_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 87 0x400 0x01>; ++ reg = <0x4000d000 0x400>; ++ clocks = <&rcc SPDIF_K>; ++ clock-names = "kclk"; ++ interrupts = ; ++ dmas = <&dmamux1 93 0x400 0x01>, ++ <&dmamux1 94 0x400 0x01>; ++ dma-names = "rx", "rx-ctrl"; ++ status = "disabled"; ++ }; ++ ++ usart2: serial@4000e000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x4000e000 0x400>; ++ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART2_K>; ++ wakeup-source; ++ dmas = <&dmamux1 43 0x400 0x15>, ++ <&dmamux1 44 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ usart3: serial@4000f000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x4000f000 0x400>; ++ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART3_K>; ++ wakeup-source; ++ dmas = <&dmamux1 45 0x400 0x15>, ++ <&dmamux1 46 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@40010000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40010000 0x400>; ++ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART4_K>; ++ wakeup-source; ++ dmas = <&dmamux1 63 0x400 0x15>, ++ <&dmamux1 64 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@40011000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40011000 0x400>; ++ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART5_K>; ++ wakeup-source; ++ dmas = <&dmamux1 65 0x400 0x15>, ++ <&dmamux1 66 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@40012000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40012000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C1_K>; ++ resets = <&rcc I2C1_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x1>; ++ wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +- sai1b: audio-controller@4400a024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI1_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 88 0x400 0x01>; ++ i2c2: i2c@40013000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40013000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C2_K>; ++ resets = <&rcc I2C2_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x2>; ++ wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; +- }; + +- sai2: sai@4400b000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400b000 0x400>; +- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI2_R>; +- status = "disabled"; ++ i2c3: i2c@40014000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40014000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C3_K>; ++ resets = <&rcc I2C3_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x4>; ++ wakeup-source; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; + +- sai2a: audio-controller@4400b004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x20>; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 89 0x400 0x01>; ++ i2c5: i2c@40015000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40015000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C5_K>; ++ resets = <&rcc I2C5_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x10>; ++ wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +- sai2b: audio-controller@4400b024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 90 0x400 0x01>; ++ cec: cec@40016000 { ++ compatible = "st,stm32-cec"; ++ reg = <0x40016000 0x400>; ++ interrupts = ; ++ clocks = <&rcc CEC_K>, <&rcc CEC>; ++ clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; +- }; + +- sai3: sai@4400c000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400c000 0x400>; +- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI3_R>; +- status = "disabled"; ++ dac: dac@40017000 { ++ compatible = "st,stm32h7-dac-core"; ++ reg = <0x40017000 0x400>; ++ clocks = <&rcc DAC12>; ++ clock-names = "pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; + +- sai3a: audio-controller@4400c004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x20>; +- clocks = <&rcc SAI3_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 113 0x400 0x01>; ++ dac1: dac@1 { ++ compatible = "st,stm32-dac"; ++ #io-channel-cells = <1>; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ dac2: dac@2 { ++ compatible = "st,stm32-dac"; ++ #io-channel-cells = <1>; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ }; ++ ++ uart7: serial@40018000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40018000 0x400>; ++ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART7_K>; ++ wakeup-source; ++ dmas = <&dmamux1 79 0x400 0x15>, ++ <&dmamux1 80 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- sai3b: audio-controller@4400c024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI3_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 114 0x400 0x01>; ++ uart8: serial@40019000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40019000 0x400>; ++ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART8_K>; ++ wakeup-source; ++ dmas = <&dmamux1 81 0x400 0x15>, ++ <&dmamux1 82 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- dfsdm: dfsdm@4400d000 { +- compatible = "st,stm32mp1-dfsdm"; +- reg = <0x4400d000 0x800>; +- clocks = <&rcc DFSDM_K>; +- clock-names = "dfsdm"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; ++ timers1: timer@44000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44000000 0x400>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "brk", "up", "trg-com", "cc"; ++ clocks = <&rcc TIM1_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 11 0x400 0x1>, ++ <&dmamux1 12 0x400 0x1>, ++ <&dmamux1 13 0x400 0x1>, ++ <&dmamux1 14 0x400 0x1>, ++ <&dmamux1 15 0x400 0x1>, ++ <&dmamux1 16 0x400 0x1>, ++ <&dmamux1 17 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", ++ "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- dfsdm0: filter@0 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <0>; +- interrupts = ; +- dmas = <&dmamux1 101 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; ++ timer@0 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; + +- dfsdm1: filter@1 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <1>; +- interrupts = ; +- dmas = <&dmamux1 102 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; ++ timers8: timer@44001000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44001000 0x400>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "brk", "up", "trg-com", "cc"; ++ clocks = <&rcc TIM8_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 47 0x400 0x1>, ++ <&dmamux1 48 0x400 0x1>, ++ <&dmamux1 49 0x400 0x1>, ++ <&dmamux1 50 0x400 0x1>, ++ <&dmamux1 51 0x400 0x1>, ++ <&dmamux1 52 0x400 0x1>, ++ <&dmamux1 53 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", ++ "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@7 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <7>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; + +- dfsdm2: filter@2 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <2>; +- interrupts = ; +- dmas = <&dmamux1 103 0x400 0x01>; +- dma-names = "rx"; ++ usart6: serial@44003000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x44003000 0x400>; ++ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART6_K>; ++ wakeup-source; ++ dmas = <&dmamux1 71 0x400 0x15>, ++ <&dmamux1 72 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- dfsdm3: filter@3 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <3>; +- interrupts = ; +- dmas = <&dmamux1 104 0x400 0x01>; +- dma-names = "rx"; ++ i2s1: audio-controller@44004000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x44004000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 37 0x400 0x01>, ++ <&dmamux1 38 0x400 0x01>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- dfsdm4: filter@4 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <4>; +- interrupts = ; +- dmas = <&dmamux1 91 0x400 0x01>; +- dma-names = "rx"; ++ spi1: spi@44004000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x44004000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI1_K>; ++ resets = <&rcc SPI1_R>; ++ dmas = <&dmamux1 37 0x400 0x05>, ++ <&dmamux1 38 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- dfsdm5: filter@5 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <5>; +- interrupts = ; +- dmas = <&dmamux1 92 0x400 0x01>; +- dma-names = "rx"; ++ spi4: spi@44005000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x44005000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI4_K>; ++ resets = <&rcc SPI4_R>; ++ dmas = <&dmamux1 83 0x400 0x05>, ++ <&dmamux1 84 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- dma1: dma-controller@48000000 { +- compatible = "st,stm32-dma"; +- reg = <0x48000000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&rcc DMA1>; +- resets = <&rcc DMA1_R>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- }; ++ timers15: timer@44006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44006000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM15_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 105 0x400 0x1>, ++ <&dmamux1 106 0x400 0x1>, ++ <&dmamux1 107 0x400 0x1>, ++ <&dmamux1 108 0x400 0x1>; ++ dma-names = "ch1", "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- dma2: dma-controller@48001000 { +- compatible = "st,stm32-dma"; +- reg = <0x48001000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&rcc DMA2>; +- resets = <&rcc DMA2_R>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- }; ++ timer@14 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <14>; ++ status = "disabled"; ++ }; ++ }; + +- dmamux1: dma-router@48002000 { +- compatible = "st,stm32h7-dmamux"; +- reg = <0x48002000 0x40>; +- #dma-cells = <3>; +- dma-requests = <128>; +- dma-masters = <&dma1 &dma2>; +- dma-channels = <16>; +- clocks = <&rcc DMAMUX>; +- resets = <&rcc DMAMUX_R>; +- }; ++ timers16: timer@44007000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44007000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM16_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 109 0x400 0x1>, ++ <&dmamux1 110 0x400 0x1>; ++ dma-names = "ch1", "up"; ++ status = "disabled"; + +- adc: adc@48003000 { +- compatible = "st,stm32mp1-adc-core"; +- reg = <0x48003000 0x400>; +- interrupts = , +- ; +- clocks = <&rcc ADC12>, <&rcc ADC12_K>; +- clock-names = "bus", "adc"; +- interrupt-controller; +- st,syscfg = <&syscfg>; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ timer@15 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <15>; ++ status = "disabled"; ++ }; ++ }; + +- adc1: adc@0 { +- compatible = "st,stm32mp1-adc"; +- #io-channel-cells = <1>; ++ timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x0>; +- interrupt-parent = <&adc>; +- interrupts = <0>; +- dmas = <&dmamux1 9 0x400 0x01>; +- dma-names = "rx"; ++ compatible = "st,stm32-timers"; ++ reg = <0x44008000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM17_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 111 0x400 0x1>, ++ <&dmamux1 112 0x400 0x1>; ++ dma-names = "ch1", "up"; + status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@16 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <16>; ++ status = "disabled"; ++ }; + }; + +- adc2: adc@100 { +- compatible = "st,stm32mp1-adc"; +- #io-channel-cells = <1>; ++ spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x100>; +- interrupt-parent = <&adc>; +- interrupts = <1>; +- dmas = <&dmamux1 10 0x400 0x01>; +- dma-names = "rx"; +- nvmem-cells = <&vrefint>; +- nvmem-cell-names = "vrefint"; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x44009000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI5_K>; ++ resets = <&rcc SPI5_R>; ++ dmas = <&dmamux1 85 0x400 0x05>, ++ <&dmamux1 86 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; +- channel@13 { +- reg = <13>; +- label = "vrefint"; ++ }; ++ ++ sai1: sai@4400a000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x4400a000 0x400>; ++ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI1_R>; ++ status = "disabled"; ++ ++ sai1a: audio-controller@4400a004 { ++ #sound-dai-cells = <0>; ++ ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x4 0x20>; ++ clocks = <&rcc SAI1_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 87 0x400 0x01>; ++ status = "disabled"; + }; +- channel@14 { +- reg = <14>; +- label = "vddcore"; ++ ++ sai1b: audio-controller@4400a024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI1_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 88 0x400 0x01>; ++ status = "disabled"; + }; + }; +- }; + +- sdmmc3: mmc@48004000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x48004000 0x400>; +- interrupts = ; +- clocks = <&rcc SDMMC3_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC3_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- usbotg_hs: usb-otg@49000000 { +- compatible = "st,stm32mp15-hsotg", "snps,dwc2"; +- reg = <0x49000000 0x10000>; +- clocks = <&rcc USBO_K>, <&usbphyc>; +- clock-names = "otg", "utmi"; +- resets = <&rcc USBO_R>; +- reset-names = "dwc2"; +- interrupts = ; +- g-rx-fifo-size = <512>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <256 16 16 16 16 16 16 16>; +- dr_mode = "otg"; +- otg-rev = <0x200>; +- usb33d-supply = <&usb33>; +- status = "disabled"; +- }; ++ sai2: sai@4400b000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x4400b000 0x400>; ++ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI2_R>; ++ status = "disabled"; + +- ipcc: mailbox@4c001000 { +- compatible = "st,stm32mp1-ipcc"; +- #mbox-cells = <1>; +- reg = <0x4c001000 0x400>; +- st,proc-id = <0>; +- interrupts-extended = +- <&exti 61 IRQ_TYPE_LEVEL_HIGH>, +- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "rx", "tx"; +- clocks = <&rcc IPCC>; +- wakeup-source; +- status = "disabled"; +- }; ++ sai2a: audio-controller@4400b004 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x4 0x20>; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 89 0x400 0x01>; ++ status = "disabled"; ++ }; + +- dcmi: dcmi@4c006000 { +- compatible = "st,stm32-dcmi"; +- reg = <0x4c006000 0x400>; +- interrupts = ; +- resets = <&rcc CAMITF_R>; +- clocks = <&rcc DCMI>; +- clock-names = "mclk"; +- dmas = <&dmamux1 75 0x400 0x01>; +- dma-names = "tx"; +- status = "disabled"; +- }; ++ sai2b: audio-controller@4400b024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 90 0x400 0x01>; ++ status = "disabled"; ++ }; ++ }; + +- rcc: rcc@50000000 { +- compatible = "st,stm32mp1-rcc", "syscon"; +- reg = <0x50000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; ++ sai3: sai@4400c000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x4400c000 0x400>; ++ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI3_R>; ++ status = "disabled"; + +- pwr_regulators: pwr@50001000 { +- compatible = "st,stm32mp1,pwr-reg"; +- reg = <0x50001000 0x10>; ++ sai3a: audio-controller@4400c004 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x04 0x20>; ++ clocks = <&rcc SAI3_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 113 0x400 0x01>; ++ status = "disabled"; ++ }; + +- reg11: reg11 { +- regulator-name = "reg11"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; ++ sai3b: audio-controller@4400c024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI3_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 114 0x400 0x01>; ++ status = "disabled"; ++ }; + }; + +- reg18: reg18 { +- regulator-name = "reg18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; ++ dfsdm: dfsdm@4400d000 { ++ compatible = "st,stm32mp1-dfsdm"; ++ reg = <0x4400d000 0x800>; ++ clocks = <&rcc DFSDM_K>; ++ clock-names = "dfsdm"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; + +- usb33: usb33 { +- regulator-name = "usb33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; ++ dfsdm0: filter@0 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <0>; ++ interrupts = ; ++ dmas = <&dmamux1 101 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- pwr_mcu: pwr_mcu@50001014 { +- compatible = "st,stm32mp151-pwr-mcu", "syscon"; +- reg = <0x50001014 0x4>; +- }; ++ dfsdm1: filter@1 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <1>; ++ interrupts = ; ++ dmas = <&dmamux1 102 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- exti: interrupt-controller@5000d000 { +- compatible = "st,stm32mp1-exti", "syscon"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000d000 0x400>; +- }; ++ dfsdm2: filter@2 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <2>; ++ interrupts = ; ++ dmas = <&dmamux1 103 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- syscfg: syscon@50020000 { +- compatible = "st,stm32mp157-syscfg", "syscon"; +- reg = <0x50020000 0x400>; +- clocks = <&rcc SYSCFG>; +- }; ++ dfsdm3: filter@3 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <3>; ++ interrupts = ; ++ dmas = <&dmamux1 104 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- lptimer2: timer@50021000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50021000 0x400>; +- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM2_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; ++ dfsdm4: filter@4 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <4>; ++ interrupts = ; ++ dmas = <&dmamux1 91 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; ++ dfsdm5: filter@5 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <5>; ++ interrupts = ; ++ dmas = <&dmamux1 92 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + }; + +- trigger@1 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <1>; ++ dma1: dma-controller@48000000 { ++ compatible = "st,stm32-dma"; ++ reg = <0x48000000 0x400>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ clocks = <&rcc DMA1>; ++ resets = <&rcc DMA1_R>; ++ #dma-cells = <4>; ++ st,mem2mem; ++ dma-requests = <8>; ++ }; ++ ++ dma2: dma-controller@48001000 { ++ compatible = "st,stm32-dma"; ++ reg = <0x48001000 0x400>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ clocks = <&rcc DMA2>; ++ resets = <&rcc DMA2_R>; ++ #dma-cells = <4>; ++ st,mem2mem; ++ dma-requests = <8>; ++ }; ++ ++ dmamux1: dma-router@48002000 { ++ compatible = "st,stm32h7-dmamux"; ++ reg = <0x48002000 0x40>; ++ #dma-cells = <3>; ++ dma-requests = <128>; ++ dma-masters = <&dma1 &dma2>; ++ dma-channels = <16>; ++ clocks = <&rcc DMAMUX>; ++ resets = <&rcc DMAMUX_R>; ++ }; ++ ++ adc: adc@48003000 { ++ compatible = "st,stm32mp1-adc-core"; ++ reg = <0x48003000 0x400>; ++ interrupts = , ++ ; ++ clocks = <&rcc ADC12>, <&rcc ADC12_K>; ++ clock-names = "bus", "adc"; ++ interrupt-controller; ++ st,syscfg = <&syscfg>; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "disabled"; +- }; + +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- }; ++ adc1: adc@0 { ++ compatible = "st,stm32mp1-adc"; ++ #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; ++ interrupt-parent = <&adc>; ++ interrupts = <0>; ++ dmas = <&dmamux1 9 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- lptimer3: timer@50022000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50022000 0x400>; +- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM3_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; ++ adc2: adc@100 { ++ compatible = "st,stm32mp1-adc"; ++ #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x100>; ++ interrupt-parent = <&adc>; ++ interrupts = <1>; ++ dmas = <&dmamux1 10 0x400 0x01>; ++ dma-names = "rx"; ++ nvmem-cells = <&vrefint>; ++ nvmem-cell-names = "vrefint"; ++ status = "disabled"; ++ channel@13 { ++ reg = <13>; ++ label = "vrefint"; ++ }; ++ channel@14 { ++ reg = <14>; ++ label = "vddcore"; ++ }; ++ }; ++ }; + +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; ++ sdmmc3: mmc@48004000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x00253180>; ++ reg = <0x48004000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SDMMC3_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC3_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <120000000>; + status = "disabled"; + }; + +- trigger@2 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <2>; ++ usbotg_hs: usb-otg@49000000 { ++ compatible = "st,stm32mp15-hsotg", "snps,dwc2"; ++ reg = <0x49000000 0x10000>; ++ clocks = <&rcc USBO_K>, <&usbphyc>; ++ clock-names = "otg", "utmi"; ++ resets = <&rcc USBO_R>; ++ reset-names = "dwc2"; ++ interrupts = ; ++ g-rx-fifo-size = <512>; ++ g-np-tx-fifo-size = <32>; ++ g-tx-fifo-size = <256 16 16 16 16 16 16 16>; ++ dr_mode = "otg"; ++ otg-rev = <0x200>; ++ usb33d-supply = <&usb33>; + status = "disabled"; + }; +- }; + +- lptimer4: timer@50023000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x50023000 0x400>; +- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM4_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; ++ dcmi: dcmi@4c006000 { ++ compatible = "st,stm32-dcmi"; ++ reg = <0x4c006000 0x400>; ++ interrupts = ; ++ resets = <&rcc CAMITF_R>; ++ clocks = <&rcc DCMI>; ++ clock-names = "mclk"; ++ dmas = <&dmamux1 75 0x400 0x01>; ++ dma-names = "tx"; + status = "disabled"; + }; +- }; + +- lptimer5: timer@50024000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x50024000 0x400>; +- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM5_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; ++ lptimer2: timer@50021000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50021000 0x400>; ++ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM2_K>; ++ clock-names = "mux"; ++ wakeup-source; + status = "disabled"; +- }; +- }; + +- vrefbuf: vrefbuf@50025000 { +- compatible = "st,stm32-vrefbuf"; +- reg = <0x50025000 0x8>; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2500000>; +- clocks = <&rcc VREF>; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- sai4: sai@50027000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50027000 0x400>; +- reg = <0x50027000 0x4>, <0x500273f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI4_R>; +- status = "disabled"; ++ trigger@1 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <1>; ++ status = "disabled"; ++ }; + +- sai4a: audio-controller@50027004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x20>; +- clocks = <&rcc SAI4_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 99 0x400 0x01>; +- status = "disabled"; ++ counter { ++ compatible = "st,stm32-lptimer-counter"; ++ status = "disabled"; ++ }; + }; + +- sai4b: audio-controller@50027024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI4_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 100 0x400 0x01>; ++ lptimer3: timer@50022000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50022000 0x400>; ++ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM3_K>; ++ clock-names = "mux"; ++ wakeup-source; + status = "disabled"; +- }; +- }; +- +- dts: thermal@50028000 { +- compatible = "st,stm32-thermal"; +- reg = <0x50028000 0x100>; +- interrupts = ; +- clocks = <&rcc TMPSENS>; +- clock-names = "pclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- hash1: hash@54002000 { +- compatible = "st,stm32f756-hash"; +- reg = <0x54002000 0x400>; +- interrupts = ; +- clocks = <&rcc HASH1>; +- resets = <&rcc HASH1_R>; +- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; +- dma-names = "in"; +- dma-maxburst = <2>; +- status = "disabled"; +- }; +- +- rng1: rng@54003000 { +- compatible = "st,stm32-rng"; +- reg = <0x54003000 0x400>; +- clocks = <&rcc RNG1_K>; +- resets = <&rcc RNG1_R>; +- status = "disabled"; +- }; +- +- mdma1: dma-controller@58000000 { +- compatible = "st,stm32h7-mdma"; +- reg = <0x58000000 0x1000>; +- interrupts = ; +- clocks = <&rcc MDMA>; +- resets = <&rcc MDMA_R>; +- #dma-cells = <5>; +- dma-channels = <32>; +- dma-requests = <48>; +- }; + +- fmc: memory-controller@58002000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "st,stm32mp1-fmc2-ebi"; +- reg = <0x58002000 0x1000>; +- clocks = <&rcc FMC_K>; +- resets = <&rcc FMC_R>; +- status = "disabled"; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ +- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ +- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ +- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ +- <4 0 0x80000000 0x10000000>; /* NAND */ +- +- nand-controller@4,0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32mp1-fmc2-nfc"; +- reg = <4 0x00000000 0x1000>, +- <4 0x08010000 0x1000>, +- <4 0x08020000 0x1000>, +- <4 0x01000000 0x1000>, +- <4 0x09010000 0x1000>, +- <4 0x09020000 0x1000>; +- interrupts = ; +- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, +- <&mdma1 20 0x2 0x12000a08 0x0 0x0>, +- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; +- dma-names = "tx", "rx", "ecc"; +- status = "disabled"; ++ trigger@2 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <2>; ++ status = "disabled"; ++ }; + }; +- }; +- +- qspi: spi@58003000 { +- compatible = "st,stm32f469-qspi"; +- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; +- reg-names = "qspi", "qspi_mm"; +- interrupts = ; +- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, +- <&mdma1 22 0x2 0x10100008 0x0 0x0>; +- dma-names = "tx", "rx"; +- clocks = <&rcc QSPI_K>; +- resets = <&rcc QSPI_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; + +- sdmmc1: mmc@58005000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x58005000 0x1000>; +- interrupts = ; +- clocks = <&rcc SDMMC1_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC1_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@58007000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x58007000 0x1000>; +- interrupts = ; +- clocks = <&rcc SDMMC2_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC2_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- crc1: crc@58009000 { +- compatible = "st,stm32f7-crc"; +- reg = <0x58009000 0x400>; +- clocks = <&rcc CRC1>; +- status = "disabled"; +- }; +- +- ethernet0: ethernet@5800a000 { +- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; +- reg = <0x5800a000 0x2000>; +- reg-names = "stmmaceth"; +- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; +- clock-names = "stmmaceth", +- "mac-clk-tx", +- "mac-clk-rx", +- "eth-ck", +- "ptp_ref", +- "ethstp"; +- clocks = <&rcc ETHMAC>, +- <&rcc ETHTX>, +- <&rcc ETHRX>, +- <&rcc ETHCK_K>, +- <&rcc ETHPTP_K>, +- <&rcc ETHSTP>; +- st,syscon = <&syscfg 0x4>; +- snps,mixed-burst; +- snps,pbl = <2>; +- snps,en-tx-lpi-clockgating; +- snps,axi-config = <&stmmac_axi_config_0>; +- snps,tso; +- status = "disabled"; ++ lptimer4: timer@50023000 { ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50023000 0x400>; ++ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM4_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; + +- stmmac_axi_config_0: stmmac-axi-config { +- snps,wr_osr_lmt = <0x7>; +- snps,rd_osr_lmt = <0x7>; +- snps,blen = <0 0 0 0 16 8 4>; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + }; +- }; + +- usbh_ohci: usb@5800c000 { +- compatible = "generic-ohci"; +- reg = <0x5800c000 0x1000>; +- clocks = <&usbphyc>, <&rcc USBH>; +- resets = <&rcc USBH_R>; +- interrupts = ; +- status = "disabled"; +- }; ++ lptimer5: timer@50024000 { ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50024000 0x400>; ++ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM5_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; + +- usbh_ehci: usb@5800d000 { +- compatible = "generic-ehci"; +- reg = <0x5800d000 0x1000>; +- clocks = <&usbphyc>, <&rcc USBH>; +- resets = <&rcc USBH_R>; +- interrupts = ; +- companion = <&usbh_ohci>; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ }; + +- ltdc: display-controller@5a001000 { +- compatible = "st,stm32-ltdc"; +- reg = <0x5a001000 0x400>; +- interrupts = , +- ; +- clocks = <&rcc LTDC_PX>; +- clock-names = "lcd"; +- resets = <&rcc LTDC_R>; +- status = "disabled"; +- }; ++ vrefbuf: vrefbuf@50025000 { ++ compatible = "st,stm32-vrefbuf"; ++ reg = <0x50025000 0x8>; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <2500000>; ++ clocks = <&rcc VREF>; ++ status = "disabled"; ++ }; + +- iwdg2: watchdog@5a002000 { +- compatible = "st,stm32mp1-iwdg"; +- reg = <0x5a002000 0x400>; +- clocks = <&rcc IWDG2>, <&rcc CK_LSI>; +- clock-names = "pclk", "lsi"; +- status = "disabled"; +- }; ++ sai4: sai@50027000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x50027000 0x400>; ++ reg = <0x50027000 0x4>, <0x500273f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI4_R>; ++ status = "disabled"; + +- usbphyc: usbphyc@5a006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "st,stm32mp1-usbphyc"; +- reg = <0x5a006000 0x1000>; +- clocks = <&rcc USBPHY_K>; +- resets = <&rcc USBPHY_R>; +- vdda1v1-supply = <®11>; +- vdda1v8-supply = <®18>; +- status = "disabled"; ++ sai4a: audio-controller@50027004 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x04 0x20>; ++ clocks = <&rcc SAI4_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 99 0x400 0x01>; ++ status = "disabled"; ++ }; + +- usbphyc_port0: usb-phy@0 { +- #phy-cells = <0>; +- reg = <0>; ++ sai4b: audio-controller@50027024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI4_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 100 0x400 0x01>; ++ status = "disabled"; ++ }; + }; + +- usbphyc_port1: usb-phy@1 { +- #phy-cells = <1>; +- reg = <1>; ++ hash1: hash@54002000 { ++ compatible = "st,stm32f756-hash"; ++ reg = <0x54002000 0x400>; ++ interrupts = ; ++ clocks = <&rcc HASH1>; ++ resets = <&rcc HASH1_R>; ++ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; ++ dma-names = "in"; ++ dma-maxburst = <2>; ++ status = "disabled"; + }; +- }; +- +- usart1: serial@5c000000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x5c000000 0x400>; +- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART1_K>; +- wakeup-source; +- status = "disabled"; +- }; + +- spi6: spi@5c001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x5c001000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI6_K>; +- resets = <&rcc SPI6_R>; +- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, +- <&mdma1 35 0x0 0x40002 0x0 0x0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ rng1: rng@54003000 { ++ compatible = "st,stm32-rng"; ++ reg = <0x54003000 0x400>; ++ clocks = <&rcc RNG1_K>; ++ resets = <&rcc RNG1_R>; ++ status = "disabled"; ++ }; + +- i2c4: i2c@5c002000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x5c002000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C4_K>; +- resets = <&rcc I2C4_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x8>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ fmc: memory-controller@58002000 { ++ #address-cells = <2>; ++ #size-cells = <1>; ++ compatible = "st,stm32mp1-fmc2-ebi"; ++ reg = <0x58002000 0x1000>; ++ clocks = <&rcc FMC_K>; ++ resets = <&rcc FMC_R>; ++ status = "disabled"; ++ ++ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ ++ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ ++ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ ++ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ ++ <4 0 0x80000000 0x10000000>; /* NAND */ ++ ++ nand-controller@4,0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32mp1-fmc2-nfc"; ++ reg = <4 0x00000000 0x1000>, ++ <4 0x08010000 0x1000>, ++ <4 0x08020000 0x1000>, ++ <4 0x01000000 0x1000>, ++ <4 0x09010000 0x1000>, ++ <4 0x09020000 0x1000>; ++ interrupts = ; ++ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, ++ <&mdma1 20 0x2 0x12000a08 0x0 0x0>, ++ <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; ++ dma-names = "tx", "rx", "ecc"; ++ status = "disabled"; ++ }; ++ }; + +- rtc: rtc@5c004000 { +- compatible = "st,stm32mp1-rtc"; +- reg = <0x5c004000 0x400>; +- clocks = <&rcc RTCAPB>, <&rcc RTC>; +- clock-names = "pclk", "rtc_ck"; +- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; ++ qspi: spi@58003000 { ++ compatible = "st,stm32f469-qspi"; ++ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; ++ reg-names = "qspi", "qspi_mm"; ++ interrupts = ; ++ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, ++ <&mdma1 22 0x2 0x10100008 0x0 0x0>; ++ dma-names = "tx", "rx"; ++ clocks = <&rcc QSPI_K>; ++ resets = <&rcc QSPI_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; + +- bsec: efuse@5c005000 { +- compatible = "st,stm32mp15-bsec"; +- reg = <0x5c005000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- part_number_otp: part-number-otp@4 { +- reg = <0x4 0x1>; ++ ethernet0: ethernet@5800a000 { ++ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; ++ reg = <0x5800a000 0x2000>; ++ reg-names = "stmmaceth"; ++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq"; ++ clock-names = "stmmaceth", ++ "mac-clk-tx", ++ "mac-clk-rx", ++ "eth-ck", ++ "ptp_ref", ++ "ethstp"; ++ clocks = <&rcc ETHMAC>, ++ <&rcc ETHTX>, ++ <&rcc ETHRX>, ++ <&rcc ETHCK_K>, ++ <&rcc ETHPTP_K>, ++ <&rcc ETHSTP>; ++ st,syscon = <&syscfg 0x4>; ++ snps,mixed-burst; ++ snps,pbl = <2>; ++ snps,en-tx-lpi-clockgating; ++ snps,axi-config = <&stmmac_axi_config_0>; ++ snps,tso; ++ status = "disabled"; ++ ++ stmmac_axi_config_0: stmmac-axi-config { ++ snps,wr_osr_lmt = <0x7>; ++ snps,rd_osr_lmt = <0x7>; ++ snps,blen = <0 0 0 0 16 8 4>; ++ }; + }; +- vrefint: vrefin-cal@52 { +- reg = <0x52 0x2>; ++ ++ usart1: serial@5c000000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x5c000000 0x400>; ++ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART1_K>; ++ wakeup-source; ++ status = "disabled"; + }; +- ts_cal1: calib@5c { +- reg = <0x5c 0x2>; ++ ++ spi6: spi@5c001000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x5c001000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI6_K>; ++ resets = <&rcc SPI6_R>; ++ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, ++ <&mdma1 35 0x0 0x40002 0x0 0x0>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; + }; +- ts_cal2: calib@5e { +- reg = <0x5e 0x2>; ++ ++ i2c4: i2c@5c002000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x5c002000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C4_K>; ++ resets = <&rcc I2C4_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x8>; ++ wakeup-source; ++ i2c-analog-filter; ++ status = "disabled"; + }; +- }; + +- i2c6: i2c@5c009000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x5c009000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C6_K>; +- resets = <&rcc I2C6_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x20>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; ++ i2c6: i2c@5c009000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x5c009000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C6_K>; ++ resets = <&rcc I2C6_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x20>; ++ wakeup-source; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; + }; + + tamp: tamp@5c00a000 { +--- a/arch/arm/boot/dts/st/stm32mp153.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp153.dtsi +@@ -28,32 +28,32 @@ + , + ; + }; ++}; + +- soc { +- m_can1: can@4400e000 { +- compatible = "bosch,m_can"; +- reg = <0x4400e000 0x400>, <0x44011000 0x1400>; +- reg-names = "m_can", "message_ram"; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; +- status = "disabled"; +- }; ++&etzpc { ++ m_can1: can@4400e000 { ++ compatible = "bosch,m_can"; ++ reg = <0x4400e000 0x400>, <0x44011000 0x1400>; ++ reg-names = "m_can", "message_ram"; ++ interrupts = , ++ ; ++ interrupt-names = "int0", "int1"; ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ clock-names = "hclk", "cclk"; ++ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; ++ status = "disabled"; ++ }; + +- m_can2: can@4400f000 { +- compatible = "bosch,m_can"; +- reg = <0x4400f000 0x400>, <0x44011000 0x2800>; +- reg-names = "m_can", "message_ram"; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; +- status = "disabled"; +- }; ++ m_can2: can@4400f000 { ++ compatible = "bosch,m_can"; ++ reg = <0x4400f000 0x400>, <0x44011000 0x2800>; ++ reg-names = "m_can", "message_ram"; ++ interrupts = , ++ ; ++ interrupt-names = "int0", "int1"; ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ clock-names = "hclk", "cclk"; ++ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; ++ status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi +@@ -4,15 +4,13 @@ + * Author: Alexandre Torgue for STMicroelectronics. + */ + +-/ { +- soc { +- cryp1: cryp@54001000 { +- compatible = "st,stm32mp1-cryp"; +- reg = <0x54001000 0x400>; +- interrupts = ; +- clocks = <&rcc CRYP1>; +- resets = <&rcc CRYP1_R>; +- status = "disabled"; +- }; ++&etzpc { ++ cryp1: cryp@54001000 { ++ compatible = "st,stm32mp1-cryp"; ++ reg = <0x54001000 0x400>; ++ interrupts = ; ++ clocks = <&rcc CRYP1>; ++ resets = <&rcc CRYP1_R>; ++ status = "disabled"; + }; + }; diff --git a/target/linux/stm32/patches-6.6/041-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch b/target/linux/stm32/patches-6.6/041-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch new file mode 100644 index 00000000000..9e28274b7a4 --- /dev/null +++ b/target/linux/stm32/patches-6.6/041-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch @@ -0,0 +1,566 @@ +From 91ddf8509d0308e297f1876a024645cc3478e358 Mon Sep 17 00:00:00 2001 +From: Gatien Chevallier +Date: Fri, 5 Jan 2024 14:04:02 +0100 +Subject: [PATCH] ARM: dts: stm32: put ETZPC as an access controller for + STM32MP15x boards + +Reference ETZPC as an access-control-provider. + +For more information on which peripheral is securable or supports MCU +isolation, please read the STM32MP15 reference manual + +Signed-off-by: Gatien Chevallier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp151.dtsi | 66 ++++++++++++++++++++++++++- + arch/arm/boot/dts/st/stm32mp153.dtsi | 2 + + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 + + 3 files changed, 68 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/st/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi +@@ -331,10 +331,11 @@ + }; + + etzpc: bus@5c007000 { +- compatible = "simple-bus"; ++ compatible = "st,stm32-etzpc", "simple-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; ++ #access-controller-cells = <1>; + ranges; + + timers2: timer@40000000 { +@@ -352,6 +353,7 @@ + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; ++ access-controllers = <&etzpc 16>; + status = "disabled"; + + pwm { +@@ -388,6 +390,7 @@ + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ access-controllers = <&etzpc 17>; + status = "disabled"; + + pwm { +@@ -422,6 +425,7 @@ + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; ++ access-controllers = <&etzpc 18>; + status = "disabled"; + + pwm { +@@ -458,6 +462,7 @@ + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ access-controllers = <&etzpc 19>; + status = "disabled"; + + pwm { +@@ -489,6 +494,7 @@ + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; ++ access-controllers = <&etzpc 20>; + status = "disabled"; + + timer@5 { +@@ -509,6 +515,7 @@ + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; ++ access-controllers = <&etzpc 21>; + status = "disabled"; + + timer@6 { +@@ -527,6 +534,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 22>; + status = "disabled"; + + pwm { +@@ -551,6 +559,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 23>; + status = "disabled"; + + pwm { +@@ -575,6 +584,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 24>; + status = "disabled"; + + pwm { +@@ -599,6 +609,7 @@ + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 25>; + status = "disabled"; + + pwm { +@@ -627,6 +638,7 @@ + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 27>; + status = "disabled"; + }; + +@@ -641,6 +653,7 @@ + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 27>; + status = "disabled"; + }; + +@@ -652,6 +665,7 @@ + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 28>; + status = "disabled"; + }; + +@@ -666,6 +680,7 @@ + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 28>; + status = "disabled"; + }; + +@@ -679,6 +694,7 @@ + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; ++ access-controllers = <&etzpc 29>; + status = "disabled"; + }; + +@@ -691,6 +707,7 @@ + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 30>; + status = "disabled"; + }; + +@@ -703,6 +720,7 @@ + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 31>; + status = "disabled"; + }; + +@@ -715,6 +733,7 @@ + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 32>; + status = "disabled"; + }; + +@@ -727,6 +746,7 @@ + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 33>; + status = "disabled"; + }; + +@@ -743,6 +763,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 34>; + status = "disabled"; + }; + +@@ -759,6 +780,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 35>; + status = "disabled"; + }; + +@@ -775,6 +797,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 36>; + status = "disabled"; + }; + +@@ -791,6 +814,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 37>; + status = "disabled"; + }; + +@@ -800,6 +824,7 @@ + interrupts = ; + clocks = <&rcc CEC_K>, <&rcc CEC>; + clock-names = "cec", "hdmi-cec"; ++ access-controllers = <&etzpc 38>; + status = "disabled"; + }; + +@@ -810,6 +835,7 @@ + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 39>; + status = "disabled"; + + dac1: dac@1 { +@@ -836,6 +862,7 @@ + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 40>; + status = "disabled"; + }; + +@@ -848,6 +875,7 @@ + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 41>; + status = "disabled"; + }; + +@@ -872,6 +900,7 @@ + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; ++ access-controllers = <&etzpc 48>; + status = "disabled"; + + pwm { +@@ -913,6 +942,7 @@ + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; ++ access-controllers = <&etzpc 49>; + status = "disabled"; + + pwm { +@@ -942,6 +972,7 @@ + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 51>; + status = "disabled"; + }; + +@@ -953,6 +984,7 @@ + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 52>; + status = "disabled"; + }; + +@@ -967,6 +999,7 @@ + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 52>; + status = "disabled"; + }; + +@@ -981,6 +1014,7 @@ + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 53>; + status = "disabled"; + }; + +@@ -998,6 +1032,7 @@ + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; ++ access-controllers = <&etzpc 54>; + status = "disabled"; + + pwm { +@@ -1025,6 +1060,7 @@ + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; ++ access-controllers = <&etzpc 55>; + status = "disabled"; + + pwm { +@@ -1051,6 +1087,7 @@ + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; ++ access-controllers = <&etzpc 56>; + status = "disabled"; + + pwm { +@@ -1077,6 +1114,7 @@ + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 57>; + status = "disabled"; + }; + +@@ -1088,6 +1126,7 @@ + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = ; + resets = <&rcc SAI1_R>; ++ access-controllers = <&etzpc 58>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { +@@ -1120,6 +1159,7 @@ + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = ; + resets = <&rcc SAI2_R>; ++ access-controllers = <&etzpc 59>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { +@@ -1151,6 +1191,7 @@ + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = ; + resets = <&rcc SAI3_R>; ++ access-controllers = <&etzpc 60>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { +@@ -1181,6 +1222,7 @@ + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 61>; + status = "disabled"; + + dfsdm0: filter@0 { +@@ -1260,6 +1302,7 @@ + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; ++ access-controllers = <&etzpc 88>; + }; + + dma2: dma-controller@48001000 { +@@ -1278,6 +1321,7 @@ + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; ++ access-controllers = <&etzpc 89>; + }; + + dmamux1: dma-router@48002000 { +@@ -1289,6 +1333,7 @@ + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; ++ access-controllers = <&etzpc 90>; + }; + + adc: adc@48003000 { +@@ -1303,6 +1348,7 @@ + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 72>; + status = "disabled"; + + adc1: adc@0 { +@@ -1353,6 +1399,7 @@ + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; ++ access-controllers = <&etzpc 86>; + status = "disabled"; + }; + +@@ -1370,6 +1417,7 @@ + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; ++ access-controllers = <&etzpc 85>; + status = "disabled"; + }; + +@@ -1382,6 +1430,7 @@ + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x01>; + dma-names = "tx"; ++ access-controllers = <&etzpc 70>; + status = "disabled"; + }; + +@@ -1394,6 +1443,7 @@ + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 64>; + status = "disabled"; + + pwm { +@@ -1423,6 +1473,7 @@ + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 65>; + status = "disabled"; + + pwm { +@@ -1445,6 +1496,7 @@ + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 66>; + status = "disabled"; + + pwm { +@@ -1461,6 +1513,7 @@ + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 67>; + status = "disabled"; + + pwm { +@@ -1476,6 +1529,7 @@ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; ++ access-controllers = <&etzpc 69>; + status = "disabled"; + }; + +@@ -1487,6 +1541,7 @@ + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = ; + resets = <&rcc SAI4_R>; ++ access-controllers = <&etzpc 68>; + status = "disabled"; + + sai4a: audio-controller@50027004 { +@@ -1519,6 +1574,7 @@ + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; ++ access-controllers = <&etzpc 8>; + status = "disabled"; + }; + +@@ -1527,6 +1583,7 @@ + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; ++ access-controllers = <&etzpc 7>; + status = "disabled"; + }; + +@@ -1537,6 +1594,7 @@ + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; ++ access-controllers = <&etzpc 91>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ +@@ -1576,6 +1634,7 @@ + resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 92>; + status = "disabled"; + }; + +@@ -1603,6 +1662,7 @@ + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; ++ access-controllers = <&etzpc 94>; + status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { +@@ -1618,6 +1678,7 @@ + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + wakeup-source; ++ access-controllers = <&etzpc 3>; + status = "disabled"; + }; + +@@ -1631,6 +1692,7 @@ + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0>; ++ access-controllers = <&etzpc 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; +@@ -1648,6 +1710,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 5>; + status = "disabled"; + }; + +@@ -1664,6 +1727,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 12>; + status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp153.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp153.dtsi +@@ -41,6 +41,7 @@ + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; ++ access-controllers = <&etzpc 62>; + status = "disabled"; + }; + +@@ -54,6 +55,7 @@ + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; ++ access-controllers = <&etzpc 62>; + status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi +@@ -11,6 +11,7 @@ + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; ++ access-controllers = <&etzpc 9>; + status = "disabled"; + }; + }; diff --git a/target/linux/stm32/patches-6.6/020-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch b/target/linux/stm32/patches-6.6/050-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch similarity index 100% rename from target/linux/stm32/patches-6.6/020-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch rename to target/linux/stm32/patches-6.6/050-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch diff --git a/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch b/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch index 57d2a26c1af..b3758a54d90 100644 --- a/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch +++ b/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch @@ -29,8 +29,8 @@ Signed-off-by: Christophe Roullier u32 speed; const struct stm32_ops *ops; struct device *dev; -@@ -374,6 +376,16 @@ static int stm32_dwmac_parse_data(struct - dev_dbg(dev, "Warning sysconfig register mask not set\n"); +@@ -379,6 +381,16 @@ static int stm32_dwmac_parse_data(struct + } } + dwmac->regulator = devm_regulator_get_optional(dev, "phy"); @@ -46,7 +46,7 @@ Signed-off-by: Christophe Roullier return err; } -@@ -439,6 +451,28 @@ static int stm32mp1_parse_data(struct st +@@ -444,6 +456,28 @@ static int stm32mp1_parse_data(struct st return err; } @@ -75,7 +75,7 @@ Signed-off-by: Christophe Roullier static int stm32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; -@@ -480,12 +514,18 @@ static int stm32_dwmac_probe(struct plat +@@ -485,12 +519,18 @@ static int stm32_dwmac_probe(struct plat if (ret) return ret; @@ -95,7 +95,7 @@ Signed-off-by: Christophe Roullier err_clk_disable: stm32_dwmac_clk_disable(dwmac, false); -@@ -506,6 +546,8 @@ static void stm32_dwmac_remove(struct pl +@@ -511,6 +551,8 @@ static void stm32_dwmac_remove(struct pl dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); } diff --git a/target/linux/stm32/patches-6.6/910-ARM-dts-stm32-add-missing-eth_wake_irq-interrupt-for.patch b/target/linux/stm32/patches-6.6/910-ARM-dts-stm32-add-missing-eth_wake_irq-interrupt-for.patch new file mode 100644 index 00000000000..cb1bc91ce8e --- /dev/null +++ b/target/linux/stm32/patches-6.6/910-ARM-dts-stm32-add-missing-eth_wake_irq-interrupt-for.patch @@ -0,0 +1,26 @@ +From 6e10eb83e20e3a31bef8580bb4197240b0a28888 Mon Sep 17 00:00:00 2001 +From: Thomas Richard +Date: Thu, 17 Oct 2024 19:51:32 +0200 +Subject: [PATCH] ARM: dts: stm32: add missing eth_wake_irq interrupt for the + ethernet on STM32MP157 + +Signed-off-by: Thomas Richard +--- + arch/arm/boot/dts/st/stm32mp151.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/st/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi +@@ -1642,8 +1642,10 @@ + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; +- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; ++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, ++ <&exti 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", ++ "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", diff --git a/target/linux/stm32/stm32mp1/config-6.6 b/target/linux/stm32/stm32mp1/config-6.6 index 31ead21ce73..b81f7613946 100644 --- a/target/linux/stm32/stm32mp1/config-6.6 +++ b/target/linux/stm32/stm32mp1/config-6.6 @@ -90,6 +90,7 @@ CONFIG_CMDLINE_PARTITION=y CONFIG_COMMON_CLK=y CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_STM32MP135=y +CONFIG_COMMON_CLK_STM32MP157=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 CONFIG_COMPAT_32BIT_TIME=y CONFIG_CONSOLE_TRANSLATIONS=y @@ -237,7 +238,7 @@ CONFIG_HOTPLUG_CPU=y CONFIG_HW_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_OPTEE=y -# CONFIG_HW_RANDOM_STM32 is not set +CONFIG_HW_RANDOM_STM32=y CONFIG_HZ_FIXED=0 CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y @@ -255,6 +256,7 @@ CONFIG_I2C_SMBUS=y # CONFIG_I2C_STM32F4 is not set CONFIG_I2C_STM32F7=y CONFIG_INPUT=y +# CONFIG_INPUT_STPMIC1_ONKEY is not set # CONFIG_IOMMUFD is not set # CONFIG_IOMMU_DEBUGFS is not set CONFIG_IOMMU_IO_PGTABLE=y @@ -285,7 +287,7 @@ CONFIG_LOG_BUF_SHIFT=16 # CONFIG_LRU_GEN is not set CONFIG_LZO_DECOMPRESS=y CONFIG_MACH_STM32MP13=y -# CONFIG_MACH_STM32MP157 is not set +CONFIG_MACH_STM32MP157=y CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_SERIAL=y CONFIG_MDIO_BITBANG=y @@ -295,8 +297,10 @@ CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_GPIO is not set CONFIG_MEMORY=y CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_CORE=y # CONFIG_MFD_STM32_LPTIMER is not set # CONFIG_MFD_STM32_TIMERS is not set +CONFIG_MFD_STPMIC1=y CONFIG_MFD_SYSCON=y CONFIG_MIGHT_HAVE_CACHE_L2X0=y CONFIG_MIGRATION=y @@ -355,6 +359,7 @@ CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_MCP23S08_I2C=y CONFIG_PINCTRL_STM32=y CONFIG_PINCTRL_STM32MP135=y +CONFIG_PINCTRL_STM32MP157=y # CONFIG_PL353_SMC is not set CONFIG_PM=y CONFIG_PM_CLK=y @@ -383,16 +388,19 @@ CONFIG_RANDSTRUCT_NONE=y CONFIG_RAS=y CONFIG_RATIONAL=y # CONFIG_RAVE_SP_CORE is not set +CONFIG_REALTEK_PHY=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y CONFIG_REGMAP_MMIO=y CONFIG_REGULATOR=y CONFIG_REGULATOR_ARM_SCMI=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_STM32_BOOSTER is not set -# CONFIG_REGULATOR_STM32_PWR is not set +CONFIG_REGULATOR_STM32_PWR=y # CONFIG_REGULATOR_STM32_VREFBUF is not set +CONFIG_REGULATOR_STPMIC1=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SCMI=y CONFIG_RESET_SIMPLE=y @@ -440,6 +448,7 @@ CONFIG_STM32_MDMA=y CONFIG_STM32_WATCHDOG=y CONFIG_STMMAC_ETH=y CONFIG_STMMAC_PLATFORM=y +# CONFIG_STPMIC1_WATCHDOG is not set # CONFIG_STRIP_ASM_SYMS is not set CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y