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generic: backport support for MT7981 Ethernet
Backport support for the MT7981 SoC to mtk_eth_soc. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
18a9ae56e9
commit
18a3cd2062
@ -0,0 +1,183 @@
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--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
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@@ -96,12 +96,20 @@ static int set_mux_gmac2_gmac0_to_gephy(
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static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path)
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{
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- unsigned int val = 0;
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+ unsigned int val = 0, mask = 0, reg = 0;
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bool updated = true;
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switch (path) {
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case MTK_ETH_PATH_GMAC2_SGMII:
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- val = CO_QPHY_SEL;
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_U3_COPHY_V2)) {
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+ reg = USB_PHY_SWITCH_REG;
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+ val = SGMII_QPHY_SEL;
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+ mask = QPHY_SEL_MASK;
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+ } else {
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+ reg = INFRA_MISC2;
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+ val = CO_QPHY_SEL;
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+ mask = val;
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+ }
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break;
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default:
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updated = false;
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@@ -109,7 +117,7 @@ static int set_mux_u3_gmac2_to_qphy(stru
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}
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if (updated)
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- regmap_update_bits(eth->infra, INFRA_MISC2, CO_QPHY_SEL, val);
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+ regmap_update_bits(eth->infra, reg, mask, val);
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dev_dbg(eth->dev, "path %s in %s updated = %d\n",
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mtk_eth_path_name(path), __func__, updated);
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -4757,6 +4757,26 @@ static const struct mtk_soc_data mt7629_
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},
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};
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+static const struct mtk_soc_data mt7981_data = {
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+ .reg_map = &mt7986_reg_map,
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+ .ana_rgc3 = 0x128,
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+ .caps = MT7981_CAPS,
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+ .hw_features = MTK_HW_FEATURES,
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+ .required_clks = MT7981_CLKS_BITMAP,
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+ .required_pctl = false,
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+ .offload_version = 2,
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+ .hash_offset = 4,
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+ .foe_entry_size = sizeof(struct mtk_foe_entry),
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+ .txrx = {
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+ .txd_size = sizeof(struct mtk_tx_dma_v2),
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+ .rxd_size = sizeof(struct mtk_rx_dma_v2),
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+ .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
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+ .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
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+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
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+ .dma_len_offset = 8,
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+ },
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+};
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+
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static const struct mtk_soc_data mt7986_data = {
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.reg_map = &mt7986_reg_map,
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.ana_rgc3 = 0x128,
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@@ -4799,6 +4819,7 @@ const struct of_device_id of_mtk_match[]
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{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
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{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
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{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
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+ { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data},
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{ .compatible = "mediatek,mt7986-eth", .data = &mt7986_data},
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{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data},
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{},
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -553,11 +553,22 @@
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#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
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#define SGMII_PHYA_PWD BIT(4)
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+/* Register to QPHY wrapper control */
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+#define SGMSYS_QPHY_WRAP_CTRL 0xec
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+#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
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+#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
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+#define MTK_SGMII_FLAG_PN_SWAP BIT(0)
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+
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/* Infrasys subsystem config registers */
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#define INFRA_MISC2 0x70c
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#define CO_QPHY_SEL BIT(0)
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#define GEPHY_MAC_SEL BIT(1)
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+/* Top misc registers */
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+#define USB_PHY_SWITCH_REG 0x218
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+#define QPHY_SEL_MASK GENMASK(1, 0)
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+#define SGMII_QPHY_SEL 0x2
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+
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/* MT7628/88 specific stuff */
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#define MT7628_PDMA_OFFSET 0x0800
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#define MT7628_SDM_OFFSET 0x0c00
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@@ -738,6 +749,17 @@ enum mtk_clks_map {
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BIT(MTK_CLK_SGMII2_CDR_FB) | \
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BIT(MTK_CLK_SGMII_CK) | \
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BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
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+#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
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+ BIT(MTK_CLK_WOCPU0) | \
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+ BIT(MTK_CLK_SGMII_TX_250M) | \
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+ BIT(MTK_CLK_SGMII_RX_250M) | \
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+ BIT(MTK_CLK_SGMII_CDR_REF) | \
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+ BIT(MTK_CLK_SGMII_CDR_FB) | \
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+ BIT(MTK_CLK_SGMII2_TX_250M) | \
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+ BIT(MTK_CLK_SGMII2_RX_250M) | \
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+ BIT(MTK_CLK_SGMII2_CDR_REF) | \
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+ BIT(MTK_CLK_SGMII2_CDR_FB) | \
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+ BIT(MTK_CLK_SGMII_CK))
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#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
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BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
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BIT(MTK_CLK_SGMII_TX_250M) | \
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@@ -851,6 +873,7 @@ enum mkt_eth_capabilities {
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MTK_NETSYS_V2_BIT,
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MTK_SOC_MT7628_BIT,
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MTK_RSTCTRL_PPE1_BIT,
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+ MTK_U3_COPHY_V2_BIT,
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/* MUX BITS*/
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MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
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@@ -885,6 +908,7 @@ enum mkt_eth_capabilities {
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#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
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#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
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#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
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+#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT)
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#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
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BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
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@@ -963,6 +987,11 @@ enum mkt_eth_capabilities {
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MTK_MUX_U3_GMAC2_TO_QPHY | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
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+#define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \
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+ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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+ MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \
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+ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
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+
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#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
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MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
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MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
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@@ -1076,12 +1105,14 @@ struct mtk_soc_data {
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* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
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* @interface: Currently configured interface mode
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* @pcs: Phylink PCS structure
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+ * @flags: Flags indicating hardware properties
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*/
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struct mtk_pcs {
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struct regmap *regmap;
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u32 ana_rgc3;
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phy_interface_t interface;
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struct phylink_pcs pcs;
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+ u32 flags;
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};
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/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -87,6 +87,11 @@ static int mtk_pcs_config(struct phylink
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regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
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SGMII_PHYA_PWD, SGMII_PHYA_PWD);
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+ if (mpcs->flags & MTK_SGMII_FLAG_PN_SWAP)
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+ regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
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+ SGMII_PN_SWAP_MASK,
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+ SGMII_PN_SWAP_TX_RX);
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+
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/* Reset SGMII PCS state */
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regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
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SGMII_SW_RESET, SGMII_SW_RESET);
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@@ -186,6 +191,11 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
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ss->pcs[i].ana_rgc3 = ana_rgc3;
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ss->pcs[i].regmap = syscon_node_to_regmap(np);
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+
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+ ss->pcs[i].flags = 0;
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+ if (of_property_read_bool(np, "mediatek,pnswap"))
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+ ss->pcs[i].flags |= MTK_SGMII_FLAG_PN_SWAP;
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+
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of_node_put(np);
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if (IS_ERR(ss->pcs[i].regmap))
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return PTR_ERR(ss->pcs[i].regmap);
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@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -1326,6 +1326,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
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@@ -1357,6 +1357,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
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int mtk_eth_offload_init(struct mtk_eth *eth);
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int mtk_eth_offload_init(struct mtk_eth *eth);
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int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
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int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
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void *type_data);
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void *type_data);
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