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include: move generic riscv64 ISA to rv64gc

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The current CFLAGS (rv64imafdc) for the riscv64 targets do not contain
the full generic compute extension (g), as that also includes the
zicsr and zifencei extensions/instructions. Rename the default ISA to
'generic' to add distinction to the current binaries (although it's very
minimal), and use rv64gc for CFLAGS.

This is also a prep step for the upcoming gcv (vector-extension supporting)
targets like the Spacemit K1, and the thead-cores like the TH1520.

Compile-tested: all riscv64 targets
Runtime-tested:
 - SiFive Unleashed (FU540)
 - SiFive Unmatched (FU740)
 - Nezha D1 (D1)
 - VisionFive2 (JH7110)

Link: https://github.com/openwrt/openwrt/pull/18094
Tested-by: Chuanhong Guo <gch981213@gmail.com> # siflower target
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This commit is contained in:
Zoltan HERPAI 2025-02-24 12:18:01 +00:00
parent 8cb7919a13
commit 143569c2ed
1 changed files with 2 additions and 2 deletions
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4
include/target.mk
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@ -274,8 +274,8 @@ ifeq ($(DUMP),1)
CPU_CFLAGS_archs = -mcpu=archs
endif
ifeq ($(ARCH),riscv64)
CPU_TYPE ?= riscv64
CPU_CFLAGS_riscv64:=-mabi=lp64d -march=rv64imafdc
CPU_TYPE ?= generic
CPU_CFLAGS_generic:=-mabi=lp64d -march=rv64gc
endif
ifeq ($(ARCH),loongarch64)
CPU_TYPE ?= generic