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Revert "ramips: pci: sync with staging driver"
This reverts commit e07baec9faf487fd143976636025b5da55e13c20. Signed-off-by: John Crispin <john@phrozen.org>
This commit is contained in:
John Crispin
parent
bf5829ddf9
commit
0bfb41a55a
@ -52,10 +52,14 @@
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <ralink_regs.h>
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extern void pcie_phy_init(void);
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extern void chk_phy_pll(void);
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/*
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* These functions and structures provide the BIOS scan and mapping of the PCI
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* devices.
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@ -113,6 +117,7 @@
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#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
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#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
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#define MV_WRITE(ofs, data) \
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*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
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#define MV_READ(ofs, data) \
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@ -130,20 +135,20 @@
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#define MV_READ_8(ofs, data) \
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*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
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#define RALINK_PCI_MM_MAP_BASE 0x60000000
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#define RALINK_PCI_IO_MAP_BASE 0x1e160000
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#define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
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#define ASSERT_SYSRST_PCIE(val) \
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do { \
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#define ASSERT_SYSRST_PCIE(val) do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL |= val; \
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else \
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RALINK_RSTCTRL &= ~val; \
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} while(0)
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#define DEASSERT_SYSRST_PCIE(val) \
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do { \
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#define DEASSERT_SYSRST_PCIE(val) do { \
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if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
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RALINK_RSTCTRL &= ~val; \
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else \
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@ -183,6 +188,8 @@ static int pcie_link_status = 0;
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#define PCI_ACCESS_WRITE_2 4
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#define PCI_ACCESS_WRITE_4 5
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static int pcie_irq[3];
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static int config_access(unsigned char access_type, struct pci_bus *bus,
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unsigned int devfn, unsigned int where, u32 * data)
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{
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@ -268,6 +275,7 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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{
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@ -301,6 +309,7 @@ struct pci_ops mt7621_pci_ops= {
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static struct resource mt7621_res_pci_mem1;
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static struct resource mt7621_res_pci_io1;
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static struct pci_controller mt7621_controller = {
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.pci_ops = &mt7621_pci_ops,
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.mem_resource = &mt7621_res_pci_mem1,
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@ -333,6 +342,7 @@ write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned
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return;
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}
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int
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pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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@ -361,8 +371,11 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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void
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set_pcie_phy(u32 *addr, int start_b, int bits, int val)
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{
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// printk("0x%p:", addr);
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// printk(" %x", *addr);
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*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
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*(unsigned int *)(addr) |= val << start_b;
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// printk(" -> %x\n", *addr);
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}
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void
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@ -465,21 +478,25 @@ void setup_cm_memory_region(struct resource *mem_resource)
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resource_size_t mask;
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if (mips_cps_numiocu(0)) {
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/* FIXME: hardware doesn't accept mask values with 1s after
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* 0s (e.g. 0xffef), so it would be great to warn if that's
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* about to happen */
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0s (e.g. 0xffef), so it would be great to warn if that's
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about to happen */
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mask = ~(mem_resource->end - mem_resource->start);
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write_gcr_reg1_base(mem_resource->start);
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write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
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(unsigned long long)read_gcr_reg1_base(),
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(unsigned long long)read_gcr_reg1_mask());
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printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
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read_gcr_reg1_base(),
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read_gcr_reg1_mask());
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}
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}
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static int mt7621_pci_probe(struct platform_device *pdev)
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{
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unsigned long val = 0;
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int i;
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for (i = 0; i < 3; i++)
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pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
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iomem_resource.start = 0;
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iomem_resource.end= ~0;
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@ -491,6 +508,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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val |= RALINK_PCIE2_RST;
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ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
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printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
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*(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
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*(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
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@ -506,17 +524,17 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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val |= RALINK_PCIE2_RST;
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DEASSERT_SYSRST_PCIE(val);
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printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
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if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
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bypass_pipe_rst();
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set_phy_for_ssc();
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printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
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read_config(0, 0, 0, 0x70c, &val);
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printk("Port 0 N_FTS = %x\n", (unsigned int)val);
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read_config(0, 1, 0, 0x70c, &val);
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printk("Port 1 N_FTS = %x\n", (unsigned int)val);
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read_config(0, 2, 0, 0x70c, &val);
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printk("Port 2 N_FTS = %x\n", (unsigned int)val);
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@ -544,7 +562,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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pcie_link_status |= 1<<0;
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RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
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}
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if(( RALINK_PCI1_STATUS & 0x1) == 0)
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{
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printk("PCIE1 no card, disable it(RST&CLK)\n");
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@ -555,7 +572,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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pcie_link_status |= 1<<1;
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RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
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}
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if (( RALINK_PCI2_STATUS & 0x1) == 0) {
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printk("PCIE2 no card, disable it(RST&CLK)\n");
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ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
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@ -565,7 +581,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
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pcie_link_status |= 1<<2;
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RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
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}
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if (pcie_link_status == 0)
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return 0;
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@ -605,6 +620,8 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
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break;
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}
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printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
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//printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
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/*
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ioport_resource.start = mt7621_res_pci_io1.start;
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@ -621,7 +638,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI0_CLASS = 0x06040001;
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printk("PCIE0 enabled\n");
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}
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//PCIe1
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if ((pcie_link_status & 0x2) != 0) {
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RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
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@ -629,7 +645,6 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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RALINK_PCI1_CLASS = 0x06040001;
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printk("PCIE1 enabled\n");
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}
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//PCIe2
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if ((pcie_link_status & 0x4) != 0) {
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RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
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@ -642,6 +657,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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case 7:
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read_config(0, 2, 0, 0x4, &val);
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write_config(0, 2, 0, 0x4, val|0x4);
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// write_config(0, 1, 0, 0x4, val|0x7);
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read_config(0, 2, 0, 0x70c, &val);
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val &= ~(0xff)<<8;
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val |= 0x50<<8;
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@ -651,6 +667,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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case 6:
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read_config(0, 1, 0, 0x4, &val);
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write_config(0, 1, 0, 0x4, val|0x4);
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// write_config(0, 1, 0, 0x4, val|0x7);
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read_config(0, 1, 0, 0x70c, &val);
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val &= ~(0xff)<<8;
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val |= 0x50<<8;
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@ -658,6 +675,7 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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default:
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read_config(0, 0, 0, 0x4, &val);
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write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
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// write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
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read_config(0, 0, 0, 0x70c, &val);
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val &= ~(0xff)<<8;
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val |= 0x50<<8;
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