mirror of
https://github.com/openwrt/openwrt.git
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layerscape: upgrade kernel to 4.14
This patch is to upgrade kernel to 4.14 for layerscape. patches-4.14 for layerscape included two categories. - NXP Layerscape SDK kernel-4.14 patches All patches on tag LSDK-18.09-V4.14 were ported to OpenWrt kernel. Since there were hundreds patches, we had to make an all-in-one patch for each IP/feature. See below links for LSDK kernel. https://lsdk.github.io/components.html https://source.codeaurora.org/external/qoriq/qoriq-components/linux - Non-LSDK kernel patches Other patches which were not in LSDK were just put in patches-4.14. Kept below patches from patches-4.9. 303-dts-layerscape-add-traverse-ls1043.patch 821-add-esdhc-vsel-to-ls1043.patch 822-rgmii-fixed-link.patch Renamed and rebase them as below in patches-4.14, 303-add-DTS-for-Traverse-LS1043-Boards.patch 712-sdk-dpaa-rgmii-fixed-link.patch 824-mmc-sdhci-of-esdhc-add-voltage-switch-support-for-ls.patch Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>
This commit is contained in:
Biwen Li
Hauke Mehrtens
parent
7bd6969acc
commit
0a827ebd2f
@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk
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BOARD:=layerscape
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BOARDNAME:=NXP Layerscape
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KERNEL_PATCHVER:=4.9
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KERNEL_PATCHVER:=4.14
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FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4
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SUBTARGETS:=armv8_64b armv8_32b armv7
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MAINTAINER:=Yangbo Lu <yangbo.lu@nxp.com>
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780
target/linux/layerscape/armv7/config-4.14
Executable file
780
target/linux/layerscape/armv7/config-4.14
Executable file
@ -0,0 +1,780 @@
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CONFIG_AD525X_DPOT=y
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CONFIG_AD525X_DPOT_I2C=y
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# CONFIG_AD525X_DPOT_SPI is not set
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CONFIG_ALIGNMENT_TRAP=y
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CONFIG_APDS9802ALS=y
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CONFIG_AQUANTIA_PHY=y
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# CONFIG_ARCH_AXXIA is not set
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_ARCH_HAS_RESET_CONTROLLER=y
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CONFIG_ARCH_HAS_SET_MEMORY=y
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CONFIG_ARCH_HAS_SG_CHAIN=y
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CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
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CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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# CONFIG_ARCH_MULTI_CPU_AUTO is not set
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CONFIG_ARCH_MULTI_V6_V7=y
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CONFIG_ARCH_MULTI_V7=y
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CONFIG_ARCH_MXC=y
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CONFIG_ARCH_NR_GPIO=0
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
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CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
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# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
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# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
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CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
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CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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CONFIG_ARM_APPENDED_DTB=y
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CONFIG_ARM_ARCH_TIMER=y
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CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
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CONFIG_ARM_ATAG_DTB_COMPAT=y
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# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
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CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
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CONFIG_ARM_CPUIDLE=y
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CONFIG_ARM_CPU_SUSPEND=y
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CONFIG_ARM_ERRATA_430973=y
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CONFIG_ARM_ERRATA_643719=y
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CONFIG_ARM_ERRATA_720789=y
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CONFIG_ARM_ERRATA_754322=y
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CONFIG_ARM_ERRATA_754327=y
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CONFIG_ARM_ERRATA_764369=y
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CONFIG_ARM_ERRATA_775420=y
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CONFIG_ARM_ERRATA_798181=y
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CONFIG_ARM_GIC=y
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CONFIG_ARM_HAS_SG_CHAIN=y
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CONFIG_ARM_HEAVY_MB=y
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# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
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CONFIG_ARM_L1_CACHE_SHIFT=6
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CONFIG_ARM_L1_CACHE_SHIFT_6=y
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CONFIG_ARM_LPAE=y
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CONFIG_ARM_PATCH_IDIV=y
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CONFIG_ARM_PATCH_PHYS_VIRT=y
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CONFIG_ARM_PMU=y
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CONFIG_ARM_PSCI=y
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CONFIG_ARM_PSCI_FW=y
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# CONFIG_ARM_SMMU is not set
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CONFIG_ARM_THUMB=y
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CONFIG_ARM_THUMBEE=y
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CONFIG_ARM_TIMER_SP804=y
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CONFIG_ARM_UNWIND=y
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CONFIG_ARM_VIRT_EXT=y
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CONFIG_AT803X_PHY=y
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CONFIG_ATAGS=y
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CONFIG_AUTOFS4_FS=y
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CONFIG_AUTO_ZRELADDR=y
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CONFIG_BATTERY_SBS=y
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CONFIG_BCM_NET_PHYLIB=y
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CONFIG_BINARY_PRINTF=y
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CONFIG_BLK_CMDLINE_PARSER=y
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CONFIG_BLK_DEV_BSG=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_COUNT=16
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CONFIG_BLK_DEV_RAM_SIZE=262144
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_DEV_SR=y
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# CONFIG_BLK_DEV_SR_VENDOR is not set
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BLK_MQ_VIRTIO=y
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CONFIG_BLK_SCSI_REQUEST=y
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# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
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CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
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CONFIG_BOUNCE=y
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# CONFIG_BPF_SYSCALL is not set
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CONFIG_BRCMSTB_GISB_ARB=y
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CONFIG_BROADCOM_PHY=y
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CONFIG_BUILD_BIN2C=y
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CONFIG_CACHE_L2X0=y
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# CONFIG_CACHE_L2X0_PMU is not set
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CONFIG_CHECKPOINT_RESTORE=y
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CONFIG_CHR_DEV_SG=y
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CONFIG_CLKDEV_LOOKUP=y
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CONFIG_CLKSRC_IMX_GPT=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLK_QORIQ=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_CMA=y
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CONFIG_CMA_ALIGNMENT=8
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CONFIG_CMA_AREAS=7
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# CONFIG_CMA_DEBUG is not set
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# CONFIG_CMA_DEBUGFS is not set
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CONFIG_CMA_SIZE_MBYTES=64
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# CONFIG_CMA_SIZE_SEL_MAX is not set
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CONFIG_CMA_SIZE_SEL_MBYTES=y
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# CONFIG_CMA_SIZE_SEL_MIN is not set
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# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
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CONFIG_CMDLINE_PARTITION=y
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CONFIG_COMMON_CLK=y
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CONFIG_COMPAT_BRK=y
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CONFIG_CONFIGFS_FS=y
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CONFIG_CONSOLE_TRANSLATIONS=y
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CONFIG_CONTEXT_SWITCH_TRACER=y
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CONFIG_COREDUMP=y
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CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_32v6K=y
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CONFIG_CPU_32v7=y
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CONFIG_CPU_ABRT_EV7=y
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# CONFIG_CPU_BIG_ENDIAN is not set
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# CONFIG_CPU_BPREDICT_DISABLE is not set
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CONFIG_CPU_CACHE_V7=y
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CONFIG_CPU_CACHE_VIPT=y
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CONFIG_CPU_COPY_V6=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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CONFIG_CPU_FREQ=y
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CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
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# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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CONFIG_CPU_FREQ_GOV_COMMON=y
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# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
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CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
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# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_IDLE=y
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# CONFIG_CPU_IDLE_GOV_LADDER is not set
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CONFIG_CPU_IDLE_GOV_MENU=y
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CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_PM=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_SPECTRE=y
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CONFIG_CPU_THERMAL=y
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CONFIG_CPU_THUMB_CAPABLE=y
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CONFIG_CPU_TLB_V7=y
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CONFIG_CPU_V7=y
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CONFIG_CRASH_CORE=y
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CONFIG_CRC16=y
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# CONFIG_CRC32_SARWATE is not set
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CONFIG_CRC32_SLICEBY8=y
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CONFIG_CROSS_MEMORY_ATTACH=y
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CONFIG_CRYPTO_ACOMP2=y
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CONFIG_CRYPTO_AEAD=y
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CONFIG_CRYPTO_AEAD2=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_MANAGER=y
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CONFIG_CRYPTO_MANAGER2=y
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CONFIG_CRYPTO_NULL2=y
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CONFIG_CRYPTO_RNG2=y
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# CONFIG_CRYPTO_TLS is not set
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CONFIG_CRYPTO_WORKQUEUE=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_ALIGN_RODATA=y
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CONFIG_DEBUG_BUGVERBOSE=y
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CONFIG_DEBUG_IMX_UART_PORT=1
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CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
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# CONFIG_DEBUG_UART_8250 is not set
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# CONFIG_DEBUG_USER is not set
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CONFIG_DECOMPRESS_BZIP2=y
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CONFIG_DECOMPRESS_GZIP=y
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CONFIG_DECOMPRESS_LZMA=y
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CONFIG_DECOMPRESS_LZO=y
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CONFIG_DECOMPRESS_XZ=y
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CONFIG_DEFAULT_CFQ=y
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# CONFIG_DEFAULT_DEADLINE is not set
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CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
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CONFIG_DEFAULT_IOSCHED="cfq"
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CONFIG_DETECT_HUNG_TASK=y
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# CONFIG_DEVFREQ_GOV_PASSIVE is not set
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# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
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# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
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# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
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# CONFIG_DEVFREQ_GOV_USERSPACE is not set
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# CONFIG_DEVFREQ_THERMAL is not set
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CONFIG_DEVKMEM=y
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CONFIG_DEVMEM=y
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CONFIG_DEVTMPFS=y
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CONFIG_DEVTMPFS_MOUNT=y
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CONFIG_DMADEVICES=y
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CONFIG_DMA_CMA=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_OF=y
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CONFIG_DMA_SHARED_BUFFER=y
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CONFIG_DMA_VIRTUAL_CHANNELS=y
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CONFIG_DMI=y
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CONFIG_DMIID=y
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# CONFIG_DMI_SYSFS is not set
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_DT_IDLE_STATES=y
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CONFIG_DUMMY_CONSOLE=y
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CONFIG_DW_DMAC=y
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CONFIG_DW_DMAC_CORE=y
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CONFIG_DW_WATCHDOG=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_93CX6=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EFI=y
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# CONFIG_EFIVAR_FS is not set
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CONFIG_EFI_ARMSTUB=y
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# CONFIG_EFI_CAPSULE_LOADER is not set
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CONFIG_EFI_ESRT=y
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CONFIG_EFI_PARAMS_FROM_FDT=y
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CONFIG_EFI_RUNTIME_WRAPPERS=y
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CONFIG_EFI_STUB=y
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# CONFIG_EFI_TEST is not set
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# CONFIG_EFI_VARS is not set
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CONFIG_ELF_CORE=y
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# CONFIG_ENABLE_DEFAULT_TRACERS is not set
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CONFIG_ENABLE_MUST_CHECK=y
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CONFIG_EVENT_TRACING=y
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CONFIG_EXT4_FS=y
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CONFIG_EXT4_FS_POSIX_ACL=y
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CONFIG_EXT4_FS_SECURITY=y
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CONFIG_FAT_FS=y
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# CONFIG_FEC is not set
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CONFIG_FHANDLE=y
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CONFIG_FIRMWARE_IN_KERNEL=y
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CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FORCE_MAX_ZONEORDER=12
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CONFIG_FREEZER=y
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# CONFIG_FSL_DPAA2_ETH_CEETM is not set
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CONFIG_FSL_EDMA=y
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CONFIG_FSL_GUTS=y
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CONFIG_FSL_IFC=y
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# CONFIG_FSL_PPFE is not set
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CONFIG_FSL_PQ_MDIO=y
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# CONFIG_FSL_QDMA is not set
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# CONFIG_FSL_SDK_DPA is not set
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CONFIG_FSL_XGMAC_MDIO=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FS_POSIX_ACL=y
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CONFIG_FTM_ALARM=y
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CONFIG_FTRACE=y
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# CONFIG_FTRACE_SYSCALLS is not set
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CONFIG_FUSE_FS=y
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# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_EARLY_IOREMAP=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IO=y
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CONFIG_GENERIC_IRQ_CHIP=y
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CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
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CONFIG_GENERIC_MSI_IRQ=y
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CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_PHY=y
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CONFIG_GENERIC_PINCONF=y
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CONFIG_GENERIC_PINCTRL_GROUPS=y
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CONFIG_GENERIC_PINMUX_FUNCTIONS=y
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CONFIG_GENERIC_SCHED_CLOCK=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_STRNCPY_FROM_USER=y
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CONFIG_GENERIC_STRNLEN_USER=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GIANFAR=y
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CONFIG_GLOB=y
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CONFIG_GPIOLIB=y
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CONFIG_GPIO_GENERIC=y
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CONFIG_GPIO_GENERIC_PLATFORM=y
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CONFIG_GPIO_MPC8XXX=y
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CONFIG_GPIO_MXC=y
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# CONFIG_GRO_CELLS is not set
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
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CONFIG_HARDIRQS_SW_RESEND=y
|
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CONFIG_HAS_DMA=y
|
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT_MAP=y
|
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# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
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CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
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CONFIG_HAVE_ARCH_BITREVERSE=y
|
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CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
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CONFIG_HAVE_ARCH_KGDB=y
|
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CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
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CONFIG_HAVE_ARCH_TRACEHOOK=y
|
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CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
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CONFIG_HAVE_ARM_ARCH_TIMER=y
|
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CONFIG_HAVE_ARM_SMCCC=y
|
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# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
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CONFIG_HAVE_CC_STACKPROTECTOR=y
|
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CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_CLK_PREPARE=y
|
||||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
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CONFIG_HAVE_C_RECORDMCOUNT=y
|
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
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CONFIG_HAVE_DYNAMIC_FTRACE=y
|
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CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_HAVE_EBPF_JIT=y
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_GENERIC_GUP=y
|
||||
CONFIG_HAVE_HW_BREAKPOINT=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_IMX_SRC=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_OPTPROBES=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HAVE_PERF_REGS=y
|
||||
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
||||
CONFIG_HAVE_PROC_CPU=y
|
||||
CONFIG_HAVE_RCU_TABLE_FREE=y
|
||||
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_HAVE_UID16=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
# CONFIG_HUGETLBFS is not set
|
||||
CONFIG_HVC_DRIVER=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_IMX_RNGC=y
|
||||
CONFIG_HZ_FIXED=0
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_DEMUX_PINCTRL=y
|
||||
CONFIG_I2C_DESIGNWARE_CORE=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_IMX=y
|
||||
# CONFIG_I2C_IMX_LPI2C is not set
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_I2C_MUX_PINCTRL=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_I2C_SLAVE=y
|
||||
CONFIG_I2C_SLAVE_EEPROM=y
|
||||
CONFIG_I2C_XILINX=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
CONFIG_ICS932S401=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_IMX2_WDT=y
|
||||
CONFIG_IMX_DMA=y
|
||||
CONFIG_IMX_SDMA=y
|
||||
# CONFIG_IMX_WEIM is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_INPUT=y
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
CONFIG_IOMMU_HELPER=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_IPC_NS=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_ISDN is not set
|
||||
CONFIG_ISL29003=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KERNEL_GZIP=y
|
||||
# CONFIG_KERNEL_XZ is not set
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LS_SCFG_MSI=y
|
||||
CONFIG_LS_SOC_DRIVERS=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_MCPM=y
|
||||
CONFIG_MDIO_BITBANG=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
# CONFIG_MDIO_FSL_BACKPLANE is not set
|
||||
# CONFIG_MDIO_GPIO is not set
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
# CONFIG_MFD_VEXPRESS_SYSREG is not set
|
||||
CONFIG_MICREL_PHY=y
|
||||
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
||||
CONFIG_MIGHT_HAVE_PCI=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
# CONFIG_MMC_MXC is not set
|
||||
CONFIG_MMC_SDHCI=y
|
||||
# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
|
||||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
||||
CONFIG_MMC_SDHCI_OF_ESDHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
# CONFIG_MMC_TIFM_SD is not set
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_GEOMETRY=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_DATAFLASH=y
|
||||
# CONFIG_MTD_DATAFLASH_OTP is not set
|
||||
# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SST25L=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
# CONFIG_MTD_UBI_BLOCK is not set
|
||||
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MULTI_IRQ_HANDLER=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_MX3_IPU=y
|
||||
CONFIG_MX3_IPU_IRQS=4
|
||||
# CONFIG_MXS_DMA is not set
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_NATIONAL_PHY=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_NS=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_NOP_TRACER=y
|
||||
CONFIG_NO_BOOTMEM=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=16
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_NVMEM=y
|
||||
# CONFIG_NVMEM_IMX_IIM is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_ADDRESS_PCI=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_PCI=y
|
||||
CONFIG_OF_PCI_IRQ=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_OUTER_CACHE_SYNC=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
# CONFIG_PCIEASPM_DEBUG is not set
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_ECAM=y
|
||||
CONFIG_PCI_HOST_COMMON=y
|
||||
CONFIG_PCI_HOST_GENERIC=y
|
||||
CONFIG_PCI_LABEL=y
|
||||
CONFIG_PCI_LAYERSCAPE=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=3
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PID_NS=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_PL310_ERRATA_727915=y
|
||||
CONFIG_PL310_ERRATA_753970=y
|
||||
CONFIG_PL310_ERRATA_769419=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_PM_SLEEP=y
|
||||
CONFIG_PM_SLEEP_SMP=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_POSIX_MQUEUE_SYSCTL=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_BRCMKONA=y
|
||||
CONFIG_POWER_RESET_BRCMSTB=y
|
||||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_POWER_RESET_GPIO_RESTART=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
|
||||
CONFIG_POWER_RESET_VEXPRESS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PROBE_EVENTS=y
|
||||
CONFIG_PROC_CHILDREN=y
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_CONSOLE=y
|
||||
# CONFIG_PSTORE_LZ4_COMPRESS is not set
|
||||
# CONFIG_PSTORE_LZO_COMPRESS is not set
|
||||
CONFIG_PSTORE_PMSG=y
|
||||
CONFIG_PSTORE_RAM=y
|
||||
CONFIG_PSTORE_ZLIB_COMPRESS=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
CONFIG_PTP_1588_CLOCK_GIANFAR=y
|
||||
CONFIG_QORIQ_CPUFREQ=y
|
||||
# CONFIG_QUICC_ENGINE is not set
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REED_SOLOMON=y
|
||||
CONFIG_REED_SOLOMON_DEC8=y
|
||||
CONFIG_REED_SOLOMON_ENC8=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_SPI=y
|
||||
# CONFIG_RESET_ATTACK_MITIGATION is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RING_BUFFER=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_CMOS is not set
|
||||
CONFIG_RTC_DRV_DS1307=y
|
||||
CONFIG_RTC_DRV_DS3232=y
|
||||
# CONFIG_RTC_DRV_EFI is not set
|
||||
CONFIG_RTC_DRV_EM3027=y
|
||||
# CONFIG_RTC_DRV_IMXDI is not set
|
||||
# CONFIG_RTC_DRV_MXC is not set
|
||||
CONFIG_RTC_DRV_PCF2127=y
|
||||
CONFIG_RTC_DRV_PCF85263=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_SCHED_DEBUG=y
|
||||
# CONFIG_SCHED_INFO is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_EM=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_BCM63XX=y
|
||||
CONFIG_SERIAL_BCM63XX_CONSOLE=y
|
||||
CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
|
||||
CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
|
||||
CONFIG_SERIAL_FSL_LPUART=y
|
||||
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
|
||||
CONFIG_SERIAL_IMX=y
|
||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_ST_ASC=y
|
||||
CONFIG_SERIAL_ST_ASC_CONSOLE=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
CONFIG_SOCK_DIAG=y
|
||||
CONFIG_SOC_BRCMSTB=y
|
||||
CONFIG_SOC_BUS=y
|
||||
# CONFIG_SOC_IMX50 is not set
|
||||
# CONFIG_SOC_IMX51 is not set
|
||||
# CONFIG_SOC_IMX53 is not set
|
||||
# CONFIG_SOC_IMX6Q is not set
|
||||
# CONFIG_SOC_IMX6SL is not set
|
||||
# CONFIG_SOC_IMX6SX is not set
|
||||
# CONFIG_SOC_IMX6UL is not set
|
||||
# CONFIG_SOC_IMX7D is not set
|
||||
CONFIG_SOC_LS1021A=y
|
||||
# CONFIG_SOC_VF610 is not set
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_CADENCE=y
|
||||
# CONFIG_SPI_FSL_LPSPI is not set
|
||||
# CONFIG_SPI_FSL_QUADSPI is not set
|
||||
# CONFIG_SPI_IMX is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
CONFIG_SPI_XILINX=y
|
||||
CONFIG_SPMI=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_ZLIB=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRAM_EXEC=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKTRACE=y
|
||||
CONFIG_STAGING_BOARD=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
CONFIG_SUSPEND=y
|
||||
CONFIG_SUSPEND_FREEZER=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_TRACEPOINTS=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACING=y
|
||||
CONFIG_TRACING_EVENTS_GPIO=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UCS2_STRING=y
|
||||
CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_UPROBES=y
|
||||
CONFIG_UPROBE_EVENTS=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_UTS_NS=y
|
||||
CONFIG_VDSO=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_VEXPRESS_CONFIG=y
|
||||
CONFIG_VEXPRESS_SYSCFG=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_PCI_LEGACY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_CONSOLE_SLEEP=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
|
||||
CONFIG_XILINX_WATCHDOG=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_POWERPC=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
CONFIG_XZ_DEC_X86=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
937
target/linux/layerscape/armv8_32b/config-4.14
Normal file
937
target/linux/layerscape/armv8_32b/config-4.14
Normal file
@ -0,0 +1,937 @@
|
||||
CONFIG_AD525X_DPOT=y
|
||||
CONFIG_AD525X_DPOT_I2C=y
|
||||
# CONFIG_AD525X_DPOT_SPI is not set
|
||||
CONFIG_ALIGNMENT_TRAP=y
|
||||
CONFIG_APDS9802ALS=y
|
||||
CONFIG_AQUANTIA_PHY=y
|
||||
# CONFIG_ARCH_AXXIA is not set
|
||||
CONFIG_ARCH_CLOCKSOURCE_DATA=y
|
||||
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
|
||||
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
||||
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
|
||||
CONFIG_ARCH_HAS_SET_MEMORY=y
|
||||
CONFIG_ARCH_HAS_SG_CHAIN=y
|
||||
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
|
||||
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
|
||||
CONFIG_ARCH_HAS_TICK_BROADCAST=y
|
||||
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
|
||||
CONFIG_ARCH_MULTIPLATFORM=y
|
||||
# CONFIG_ARCH_MULTI_CPU_AUTO is not set
|
||||
CONFIG_ARCH_MULTI_V6_V7=y
|
||||
CONFIG_ARCH_MULTI_V7=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_ARCH_NR_GPIO=0
|
||||
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
|
||||
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
|
||||
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
|
||||
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
|
||||
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
|
||||
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
|
||||
CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
|
||||
CONFIG_ARCH_SUPPORTS_UPROBES=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
|
||||
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
|
||||
CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
|
||||
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARM_APPENDED_DTB=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
|
||||
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_CPU_SUSPEND=y
|
||||
CONFIG_ARM_ERRATA_430973=y
|
||||
CONFIG_ARM_ERRATA_643719=y
|
||||
CONFIG_ARM_ERRATA_720789=y
|
||||
CONFIG_ARM_ERRATA_754322=y
|
||||
CONFIG_ARM_ERRATA_754327=y
|
||||
CONFIG_ARM_ERRATA_764369=y
|
||||
CONFIG_ARM_ERRATA_775420=y
|
||||
CONFIG_ARM_ERRATA_798181=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_HAS_SG_CHAIN=y
|
||||
CONFIG_ARM_HEAVY_MB=y
|
||||
# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
|
||||
CONFIG_ARM_L1_CACHE_SHIFT=6
|
||||
CONFIG_ARM_L1_CACHE_SHIFT_6=y
|
||||
CONFIG_ARM_LPAE=y
|
||||
CONFIG_ARM_PATCH_IDIV=y
|
||||
CONFIG_ARM_PATCH_PHYS_VIRT=y
|
||||
CONFIG_ARM_PMU=y
|
||||
CONFIG_ARM_PSCI=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
# CONFIG_ARM_SMMU is not set
|
||||
CONFIG_ARM_THUMB=y
|
||||
CONFIG_ARM_THUMBEE=y
|
||||
CONFIG_ARM_TIMER_SP804=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
CONFIG_ARM_VIRT_EXT=y
|
||||
CONFIG_ASSOCIATIVE_ARRAY=y
|
||||
CONFIG_AT803X_PHY=y
|
||||
CONFIG_ATAGS=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_AUTO_ZRELADDR=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BATTERY_SBS=y
|
||||
CONFIG_BCM_NET_PHYLIB=y
|
||||
CONFIG_BINARY_PRINTF=y
|
||||
CONFIG_BLK_CMDLINE_PARSER=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=16
|
||||
CONFIG_BLK_DEV_RAM_SIZE=262144
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_DEV_SR=y
|
||||
# CONFIG_BLK_DEV_SR_VENDOR is not set
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_MQ_VIRTIO=y
|
||||
CONFIG_BLK_SCSI_REQUEST=y
|
||||
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
|
||||
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
|
||||
CONFIG_BOUNCE=y
|
||||
# CONFIG_BPF_SYSCALL is not set
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_CACHE_L2X0=y
|
||||
# CONFIG_CACHE_L2X0_PMU is not set
|
||||
CONFIG_CAN=y
|
||||
CONFIG_CAN_BCM=y
|
||||
CONFIG_CAN_CALC_BITTIMING=y
|
||||
# CONFIG_CAN_CC770 is not set
|
||||
# CONFIG_CAN_C_CAN is not set
|
||||
CONFIG_CAN_DEV=y
|
||||
CONFIG_CAN_FLEXCAN=y
|
||||
# CONFIG_CAN_GRCAN is not set
|
||||
CONFIG_CAN_GW=y
|
||||
# CONFIG_CAN_LEDS is not set
|
||||
CONFIG_CAN_MCP251X=y
|
||||
CONFIG_CAN_RAW=y
|
||||
# CONFIG_CAN_SJA1000 is not set
|
||||
# CONFIG_CAN_SOFTING is not set
|
||||
# CONFIG_CAN_TI_HECC is not set
|
||||
CONFIG_CHECKPOINT_RESTORE=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLKSRC_IMX_GPT=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLK_QORIQ=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
CONFIG_CMDLINE_PARTITION=y
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMPAT_BRK=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_CONTEXT_SWITCH_TRACER=y
|
||||
CONFIG_COREDUMP=y
|
||||
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_32v6K=y
|
||||
CONFIG_CPU_32v7=y
|
||||
CONFIG_CPU_ABRT_EV7=y
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
# CONFIG_CPU_BPREDICT_DISABLE is not set
|
||||
CONFIG_CPU_CACHE_V7=y
|
||||
CONFIG_CPU_CACHE_VIPT=y
|
||||
CONFIG_CPU_COPY_V6=y
|
||||
CONFIG_CPU_CP15=y
|
||||
CONFIG_CPU_CP15_MMU=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
CONFIG_CPU_FREQ_GOV_COMMON=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_HAS_ASID=y
|
||||
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
|
||||
# CONFIG_CPU_ICACHE_DISABLE is not set
|
||||
CONFIG_CPU_IDLE=y
|
||||
# CONFIG_CPU_IDLE_GOV_LADDER is not set
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_PABRT_V7=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_SPECTRE=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CPU_THUMB_CAPABLE=y
|
||||
CONFIG_CPU_TLB_V7=y
|
||||
CONFIG_CPU_V7=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_ACOMP2=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
# CONFIG_CRYPTO_TLS is not set
|
||||
CONFIG_CRYPTO_WORKQUEUE=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_ALIGN_RODATA=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEBUG_IMX_UART_PORT=1
|
||||
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
|
||||
# CONFIG_DEBUG_UART_8250 is not set
|
||||
# CONFIG_DEBUG_USER is not set
|
||||
CONFIG_DECOMPRESS_BZIP2=y
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
CONFIG_DECOMPRESS_LZMA=y
|
||||
CONFIG_DECOMPRESS_LZO=y
|
||||
CONFIG_DECOMPRESS_XZ=y
|
||||
CONFIG_DEFAULT_CFQ=y
|
||||
# CONFIG_DEFAULT_DEADLINE is not set
|
||||
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEVKMEM=y
|
||||
CONFIG_DEVMEM=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
||||
CONFIG_DMI=y
|
||||
CONFIG_DMIID=y
|
||||
# CONFIG_DMI_SYSFS is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_BRIDGE=y
|
||||
CONFIG_DRM_FBDEV_EMULATION=y
|
||||
CONFIG_DRM_FBDEV_OVERALLOC=100
|
||||
CONFIG_DRM_FSL_DCU=y
|
||||
CONFIG_DRM_GEM_CMA_HELPER=y
|
||||
CONFIG_DRM_KMS_CMA_HELPER=y
|
||||
CONFIG_DRM_KMS_FB_HELPER=y
|
||||
CONFIG_DRM_KMS_HELPER=y
|
||||
CONFIG_DRM_PANEL=y
|
||||
CONFIG_DRM_PANEL_BRIDGE=y
|
||||
CONFIG_DRM_PANEL_SIMPLE=y
|
||||
CONFIG_DRM_SII902X=y
|
||||
# CONFIG_DRM_VIRTIO_GPU is not set
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DW_DMAC=y
|
||||
CONFIG_DW_DMAC_CORE=y
|
||||
CONFIG_DW_WATCHDOG=y
|
||||
CONFIG_EDAC_ATOMIC_SCRUB=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_93CX6=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EFI=y
|
||||
# CONFIG_EFIVAR_FS is not set
|
||||
CONFIG_EFI_ARMSTUB=y
|
||||
# CONFIG_EFI_CAPSULE_LOADER is not set
|
||||
CONFIG_EFI_ESRT=y
|
||||
CONFIG_EFI_PARAMS_FROM_FDT=y
|
||||
CONFIG_EFI_RUNTIME_WRAPPERS=y
|
||||
CONFIG_EFI_STUB=y
|
||||
# CONFIG_EFI_TEST is not set
|
||||
# CONFIG_EFI_VARS is not set
|
||||
CONFIG_ELF_CORE=y
|
||||
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_EVENT_TRACING=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_FAT_FS=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CFB_COPYAREA=y
|
||||
CONFIG_FB_CFB_FILLRECT=y
|
||||
CONFIG_FB_CFB_IMAGEBLIT=y
|
||||
CONFIG_FB_CMDLINE=y
|
||||
CONFIG_FB_DEFERRED_IO=y
|
||||
CONFIG_FB_EFI=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_FB_MX3=y
|
||||
# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
|
||||
CONFIG_FB_SIMPLE=y
|
||||
CONFIG_FB_SYS_COPYAREA=y
|
||||
CONFIG_FB_SYS_FILLRECT=y
|
||||
CONFIG_FB_SYS_FOPS=y
|
||||
CONFIG_FB_SYS_IMAGEBLIT=y
|
||||
CONFIG_FEC=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIRMWARE_IN_KERNEL=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FMAN_ARM=y
|
||||
# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set
|
||||
# CONFIG_FMAN_P1023 is not set
|
||||
# CONFIG_FMAN_P3040_P4080_P5020 is not set
|
||||
# CONFIG_FMAN_PFC is not set
|
||||
# CONFIG_FMAN_V3H is not set
|
||||
# CONFIG_FMAN_V3L is not set
|
||||
# CONFIG_FONTS is not set
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_SUPPORT=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
|
||||
CONFIG_FREEZER=y
|
||||
CONFIG_FSL_BMAN_CONFIG=y
|
||||
CONFIG_FSL_BMAN_DEBUGFS=y
|
||||
# CONFIG_FSL_BMAN_TEST is not set
|
||||
# CONFIG_FSL_DPAA2_ETH_CEETM is not set
|
||||
# CONFIG_FSL_DPAA_1588 is not set
|
||||
CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
|
||||
# CONFIG_FSL_DPAA_CEETM is not set
|
||||
CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000
|
||||
CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000
|
||||
# CONFIG_FSL_DPAA_DBG_LOOP is not set
|
||||
# CONFIG_FSL_DPAA_ETH_DEBUG is not set
|
||||
CONFIG_FSL_DPAA_ETH_DEBUGFS=y
|
||||
# CONFIG_FSL_DPAA_ETH_JUMBO_FRAME is not set
|
||||
CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
|
||||
CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
|
||||
CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
|
||||
# CONFIG_FSL_DPAA_HOOKS is not set
|
||||
CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
|
||||
CONFIG_FSL_DPAA_OFFLINE_PORTS=y
|
||||
# CONFIG_FSL_DPAA_TS is not set
|
||||
CONFIG_FSL_DPA_CAN_WAIT=y
|
||||
CONFIG_FSL_DPA_CAN_WAIT_SYNC=y
|
||||
# CONFIG_FSL_DPA_CHECKING is not set
|
||||
CONFIG_FSL_DPA_PIRQ_FAST=y
|
||||
CONFIG_FSL_DPA_PIRQ_SLOW=y
|
||||
CONFIG_FSL_DPA_PORTAL_SHARE=y
|
||||
CONFIG_FSL_EDMA=y
|
||||
CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
|
||||
CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
|
||||
CONFIG_FSL_GUTS=y
|
||||
CONFIG_FSL_IFC=y
|
||||
CONFIG_FSL_PPFE=y
|
||||
CONFIG_FSL_PPFE_UTIL_DISABLED=y
|
||||
CONFIG_FSL_PQ_MDIO=y
|
||||
# CONFIG_FSL_QDMA is not set
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3
|
||||
CONFIG_FSL_QMAN_CONFIG=y
|
||||
CONFIG_FSL_QMAN_DEBUGFS=y
|
||||
CONFIG_FSL_QMAN_FQD_SZ=10
|
||||
# CONFIG_FSL_QMAN_FQ_LOOKUP is not set
|
||||
CONFIG_FSL_QMAN_INIT_TIMEOUT=10
|
||||
CONFIG_FSL_QMAN_PFDR_SZ=13
|
||||
CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12
|
||||
CONFIG_FSL_QMAN_PIRQ_IPERIOD=100
|
||||
CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4
|
||||
CONFIG_FSL_QMAN_POLL_LIMIT=32
|
||||
# CONFIG_FSL_QMAN_TEST is not set
|
||||
CONFIG_FSL_SDK_BMAN=y
|
||||
CONFIG_FSL_SDK_DPA=y
|
||||
CONFIG_FSL_SDK_DPAA_ETH=y
|
||||
CONFIG_FSL_SDK_FMAN=y
|
||||
# CONFIG_FSL_SDK_FMAN_TEST is not set
|
||||
CONFIG_FSL_SDK_QMAN=y
|
||||
CONFIG_FSL_USDPAA=y
|
||||
CONFIG_FSL_XGMAC_MDIO=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_FTRACE=y
|
||||
# CONFIG_FTRACE_SYSCALLS is not set
|
||||
CONFIG_FUSE_FS=y
|
||||
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IO=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_PINCTRL_GROUPS=y
|
||||
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_MPC8XXX=y
|
||||
CONFIG_GPIO_MXC=y
|
||||
# CONFIG_GRO_CELLS is not set
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
||||
CONFIG_HAVE_ARCH_BITREVERSE=y
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_HAVE_ARM_ARCH_TIMER=y
|
||||
CONFIG_HAVE_ARM_SMCCC=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CC_STACKPROTECTOR=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_CLK_PREPARE=y
|
||||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_HAVE_EBPF_JIT=y
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_GENERIC_GUP=y
|
||||
CONFIG_HAVE_HW_BREAKPOINT=y
|
||||
CONFIG_HAVE_IDE=y
|
||||
CONFIG_HAVE_IMX_SRC=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_OPROFILE=y
|
||||
CONFIG_HAVE_OPTPROBES=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HAVE_PERF_REGS=y
|
||||
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
||||
CONFIG_HAVE_PROC_CPU=y
|
||||
CONFIG_HAVE_RCU_TABLE_FREE=y
|
||||
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
||||
CONFIG_HAVE_SMP=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_HAVE_UID16=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HDMI=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HIGHPTE=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
# CONFIG_HUGETLBFS is not set
|
||||
CONFIG_HVC_DRIVER=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_IMX_RNGC=y
|
||||
CONFIG_HZ_FIXED=0
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_ALGOBIT=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_DEMUX_PINCTRL=y
|
||||
CONFIG_I2C_DESIGNWARE_CORE=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_IMX=y
|
||||
# CONFIG_I2C_IMX_LPI2C is not set
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_I2C_MUX_PINCTRL=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_I2C_SLAVE=y
|
||||
CONFIG_I2C_SLAVE_EEPROM=y
|
||||
CONFIG_I2C_XILINX=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
CONFIG_ICS932S401=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_IMX2_WDT=y
|
||||
CONFIG_IMX_DMA=y
|
||||
CONFIG_IMX_SDMA=y
|
||||
# CONFIG_IMX_WEIM is not set
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG_DESTROY is not set
|
||||
# CONFIG_INET_RAW_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_JOYDEV=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_IOMMU_HELPER=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
CONFIG_IPC_NS=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_ISDN is not set
|
||||
CONFIG_ISL29003=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KERNEL_GZIP=y
|
||||
# CONFIG_KERNEL_XZ is not set
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
CONFIG_KEYBOARD_BCM=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
# CONFIG_KEYBOARD_IMX is not set
|
||||
CONFIG_KEYS=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=256
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_LOGO_LINUX_CLUT224=y
|
||||
CONFIG_LOGO_LINUX_MONO=y
|
||||
CONFIG_LOGO_LINUX_VGA16=y
|
||||
CONFIG_LS_SCFG_MSI=y
|
||||
# CONFIG_LS_SOC_DRIVERS is not set
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_MCPM=y
|
||||
CONFIG_MDIO_BITBANG=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
# CONFIG_MDIO_FSL_BACKPLANE is not set
|
||||
# CONFIG_MDIO_GPIO is not set
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
# CONFIG_MFD_VEXPRESS_SYSREG is not set
|
||||
CONFIG_MICREL_PHY=y
|
||||
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
||||
CONFIG_MIGHT_HAVE_PCI=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
# CONFIG_MMC_MXC is not set
|
||||
CONFIG_MMC_SDHCI=y
|
||||
# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
|
||||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
||||
CONFIG_MMC_SDHCI_OF_ESDHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
# CONFIG_MMC_TIFM_SD is not set
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_MODULES_USE_ELF_REL=y
|
||||
# CONFIG_MOUSE_BCM5974 is not set
|
||||
# CONFIG_MOUSE_CYAPA is not set
|
||||
CONFIG_MOUSE_ELAN_I2C=y
|
||||
CONFIG_MOUSE_ELAN_I2C_I2C=y
|
||||
# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
|
||||
CONFIG_MOUSE_PS2=y
|
||||
CONFIG_MOUSE_PS2_ALPS=y
|
||||
CONFIG_MOUSE_PS2_BYD=y
|
||||
CONFIG_MOUSE_PS2_CYPRESS=y
|
||||
CONFIG_MOUSE_PS2_ELANTECH=y
|
||||
CONFIG_MOUSE_PS2_FOCALTECH=y
|
||||
CONFIG_MOUSE_PS2_LOGIPS2PP=y
|
||||
CONFIG_MOUSE_PS2_SMBUS=y
|
||||
CONFIG_MOUSE_PS2_SYNAPTICS=y
|
||||
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
|
||||
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
|
||||
CONFIG_MOUSE_PS2_TRACKPOINT=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
CONFIG_MTD_CFI_GEOMETRY=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_DATAFLASH=y
|
||||
# CONFIG_MTD_DATAFLASH_OTP is not set
|
||||
# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384
|
||||
CONFIG_MTD_SST25L=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
# CONFIG_MTD_UBI_BLOCK is not set
|
||||
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MULTI_IRQ_HANDLER=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_MX3_IPU=y
|
||||
CONFIG_MX3_IPU_IRQS=4
|
||||
# CONFIG_MXS_DMA is not set
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_NATIONAL_PHY=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEON=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_NS=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
CONFIG_NOP_TRACER=y
|
||||
CONFIG_NO_BOOTMEM=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=16
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_NVMEM=y
|
||||
# CONFIG_NVMEM_IMX_IIM is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_ADDRESS_PCI=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_PCI=y
|
||||
CONFIG_OF_PCI_IRQ=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OLD_SIGACTION=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_OUTER_CACHE=y
|
||||
CONFIG_OUTER_CACHE_SYNC=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_OFFSET=0xC0000000
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
# CONFIG_PCIEASPM_DEBUG is not set
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_ECAM=y
|
||||
CONFIG_PCI_HOST_COMMON=y
|
||||
CONFIG_PCI_HOST_GENERIC=y
|
||||
CONFIG_PCI_LABEL=y
|
||||
CONFIG_PCI_LAYERSCAPE=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_PERF_USE_VMALLOC=y
|
||||
CONFIG_PGTABLE_LEVELS=3
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PID_NS=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PL310_ERRATA_588369=y
|
||||
CONFIG_PL310_ERRATA_727915=y
|
||||
CONFIG_PL310_ERRATA_753970=y
|
||||
CONFIG_PL310_ERRATA_769419=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_PM_SLEEP=y
|
||||
CONFIG_PM_SLEEP_SMP=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_POSIX_MQUEUE_SYSCTL=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_BRCMKONA=y
|
||||
CONFIG_POWER_RESET_BRCMSTB=y
|
||||
CONFIG_POWER_RESET_GPIO=y
|
||||
CONFIG_POWER_RESET_GPIO_RESTART=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
|
||||
CONFIG_POWER_RESET_VEXPRESS=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PROBE_EVENTS=y
|
||||
CONFIG_PROC_CHILDREN=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_CONSOLE=y
|
||||
# CONFIG_PSTORE_LZ4_COMPRESS is not set
|
||||
# CONFIG_PSTORE_LZO_COMPRESS is not set
|
||||
CONFIG_PSTORE_PMSG=y
|
||||
CONFIG_PSTORE_RAM=y
|
||||
CONFIG_PSTORE_ZLIB_COMPRESS=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
# CONFIG_PTP_1588_CLOCK_DPAA is not set
|
||||
CONFIG_PTP_1588_CLOCK_GIANFAR=y
|
||||
CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
|
||||
CONFIG_QORIQ_CPUFREQ=y
|
||||
# CONFIG_QUICC_ENGINE is not set
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REED_SOLOMON=y
|
||||
CONFIG_REED_SOLOMON_DEC8=y
|
||||
CONFIG_REED_SOLOMON_ENC8=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_SPI=y
|
||||
# CONFIG_RESET_ATTACK_MITIGATION is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RING_BUFFER=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_CMOS is not set
|
||||
CONFIG_RTC_DRV_DS1307=y
|
||||
CONFIG_RTC_DRV_DS3232=y
|
||||
# CONFIG_RTC_DRV_EFI is not set
|
||||
CONFIG_RTC_DRV_EM3027=y
|
||||
# CONFIG_RTC_DRV_IMXDI is not set
|
||||
# CONFIG_RTC_DRV_MXC is not set
|
||||
CONFIG_RTC_DRV_PCF2127=y
|
||||
CONFIG_RTC_DRV_PCF85263=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_SCHED_DEBUG=y
|
||||
# CONFIG_SCHED_INFO is not set
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_EM=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_BCM63XX=y
|
||||
CONFIG_SERIAL_BCM63XX_CONSOLE=y
|
||||
CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
|
||||
CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
|
||||
CONFIG_SERIAL_FSL_LPUART=y
|
||||
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
|
||||
CONFIG_SERIAL_IMX=y
|
||||
CONFIG_SERIAL_IMX_CONSOLE=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_ST_ASC=y
|
||||
CONFIG_SERIAL_ST_ASC_CONSOLE=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIO_SERPORT=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_ON_UP=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
CONFIG_SOCK_DIAG=y
|
||||
CONFIG_SOC_BRCMSTB=y
|
||||
CONFIG_SOC_BUS=y
|
||||
# CONFIG_SOC_IMX50 is not set
|
||||
# CONFIG_SOC_IMX51 is not set
|
||||
# CONFIG_SOC_IMX53 is not set
|
||||
# CONFIG_SOC_IMX6Q is not set
|
||||
# CONFIG_SOC_IMX6SL is not set
|
||||
# CONFIG_SOC_IMX6SX is not set
|
||||
# CONFIG_SOC_IMX6UL is not set
|
||||
# CONFIG_SOC_IMX7D is not set
|
||||
CONFIG_SOC_LS1021A=y
|
||||
# CONFIG_SOC_VF610 is not set
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_CADENCE=y
|
||||
# CONFIG_SPI_FSL_LPSPI is not set
|
||||
CONFIG_SPI_FSL_QUADSPI=y
|
||||
# CONFIG_SPI_IMX is not set
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
CONFIG_SPI_XILINX=y
|
||||
CONFIG_SPMI=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_SQUASHFS_ZLIB=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRAM_EXEC=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKTRACE=y
|
||||
CONFIG_STAGING_BOARD=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
CONFIG_SUSPEND=y
|
||||
CONFIG_SUSPEND_FREEZER=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SWP_EMULATE=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
# CONFIG_THUMB2_KERNEL is not set
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_TOUCHSCREEN_PROPERTIES=y
|
||||
CONFIG_TRACEPOINTS=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACING=y
|
||||
CONFIG_TRACING_EVENTS_GPIO=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UCS2_STRING=y
|
||||
CONFIG_UEVENT_HELPER_PATH=""
|
||||
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_UPROBES=y
|
||||
CONFIG_UPROBE_EVENTS=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
# CONFIG_USERIO is not set
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_USE_OF=y
|
||||
CONFIG_UTS_NS=y
|
||||
CONFIG_VDSO=y
|
||||
CONFIG_VECTORS_BASE=0xffff0000
|
||||
CONFIG_VEXPRESS_CONFIG=y
|
||||
CONFIG_VEXPRESS_SYSCFG=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_VFPv3=y
|
||||
CONFIG_VGA_ARB=y
|
||||
CONFIG_VGA_ARB_MAX_GPUS=16
|
||||
CONFIG_VIDEOMODE_HELPERS=y
|
||||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_PCI_LEGACY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_CONSOLE_SLEEP=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
|
||||
CONFIG_XILINX_WATCHDOG=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_POWERPC=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
CONFIG_XZ_DEC_X86=y
|
||||
CONFIG_ZBOOT_ROM_BSS=0
|
||||
CONFIG_ZBOOT_ROM_TEXT=0
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
991
target/linux/layerscape/armv8_64b/config-4.14
Normal file
991
target/linux/layerscape/armv8_64b/config-4.14
Normal file
@ -0,0 +1,991 @@
|
||||
CONFIG_64BIT=y
|
||||
# CONFIG_ACPI is not set
|
||||
# CONFIG_AHCI_XGENE is not set
|
||||
CONFIG_AQUANTIA_PHY=y
|
||||
CONFIG_ARCH_CLOCKSOURCE_DATA=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
|
||||
CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
|
||||
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
|
||||
CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
|
||||
CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
|
||||
CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
|
||||
CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
|
||||
CONFIG_ARCH_HAS_KCOV=y
|
||||
CONFIG_ARCH_HAS_SET_MEMORY=y
|
||||
CONFIG_ARCH_HAS_SG_CHAIN=y
|
||||
CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
|
||||
CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
|
||||
CONFIG_ARCH_HAS_TICK_BROADCAST=y
|
||||
CONFIG_ARCH_HIBERNATION_HEADER=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_LAYERSCAPE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
|
||||
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
|
||||
CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
|
||||
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
||||
CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
|
||||
CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
|
||||
CONFIG_ARCH_SUPPORTS_UPROBES=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
|
||||
CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
|
||||
CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
||||
CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
|
||||
CONFIG_ARM64=y
|
||||
# CONFIG_ARM64_16K_PAGES is not set
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
# CONFIG_ARM64_64K_PAGES is not set
|
||||
CONFIG_ARM64_CONT_SHIFT=4
|
||||
# CONFIG_ARM64_CRYPTO is not set
|
||||
CONFIG_ARM64_ERRATUM_819472=y
|
||||
CONFIG_ARM64_ERRATUM_824069=y
|
||||
CONFIG_ARM64_ERRATUM_826319=y
|
||||
CONFIG_ARM64_ERRATUM_827319=y
|
||||
CONFIG_ARM64_ERRATUM_832075=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_845719=y
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
# CONFIG_ARM64_LSE_ATOMICS is not set
|
||||
CONFIG_ARM64_MODULE_CMODEL_LARGE=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PAN=y
|
||||
# CONFIG_ARM64_PMEM is not set
|
||||
# CONFIG_ARM64_PTDUMP_CORE is not set
|
||||
# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
|
||||
# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
|
||||
CONFIG_ARM64_SSBD=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_UAO=y
|
||||
CONFIG_ARM64_VA_BITS=48
|
||||
# CONFIG_ARM64_VA_BITS_39 is not set
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_ARM64_VHE=y
|
||||
# CONFIG_ARMV8_DEPRECATED is not set
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
|
||||
CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
# CONFIG_ARM_DT_BL_CPUFREQ is not set
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
|
||||
# CONFIG_ARM_PL172_MPMC is not set
|
||||
CONFIG_ARM_PMU=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
CONFIG_ARM_SP805_WATCHDOG=y
|
||||
CONFIG_ARM_TIMER_SP804=y
|
||||
CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_AUDITSYSCALL=y
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_AUDIT_COMPAT_GENERIC=y
|
||||
CONFIG_AUDIT_GENERIC=y
|
||||
CONFIG_AUDIT_TREE=y
|
||||
CONFIG_AUDIT_WATCH=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_BALLOON_COMPACTION=y
|
||||
CONFIG_BATTERY_BQ27XXX=y
|
||||
# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
|
||||
CONFIG_BATTERY_BQ27XXX_I2C=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_BSGLIB=y
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=16
|
||||
CONFIG_BLK_DEV_RAM_SIZE=262144
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_MQ_VIRTIO=y
|
||||
CONFIG_BLK_SCSI_REQUEST=y
|
||||
CONFIG_BLOCK_COMPAT=y
|
||||
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
|
||||
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
|
||||
CONFIG_BOUNCE=y
|
||||
CONFIG_BPF_JIT=y
|
||||
# CONFIG_BPF_SYSCALL is not set
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_BTRFS_FS=y
|
||||
# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
|
||||
CONFIG_BTRFS_FS_POSIX_ACL=y
|
||||
CONFIG_BUILD_BIN2C=y
|
||||
CONFIG_CAVIUM_ERRATUM_22375=y
|
||||
CONFIG_CAVIUM_ERRATUM_23144=y
|
||||
CONFIG_CAVIUM_ERRATUM_23154=y
|
||||
CONFIG_CAVIUM_ERRATUM_27456=y
|
||||
CONFIG_CHECKPOINT_RESTORE=y
|
||||
CONFIG_CHROME_PLATFORMS=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLK_QORIQ=y
|
||||
CONFIG_CLK_SP810=y
|
||||
CONFIG_CLK_VEXPRESS_OSC=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=16
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_CS2000_CP=y
|
||||
CONFIG_COMMON_CLK_VERSATILE=y
|
||||
CONFIG_COMMON_CLK_XGENE=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_COMPAT_BINFMT_ELF=y
|
||||
CONFIG_COMPAT_NETLINK_MESSAGES=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_COREDUMP=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
# CONFIG_CPU_BIG_ENDIAN is not set
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
CONFIG_CPU_FREQ_GOV_COMMON=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
|
||||
CONFIG_CPU_IDLE=y
|
||||
# CONFIG_CPU_IDLE_GOV_LADDER is not set
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CRC7=y
|
||||
CONFIG_CRC_ITU_T=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_ACOMP2=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRCT10DIF=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
# CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC is not set
|
||||
# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_HW=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
# CONFIG_CRYPTO_TLS is not set
|
||||
CONFIG_CRYPTO_WORKQUEUE=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEBUG_EFI is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_DEBUG_INFO_REDUCED is not set
|
||||
CONFIG_DEBUG_MEMORY_INIT=y
|
||||
CONFIG_DECOMPRESS_BZIP2=y
|
||||
CONFIG_DECOMPRESS_GZIP=y
|
||||
CONFIG_DECOMPRESS_LZMA=y
|
||||
CONFIG_DECOMPRESS_LZO=y
|
||||
CONFIG_DECOMPRESS_XZ=y
|
||||
CONFIG_DEFAULT_CFQ=y
|
||||
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
|
||||
CONFIG_DEFAULT_IOSCHED="cfq"
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEVMEM=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMATEST=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_ENGINE_RAID=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
||||
CONFIG_DMI=y
|
||||
CONFIG_DMIID=y
|
||||
# CONFIG_DMI_SYSFS is not set
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EFI=y
|
||||
CONFIG_EFIVAR_FS=y
|
||||
CONFIG_EFI_ARMSTUB=y
|
||||
# CONFIG_EFI_CAPSULE_LOADER is not set
|
||||
CONFIG_EFI_ESRT=y
|
||||
CONFIG_EFI_PARAMS_FROM_FDT=y
|
||||
CONFIG_EFI_RUNTIME_WRAPPERS=y
|
||||
CONFIG_EFI_STUB=y
|
||||
# CONFIG_EFI_TEST is not set
|
||||
# CONFIG_EFI_VARS is not set
|
||||
CONFIG_ELF_CORE=y
|
||||
# CONFIG_EMBEDDED is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
# CONFIG_EXT2_FS_SECURITY is not set
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
# CONFIG_EXT3_FS_SECURITY is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_EXTCON_USB_GPIO=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FAT_FS=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_ARMCLCD=y
|
||||
CONFIG_FB_CFB_COPYAREA=y
|
||||
CONFIG_FB_CFB_FILLRECT=y
|
||||
CONFIG_FB_CFB_IMAGEBLIT=y
|
||||
CONFIG_FB_CMDLINE=y
|
||||
CONFIG_FB_DEFERRED_IO=y
|
||||
# CONFIG_FB_EFI is not set
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
# CONFIG_FB_PROVIDE_GET_FB_UNMAPPED_AREA is not set
|
||||
CONFIG_FB_SYS_COPYAREA=y
|
||||
CONFIG_FB_SYS_FILLRECT=y
|
||||
CONFIG_FB_SYS_FOPS=y
|
||||
CONFIG_FB_SYS_IMAGEBLIT=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIRMWARE_IN_KERNEL=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FMAN_ARM=y
|
||||
# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set
|
||||
# CONFIG_FMAN_P1023 is not set
|
||||
# CONFIG_FMAN_P3040_P4080_P5020 is not set
|
||||
# CONFIG_FMAN_PFC is not set
|
||||
# CONFIG_FMAN_V3H is not set
|
||||
# CONFIG_FMAN_V3L is not set
|
||||
# CONFIG_FONTS is not set
|
||||
CONFIG_FONT_8x16=y
|
||||
CONFIG_FONT_8x8=y
|
||||
CONFIG_FONT_SUPPORT=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
|
||||
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
CONFIG_FREEZER=y
|
||||
CONFIG_FSL_BMAN_CONFIG=y
|
||||
CONFIG_FSL_BMAN_DEBUGFS=y
|
||||
# CONFIG_FSL_BMAN_TEST is not set
|
||||
# CONFIG_FSL_DPAA is not set
|
||||
CONFIG_FSL_DPAA2=y
|
||||
CONFIG_FSL_DPAA2_ETH=y
|
||||
CONFIG_FSL_DPAA2_ETHSW=y
|
||||
# CONFIG_FSL_DPAA2_ETH_CEETM is not set
|
||||
# CONFIG_FSL_DPAA2_ETH_DEBUGFS is not set
|
||||
# CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE is not set
|
||||
CONFIG_FSL_DPAA2_EVB=y
|
||||
CONFIG_FSL_DPAA2_MAC=y
|
||||
# CONFIG_FSL_DPAA2_MAC_NETDEVS is not set
|
||||
# CONFIG_FSL_DPAA2_QDMA is not set
|
||||
# CONFIG_FSL_DPAA_1588 is not set
|
||||
CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
|
||||
# CONFIG_FSL_DPAA_CEETM is not set
|
||||
CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000
|
||||
CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000
|
||||
# CONFIG_FSL_DPAA_DBG_LOOP is not set
|
||||
# CONFIG_FSL_DPAA_ETH_DEBUG is not set
|
||||
CONFIG_FSL_DPAA_ETH_DEBUGFS=y
|
||||
# CONFIG_FSL_DPAA_ETH_JUMBO_FRAME is not set
|
||||
CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
|
||||
CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
|
||||
CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
|
||||
# CONFIG_FSL_DPAA_HOOKS is not set
|
||||
CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
|
||||
CONFIG_FSL_DPAA_OFFLINE_PORTS=y
|
||||
# CONFIG_FSL_DPAA_TS is not set
|
||||
CONFIG_FSL_DPA_CAN_WAIT=y
|
||||
CONFIG_FSL_DPA_CAN_WAIT_SYNC=y
|
||||
# CONFIG_FSL_DPA_CHECKING is not set
|
||||
CONFIG_FSL_DPA_PIRQ_FAST=y
|
||||
CONFIG_FSL_DPA_PIRQ_SLOW=y
|
||||
CONFIG_FSL_DPA_PORTAL_SHARE=y
|
||||
CONFIG_FSL_EDMA=y
|
||||
CONFIG_FSL_ERRATUM_A008585=y
|
||||
# CONFIG_FSL_FMAN is not set
|
||||
CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
|
||||
CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
|
||||
CONFIG_FSL_GUTS=y
|
||||
CONFIG_FSL_IFC=y
|
||||
CONFIG_FSL_LS2_CONSOLE=y
|
||||
CONFIG_FSL_MC_BUS=y
|
||||
CONFIG_FSL_MC_DPIO=y
|
||||
CONFIG_FSL_MC_RESTOOL=y
|
||||
CONFIG_FSL_PPFE=y
|
||||
CONFIG_FSL_PPFE_UTIL_DISABLED=y
|
||||
# CONFIG_FSL_QBMAN_DEBUG is not set
|
||||
# CONFIG_FSL_QDMA is not set
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
|
||||
CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3
|
||||
CONFIG_FSL_QMAN_CONFIG=y
|
||||
CONFIG_FSL_QMAN_DEBUGFS=y
|
||||
CONFIG_FSL_QMAN_FQD_SZ=10
|
||||
CONFIG_FSL_QMAN_FQ_LOOKUP=y
|
||||
CONFIG_FSL_QMAN_INIT_TIMEOUT=10
|
||||
CONFIG_FSL_QMAN_PFDR_SZ=13
|
||||
CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12
|
||||
CONFIG_FSL_QMAN_PIRQ_IPERIOD=100
|
||||
CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4
|
||||
CONFIG_FSL_QMAN_POLL_LIMIT=32
|
||||
# CONFIG_FSL_QMAN_TEST is not set
|
||||
CONFIG_FSL_SDK_BMAN=y
|
||||
CONFIG_FSL_SDK_DPA=y
|
||||
CONFIG_FSL_SDK_DPAA_ETH=y
|
||||
CONFIG_FSL_SDK_FMAN=y
|
||||
# CONFIG_FSL_SDK_FMAN_TEST is not set
|
||||
CONFIG_FSL_SDK_QMAN=y
|
||||
CONFIG_FSL_USDPAA=y
|
||||
CONFIG_FSL_XGMAC_MDIO=y
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_FTM_ALARM=y
|
||||
CONFIG_FUSE_FS=y
|
||||
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
|
||||
CONFIG_GARP=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IO=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
# CONFIG_GIANFAR is not set
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_MPC8XXX=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_GRO_CELLS is not set
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
|
||||
CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
||||
CONFIG_HAVE_ARCH_BITREVERSE=y
|
||||
CONFIG_HAVE_ARCH_HUGE_VMAP=y
|
||||
CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
||||
CONFIG_HAVE_ARCH_KASAN=y
|
||||
CONFIG_HAVE_ARCH_KGDB=y
|
||||
CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
|
||||
CONFIG_HAVE_ARCH_PFN_VALID=y
|
||||
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
||||
CONFIG_HAVE_ARCH_TRACEHOOK=y
|
||||
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_HAVE_ARCH_VMAP_STACK=y
|
||||
CONFIG_HAVE_ARM_SMCCC=y
|
||||
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
|
||||
CONFIG_HAVE_CC_STACKPROTECTOR=y
|
||||
CONFIG_HAVE_CLK=y
|
||||
CONFIG_HAVE_CLK_PREPARE=y
|
||||
CONFIG_HAVE_CMPXCHG_DOUBLE=y
|
||||
CONFIG_HAVE_CMPXCHG_LOCAL=y
|
||||
CONFIG_HAVE_CONTEXT_TRACKING=y
|
||||
CONFIG_HAVE_C_RECORDMCOUNT=y
|
||||
CONFIG_HAVE_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
||||
CONFIG_HAVE_DMA_API_DEBUG=y
|
||||
CONFIG_HAVE_DMA_CONTIGUOUS=y
|
||||
CONFIG_HAVE_DYNAMIC_FTRACE=y
|
||||
CONFIG_HAVE_EBPF_JIT=y
|
||||
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
||||
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
||||
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
||||
CONFIG_HAVE_GENERIC_GUP=y
|
||||
CONFIG_HAVE_HW_BREAKPOINT=y
|
||||
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_HAVE_MEMBLOCK=y
|
||||
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
|
||||
CONFIG_HAVE_MEMORY_PRESENT=y
|
||||
CONFIG_HAVE_NET_DSA=y
|
||||
CONFIG_HAVE_PATA_PLATFORM=y
|
||||
CONFIG_HAVE_PERF_EVENTS=y
|
||||
CONFIG_HAVE_PERF_REGS=y
|
||||
CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
||||
CONFIG_HAVE_RCU_TABLE_FREE=y
|
||||
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
||||
CONFIG_HAVE_SETUP_PER_CPU_AREA=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_HAVE_UID16=y
|
||||
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
||||
CONFIG_HIBERNATE_CALLBACKS=y
|
||||
CONFIG_HIBERNATION=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HID_KENSINGTON=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
CONFIG_HOLES_IN_ZONE=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_HVC_DRIVER=y
|
||||
CONFIG_HVC_IRQ=y
|
||||
CONFIG_HVC_XEN=y
|
||||
CONFIG_HVC_XEN_FRONTEND=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HZ=250
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_DESIGNWARE_CORE=y
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
# CONFIG_I2C_DESIGNWARE_SLAVE is not set
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_IMX=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_I2C_SLAVE=y
|
||||
# CONFIG_I2C_SLAVE_EEPROM is not set
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_IMX2_WDT=y
|
||||
CONFIG_INET_DIAG=y
|
||||
# CONFIG_INET_DIAG_DESTROY is not set
|
||||
# CONFIG_INET_RAW_DIAG is not set
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_MOUSE=y
|
||||
CONFIG_INPUT_MOUSEDEV=y
|
||||
CONFIG_INPUT_MOUSEDEV_PSAUX=y
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
|
||||
CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
|
||||
CONFIG_IOMMU_API=y
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_HELPER=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
CONFIG_IOSCHED_CFQ=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_IPC_NS=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_BYPASS_MANAGER=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
# CONFIG_ISDN is not set
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEYBOARD_ATKBD=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_LOGO_LINUX_CLUT224=y
|
||||
# CONFIG_LOGO_LINUX_MONO is not set
|
||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
||||
CONFIG_LS_SCFG_MSI=y
|
||||
CONFIG_LS_SOC_DRIVERS=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_MDIO_BITBANG=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
# CONFIG_MDIO_FSL_BACKPLANE is not set
|
||||
# CONFIG_MDIO_GPIO is not set
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_MEMORY_BALLOON=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MEMTEST=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
# CONFIG_MFD_VEXPRESS_SYSREG is not set
|
||||
CONFIG_MICREL_PHY=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
|
||||
CONFIG_MMC_SDHCI_OF_ESDHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
# CONFIG_MMC_TIFM_SD is not set
|
||||
CONFIG_MMU_NOTIFIER=y
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_MOUSE_BCM5974 is not set
|
||||
# CONFIG_MOUSE_CYAPA is not set
|
||||
CONFIG_MOUSE_PS2=y
|
||||
CONFIG_MOUSE_PS2_ALPS=y
|
||||
CONFIG_MOUSE_PS2_BYD=y
|
||||
CONFIG_MOUSE_PS2_CYPRESS=y
|
||||
# CONFIG_MOUSE_PS2_ELANTECH is not set
|
||||
CONFIG_MOUSE_PS2_FOCALTECH=y
|
||||
CONFIG_MOUSE_PS2_LOGIPS2PP=y
|
||||
CONFIG_MOUSE_PS2_SMBUS=y
|
||||
CONFIG_MOUSE_PS2_SYNAPTICS=y
|
||||
CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
|
||||
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
|
||||
CONFIG_MOUSE_PS2_TRACKPOINT=y
|
||||
# CONFIG_MOUSE_SERIAL is not set
|
||||
# CONFIG_MOUSE_VSXXXAA is not set
|
||||
CONFIG_MRP=y
|
||||
CONFIG_MTD_CFI_ADV_OPTIONS=y
|
||||
# CONFIG_MTD_CFI_GEOMETRY is not set
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_DATAFLASH=y
|
||||
# CONFIG_MTD_DATAFLASH_OTP is not set
|
||||
# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=16384
|
||||
CONFIG_MTD_SST25L=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
# CONFIG_MTD_UBI_BLOCK is not set
|
||||
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_MV_XOR_V2=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_MULTIPLE_NODES=y
|
||||
CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
# CONFIG_NET_CADENCE is not set
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_NS=y
|
||||
CONFIG_NET_PTP_CLASSIFY=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NODES_SHIFT=2
|
||||
CONFIG_NO_BOOTMEM=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=64
|
||||
CONFIG_NUMA=y
|
||||
CONFIG_NUMA_BALANCING=y
|
||||
CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_ADDRESS_PCI=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_NUMA=y
|
||||
CONFIG_OF_PCI=y
|
||||
CONFIG_OF_PCI_IRQ=y
|
||||
CONFIG_OF_RESERVED_MEM=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_PADATA=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
CONFIG_PARAVIRT=y
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
# CONFIG_PCIEASPM_DEBUG is not set
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCI_ATS=y
|
||||
CONFIG_PCI_BUS_ADDR_T_64BIT=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_ECAM=y
|
||||
CONFIG_PCI_HISI=y
|
||||
CONFIG_PCI_HOST_COMMON=y
|
||||
CONFIG_PCI_HOST_GENERIC=y
|
||||
CONFIG_PCI_IOV=y
|
||||
CONFIG_PCI_LABEL=y
|
||||
CONFIG_PCI_LAYERSCAPE=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_PID_IN_CONTEXTIDR=y
|
||||
CONFIG_PID_NS=y
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
# CONFIG_PM_DEBUG is not set
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_PM_SLEEP=y
|
||||
CONFIG_PM_SLEEP_SMP=y
|
||||
CONFIG_PM_STD_PARTITION=""
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_POSIX_MQUEUE_SYSCTL=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_POWER_RESET_VEXPRESS=y
|
||||
CONFIG_POWER_RESET_XGENE=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_PPS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PRINT_QUOTA_WARNING=y
|
||||
CONFIG_PROC_CHILDREN=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_PTP_1588_CLOCK=y
|
||||
# CONFIG_PTP_1588_CLOCK_DPAA is not set
|
||||
CONFIG_PTP_1588_CLOCK_DPAA2=y
|
||||
CONFIG_QCOM_HIDMA=y
|
||||
CONFIG_QCOM_HIDMA_MGMT=y
|
||||
CONFIG_QCOM_QDF2400_ERRATUM_0065=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
|
||||
CONFIG_QORIQ_CPUFREQ=y
|
||||
# CONFIG_QUICC_ENGINE is not set
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RADIX_TREE_MULTIORDER=y
|
||||
CONFIG_RAID6_PQ=y
|
||||
# CONFIG_RANDOMIZE_BASE is not set
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RD_BZIP2=y
|
||||
CONFIG_RD_GZIP=y
|
||||
CONFIG_RD_LZMA=y
|
||||
CONFIG_RD_LZO=y
|
||||
CONFIG_RD_XZ=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGMAP_SPI=y
|
||||
# CONFIG_RESET_ATTACK_MITIGATION is not set
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_DS1307=y
|
||||
CONFIG_RTC_DRV_DS3232=y
|
||||
CONFIG_RTC_DRV_EFI=y
|
||||
CONFIG_RTC_DRV_PCF2127=y
|
||||
CONFIG_RTC_DRV_PCF85263=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
||||
CONFIG_SCHED_INFO=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
# CONFIG_SCSI_SAS_ATA is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_SECCOMP_FILTER=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_FSL_LPUART=y
|
||||
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_SLUB is not set
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_DIAG=y
|
||||
CONFIG_SOC_BUS=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_MANUAL=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_FSL_DSPI=y
|
||||
CONFIG_SPI_FSL_QUADSPI=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_SPMI=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
# CONFIG_SQUASHFS_XZ is not set
|
||||
CONFIG_SQUASHFS_ZLIB=y
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
CONFIG_SUSPEND=y
|
||||
CONFIG_SUSPEND_FREEZER=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWIOTLB_XEN=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
CONFIG_SYS_HYPERVISOR=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
CONFIG_TASKSTATS=y
|
||||
CONFIG_TASKS_RCU=y
|
||||
CONFIG_TASK_DELAY_ACCT=y
|
||||
CONFIG_TASK_IO_ACCOUNTING=y
|
||||
CONFIG_TASK_XACCT=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UCS2_STRING=y
|
||||
CONFIG_UIO=y
|
||||
CONFIG_UIO_AEC=y
|
||||
CONFIG_UIO_CIF=y
|
||||
CONFIG_UIO_DMEM_GENIRQ=y
|
||||
CONFIG_UIO_MF624=y
|
||||
CONFIG_UIO_NETX=y
|
||||
CONFIG_UIO_PCI_GENERIC=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
# CONFIG_UIO_PRUSS is not set
|
||||
CONFIG_UIO_SERCOS3=y
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
# CONFIG_USERIO is not set
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_USE_PERCPU_NUMA_NODE_ID=y
|
||||
CONFIG_UTS_NS=y
|
||||
CONFIG_VEXPRESS_CONFIG=y
|
||||
CONFIG_VEXPRESS_SYSCFG=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_VFIO=y
|
||||
CONFIG_VFIO_FSL_MC=y
|
||||
CONFIG_VFIO_IOMMU_TYPE1=y
|
||||
# CONFIG_VFIO_MDEV is not set
|
||||
# CONFIG_VFIO_NOIOMMU is not set
|
||||
CONFIG_VFIO_PCI=y
|
||||
CONFIG_VFIO_PCI_INTX=y
|
||||
CONFIG_VFIO_PCI_MMAP=y
|
||||
# CONFIG_VFIO_PLATFORM is not set
|
||||
CONFIG_VFIO_VIRQFD=y
|
||||
CONFIG_VGA_ARB=y
|
||||
CONFIG_VGA_ARB_MAX_GPUS=16
|
||||
CONFIG_VIDEOMODE_HELPERS=y
|
||||
CONFIG_VIRTIO=y
|
||||
CONFIG_VIRTIO_BALLOON=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_PCI_LEGACY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q_MVRP=y
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_CONSOLE_SLEEP=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
|
||||
CONFIG_XEN=y
|
||||
CONFIG_XENFS=y
|
||||
CONFIG_XEN_AUTO_XLATE=y
|
||||
CONFIG_XEN_BACKEND=y
|
||||
CONFIG_XEN_BALLOON=y
|
||||
# CONFIG_XEN_BLKDEV_BACKEND is not set
|
||||
CONFIG_XEN_BLKDEV_FRONTEND=y
|
||||
CONFIG_XEN_COMPAT_XENFS=y
|
||||
CONFIG_XEN_DEV_EVTCHN=y
|
||||
CONFIG_XEN_DOM0=y
|
||||
CONFIG_XEN_EFI=y
|
||||
CONFIG_XEN_FBDEV_FRONTEND=y
|
||||
CONFIG_XEN_GNTDEV=y
|
||||
CONFIG_XEN_GRANT_DEV_ALLOC=y
|
||||
# CONFIG_XEN_NETDEV_BACKEND is not set
|
||||
CONFIG_XEN_NETDEV_FRONTEND=y
|
||||
CONFIG_XEN_PRIVCMD=y
|
||||
# CONFIG_XEN_PVCALLS_BACKEND is not set
|
||||
CONFIG_XEN_SCRUB_PAGES=y
|
||||
# CONFIG_XEN_SCSI_FRONTEND is not set
|
||||
CONFIG_XEN_SYS_HYPERVISOR=y
|
||||
# CONFIG_XEN_WDT is not set
|
||||
CONFIG_XEN_XENBUS_FRONTEND=y
|
||||
CONFIG_XFS_FS=y
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_XFS_RT=y
|
||||
CONFIG_XOR_BLOCKS=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_XZ_DEC_IA64=y
|
||||
CONFIG_XZ_DEC_POWERPC=y
|
||||
CONFIG_XZ_DEC_SPARC=y
|
||||
CONFIG_XZ_DEC_X86=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZSTD_COMPRESS=y
|
||||
CONFIG_ZSTD_DECOMPRESS=y
|
||||
@ -0,0 +1,301 @@
|
||||
From 0bafdb711c1a61fbe5bb5b4d4bb5e32425d95a72 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Fri, 16 Nov 2018 15:36:03 +0800
|
||||
Subject: [PATCH] config: support layerscape
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This is an integrated patch of config for layerscape
|
||||
|
||||
Signed-off-by: Alison Wang <alison.wang@nxp.com>
|
||||
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
|
||||
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
|
||||
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
|
||||
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
|
||||
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
|
||||
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
|
||||
Signed-off-by: Li Yang <leoyang.li@nxp.com>
|
||||
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
|
||||
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
|
||||
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
|
||||
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
||||
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/irqchip/Makefile | 1 +
|
||||
drivers/net/ethernet/freescale/Kconfig | 14 ++++----
|
||||
drivers/net/ethernet/freescale/Makefile | 3 ++
|
||||
drivers/ptp/Kconfig | 29 +++++++++++++++++
|
||||
drivers/soc/Kconfig | 1 +
|
||||
drivers/soc/fsl/Kconfig | 11 +++++++
|
||||
drivers/soc/fsl/Kconfig.arm | 16 +++++++++
|
||||
drivers/soc/fsl/Makefile | 3 ++
|
||||
drivers/soc/fsl/layerscape/Kconfig | 10 ++++++
|
||||
drivers/soc/fsl/layerscape/Makefile | 1 +
|
||||
drivers/staging/Kconfig | 4 +++
|
||||
drivers/staging/Makefile | 2 ++
|
||||
drivers/staging/fsl-dpaa2/Kconfig | 43 ++++++++++++++++++++++++-
|
||||
drivers/staging/fsl-dpaa2/Makefile | 4 +++
|
||||
14 files changed, 135 insertions(+), 7 deletions(-)
|
||||
create mode 100644 drivers/soc/fsl/Kconfig.arm
|
||||
create mode 100644 drivers/soc/fsl/layerscape/Kconfig
|
||||
create mode 100644 drivers/soc/fsl/layerscape/Makefile
|
||||
|
||||
--- a/drivers/irqchip/Makefile
|
||||
+++ b/drivers/irqchip/Makefile
|
||||
@@ -80,3 +80,4 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed
|
||||
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
|
||||
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
|
||||
obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
|
||||
+obj-$(CONFIG_QUICC_ENGINE) += irq-qeic.o
|
||||
--- a/drivers/net/ethernet/freescale/Kconfig
|
||||
+++ b/drivers/net/ethernet/freescale/Kconfig
|
||||
@@ -5,10 +5,11 @@
|
||||
config NET_VENDOR_FREESCALE
|
||||
bool "Freescale devices"
|
||||
default y
|
||||
- depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
|
||||
- M523x || M527x || M5272 || M528x || M520x || M532x || \
|
||||
- ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM) || \
|
||||
- ARCH_LAYERSCAPE || COMPILE_TEST
|
||||
+ depends on FSL_SOC || (QUICC_ENGINE && PPC32) || CPM1 || CPM2 || \
|
||||
+ PPC_MPC512x || M523x || M527x || M5272 || M528x || M520x || \
|
||||
+ M532x || ARCH_MXC || ARCH_MXS || \
|
||||
+ (PPC_MPC52xx && PPC_BESTCOMM) || ARCH_LAYERSCAPE || \
|
||||
+ COMPILE_TEST
|
||||
---help---
|
||||
If you have a network (Ethernet) card belonging to this class, say Y.
|
||||
|
||||
@@ -73,7 +74,7 @@ config FSL_XGMAC_MDIO
|
||||
|
||||
config UCC_GETH
|
||||
tristate "Freescale QE Gigabit Ethernet"
|
||||
- depends on QUICC_ENGINE
|
||||
+ depends on QUICC_ENGINE && FSL_SOC && PPC32
|
||||
select FSL_PQ_MDIO
|
||||
select PHYLIB
|
||||
---help---
|
||||
@@ -94,7 +95,8 @@ config GIANFAR
|
||||
This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx,
|
||||
and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
|
||||
on the 8540.
|
||||
-
|
||||
+source "drivers/net/ethernet/freescale/sdk_fman/Kconfig"
|
||||
+source "drivers/net/ethernet/freescale/sdk_dpaa/Kconfig"
|
||||
source "drivers/net/ethernet/freescale/dpaa/Kconfig"
|
||||
|
||||
endif # NET_VENDOR_FREESCALE
|
||||
--- a/drivers/net/ethernet/freescale/Makefile
|
||||
+++ b/drivers/net/ethernet/freescale/Makefile
|
||||
@@ -20,5 +20,8 @@ gianfar_driver-objs := gianfar.o \
|
||||
obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
|
||||
ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
|
||||
|
||||
+obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/
|
||||
+obj-$(if $(CONFIG_FSL_SDK_DPAA_ETH),y) += sdk_dpaa/
|
||||
+
|
||||
obj-$(CONFIG_FSL_FMAN) += fman/
|
||||
obj-$(CONFIG_FSL_DPAA_ETH) += dpaa/
|
||||
--- a/drivers/ptp/Kconfig
|
||||
+++ b/drivers/ptp/Kconfig
|
||||
@@ -55,6 +55,35 @@ config PTP_1588_CLOCK_GIANFAR
|
||||
To compile this driver as a module, choose M here: the module
|
||||
will be called gianfar_ptp.
|
||||
|
||||
+config PTP_1588_CLOCK_DPAA
|
||||
+ tristate "Freescale DPAA as PTP clock"
|
||||
+ depends on FSL_SDK_DPAA_ETH
|
||||
+ select PTP_1588_CLOCK
|
||||
+ select FSL_DPAA_TS
|
||||
+ default n
|
||||
+ help
|
||||
+ This driver adds support for using the DPAA 1588 timer module
|
||||
+ as a PTP clock. This clock is only useful if your PTP programs are
|
||||
+ getting hardware time stamps on the PTP Ethernet packets
|
||||
+ using the SO_TIMESTAMPING API.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the module
|
||||
+ will be called dpaa_ptp.
|
||||
+
|
||||
+config PTP_1588_CLOCK_DPAA2
|
||||
+ tristate "Freescale DPAA2 as PTP clock"
|
||||
+ depends on FSL_DPAA2_ETH
|
||||
+ select PTP_1588_CLOCK
|
||||
+ default y
|
||||
+ help
|
||||
+ This driver adds support for using the DPAA2 1588 timer module
|
||||
+ as a PTP clock. This clock is only useful if your PTP programs are
|
||||
+ getting hardware time stamps on the PTP Ethernet packets
|
||||
+ using the SO_TIMESTAMPING API.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the module
|
||||
+ will be called dpaa2-rtc.
|
||||
+
|
||||
config PTP_1588_CLOCK_IXP46X
|
||||
tristate "Intel IXP46x as PTP clock"
|
||||
depends on IXP4XX_ETH
|
||||
--- a/drivers/soc/Kconfig
|
||||
+++ b/drivers/soc/Kconfig
|
||||
@@ -5,6 +5,7 @@ source "drivers/soc/amlogic/Kconfig"
|
||||
source "drivers/soc/atmel/Kconfig"
|
||||
source "drivers/soc/bcm/Kconfig"
|
||||
source "drivers/soc/fsl/Kconfig"
|
||||
+source "drivers/soc/fsl/ls2-console/Kconfig"
|
||||
source "drivers/soc/imx/Kconfig"
|
||||
source "drivers/soc/mediatek/Kconfig"
|
||||
source "drivers/soc/qcom/Kconfig"
|
||||
--- a/drivers/soc/fsl/Kconfig
|
||||
+++ b/drivers/soc/fsl/Kconfig
|
||||
@@ -16,3 +16,14 @@ config FSL_GUTS
|
||||
Initially only reading SVR and registering soc device are supported.
|
||||
Other guts accesses, such as reading RCW, should eventually be moved
|
||||
into this driver as well.
|
||||
+
|
||||
+config FSL_SLEEP_FSM
|
||||
+ bool
|
||||
+ help
|
||||
+ This driver configures a hardware FSM (Finite State Machine) for deep sleep.
|
||||
+ The FSM is used to finish clean-ups at the last stage of system entering deep
|
||||
+ sleep, and also wakes up system when a wake up event happens.
|
||||
+
|
||||
+if ARM || ARM64
|
||||
+source "drivers/soc/fsl/Kconfig.arm"
|
||||
+endif
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/Kconfig.arm
|
||||
@@ -0,0 +1,16 @@
|
||||
+#
|
||||
+# Freescale ARM SOC Drivers
|
||||
+#
|
||||
+
|
||||
+config LS_SOC_DRIVERS
|
||||
+ bool "Layerscape Soc Drivers"
|
||||
+ depends on ARCH_LAYERSCAPE || SOC_LS1021A
|
||||
+ default n
|
||||
+ help
|
||||
+ Say y here to enable Freescale Layerscape Soc Device Drivers support.
|
||||
+ The Soc Drivers provides the device driver that is a specific block
|
||||
+ or feature on Layerscape platform.
|
||||
+
|
||||
+if LS_SOC_DRIVERS
|
||||
+ source "drivers/soc/fsl/layerscape/Kconfig"
|
||||
+endif
|
||||
--- a/drivers/soc/fsl/Makefile
|
||||
+++ b/drivers/soc/fsl/Makefile
|
||||
@@ -6,3 +6,6 @@ obj-$(CONFIG_FSL_DPAA) +
|
||||
obj-$(CONFIG_QUICC_ENGINE) += qe/
|
||||
obj-$(CONFIG_CPM) += qe/
|
||||
obj-$(CONFIG_FSL_GUTS) += guts.o
|
||||
+obj-$(CONFIG_FSL_LS2_CONSOLE) += ls2-console/
|
||||
+obj-$(CONFIG_LS_SOC_DRIVERS) += layerscape/
|
||||
+obj-$(CONFIG_FSL_SLEEP_FSM) += sleep_fsm.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/layerscape/Kconfig
|
||||
@@ -0,0 +1,10 @@
|
||||
+#
|
||||
+# Layerscape Soc drivers
|
||||
+#
|
||||
+config FTM_ALARM
|
||||
+ bool "FTM alarm driver"
|
||||
+ default n
|
||||
+ help
|
||||
+ Say y here to enable FTM alarm support. The FTM alarm provides
|
||||
+ alarm functions for wakeup system from deep sleep. There is only
|
||||
+ one FTM can be used in ALARM(FTM 0).
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/layerscape/Makefile
|
||||
@@ -0,0 +1 @@
|
||||
+obj-$(CONFIG_FTM_ALARM) += ftm_alarm.o
|
||||
--- a/drivers/staging/Kconfig
|
||||
+++ b/drivers/staging/Kconfig
|
||||
@@ -118,4 +118,8 @@ source "drivers/staging/vboxvideo/Kconfi
|
||||
|
||||
source "drivers/staging/pi433/Kconfig"
|
||||
|
||||
+source "drivers/staging/fsl_qbman/Kconfig"
|
||||
+
|
||||
+source "drivers/staging/fsl_ppfe/Kconfig"
|
||||
+
|
||||
endif # STAGING
|
||||
--- a/drivers/staging/Makefile
|
||||
+++ b/drivers/staging/Makefile
|
||||
@@ -50,3 +50,5 @@ obj-$(CONFIG_BCM2835_VCHIQ) += vc04_serv
|
||||
obj-$(CONFIG_CRYPTO_DEV_CCREE) += ccree/
|
||||
obj-$(CONFIG_DRM_VBOXVIDEO) += vboxvideo/
|
||||
obj-$(CONFIG_PI433) += pi433/
|
||||
+obj-$(CONFIG_FSL_SDK_DPA) += fsl_qbman/
|
||||
+obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/
|
||||
--- a/drivers/staging/fsl-dpaa2/Kconfig
|
||||
+++ b/drivers/staging/fsl-dpaa2/Kconfig
|
||||
@@ -4,7 +4,7 @@
|
||||
|
||||
config FSL_DPAA2
|
||||
bool "Freescale DPAA2 devices"
|
||||
- depends on FSL_MC_BUS && ARCH_LAYERSCAPE
|
||||
+ depends on FSL_MC_BUS
|
||||
---help---
|
||||
Build drivers for Freescale DataPath Acceleration
|
||||
Architecture (DPAA2) family of SoCs.
|
||||
@@ -16,3 +16,44 @@ config FSL_DPAA2_ETH
|
||||
---help---
|
||||
Ethernet driver for Freescale DPAA2 SoCs, using the
|
||||
Freescale MC bus driver
|
||||
+
|
||||
+if FSL_DPAA2_ETH
|
||||
+config FSL_DPAA2_ETH_USE_ERR_QUEUE
|
||||
+ bool "Enable Rx error queue"
|
||||
+ default n
|
||||
+ ---help---
|
||||
+ Allow Rx error frames to be enqueued on an error queue
|
||||
+ and processed by the driver (by default they are dropped
|
||||
+ in hardware).
|
||||
+ This may impact performance, recommended for debugging
|
||||
+ purposes only.
|
||||
+
|
||||
+# QBMAN_DEBUG requires some additional DPIO APIs
|
||||
+config FSL_DPAA2_ETH_DEBUGFS
|
||||
+ depends on DEBUG_FS
|
||||
+ bool "Enable debugfs support"
|
||||
+ default y
|
||||
+ ---help---
|
||||
+ Enable advanced statistics through debugfs interface.
|
||||
+
|
||||
+config FSL_DPAA2_ETH_DCB
|
||||
+ bool "Data Center Bridging (DCB) Support"
|
||||
+ default n
|
||||
+ depends on DCB
|
||||
+ ---help---
|
||||
+ Say Y here if you want to use Data Center Bridging (DCB) features
|
||||
+ (PFC) in the driver.
|
||||
+
|
||||
+ If unsure, say N.
|
||||
+endif
|
||||
+
|
||||
+source "drivers/staging/fsl-dpaa2/mac/Kconfig"
|
||||
+source "drivers/staging/fsl-dpaa2/evb/Kconfig"
|
||||
+
|
||||
+config FSL_DPAA2_ETHSW
|
||||
+ tristate "Freescale DPAA2 Ethernet Switch"
|
||||
+ depends on FSL_DPAA2
|
||||
+ depends on NET_SWITCHDEV
|
||||
+ ---help---
|
||||
+ Driver for Freescale DPAA2 Ethernet Switch. Select
|
||||
+ BRIDGE to have support for bridge tools.
|
||||
--- a/drivers/staging/fsl-dpaa2/Makefile
|
||||
+++ b/drivers/staging/fsl-dpaa2/Makefile
|
||||
@@ -3,3 +3,7 @@
|
||||
#
|
||||
|
||||
obj-$(CONFIG_FSL_DPAA2_ETH) += ethernet/
|
||||
+obj-$(CONFIG_FSL_DPAA2_MAC) += mac/
|
||||
+obj-$(CONFIG_FSL_DPAA2_EVB) += evb/
|
||||
+obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
|
||||
+obj-$(CONFIG_FSL_DPAA2_ETHSW) += ethsw/
|
||||
@ -0,0 +1,741 @@
|
||||
From 74243154052af635ee9ce9d07aab273ce219c855 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Thu, 13 Dec 2018 13:23:52 +0800
|
||||
Subject: [PATCH] core-linux: support layerscape
|
||||
|
||||
This is an integrated patch of core-linux for layerscape.
|
||||
|
||||
Signed-off-by: Abhijit Ayarekar <abhijit.ayarekar@caviumnetworks.com>
|
||||
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
|
||||
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
|
||||
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
|
||||
Signed-off-by: Christoph Hellwig <hch@lst.de>
|
||||
Signed-off-by: David Ahern <dsahern@gmail.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
|
||||
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
|
||||
Signed-off-by: Joel Fernandes <joelaf@google.com>
|
||||
Signed-off-by: Li Yang <leoyang.li@nxp.com>
|
||||
Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
|
||||
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
|
||||
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
|
||||
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
|
||||
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
|
||||
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
|
||||
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/base/dma-mapping.c | 7 ++
|
||||
drivers/net/bonding/bond_main.c | 5 +-
|
||||
drivers/net/bonding/bond_options.c | 2 +-
|
||||
drivers/net/team/team.c | 3 +-
|
||||
drivers/net/vrf.c | 3 +-
|
||||
drivers/of/device.c | 13 +++-
|
||||
drivers/soc/fsl/guts.c | 3 +
|
||||
include/linux/fsl_devices.h | 2 +
|
||||
include/linux/netdevice.h | 13 +++-
|
||||
include/linux/skbuff.h | 2 +
|
||||
include/net/bonding.h | 3 +-
|
||||
net/batman-adv/soft-interface.c | 3 +-
|
||||
net/bridge/br_device.c | 3 +-
|
||||
net/core/dev.c | 81 ++++++++++++++---------
|
||||
net/core/rtnetlink.c | 10 +--
|
||||
net/core/skbuff.c | 29 +++++++-
|
||||
samples/bpf/Makefile | 12 +++-
|
||||
samples/bpf/map_perf_test_kern.c | 2 +-
|
||||
samples/bpf/map_perf_test_user.c | 2 +-
|
||||
tools/testing/selftests/bpf/bpf_helpers.h | 56 ++++++++++++++--
|
||||
20 files changed, 193 insertions(+), 61 deletions(-)
|
||||
|
||||
--- a/drivers/base/dma-mapping.c
|
||||
+++ b/drivers/base/dma-mapping.c
|
||||
@@ -335,6 +335,7 @@ void dma_common_free_remap(void *cpu_add
|
||||
* Common configuration to enable DMA API use for a device
|
||||
*/
|
||||
#include <linux/pci.h>
|
||||
+#include <linux/fsl/mc.h>
|
||||
|
||||
int dma_configure(struct device *dev)
|
||||
{
|
||||
@@ -350,6 +351,12 @@ int dma_configure(struct device *dev)
|
||||
dma_dev = dma_dev->parent;
|
||||
}
|
||||
|
||||
+ if (dev_is_fsl_mc(dev)) {
|
||||
+ dma_dev = dev;
|
||||
+ while (dev_is_fsl_mc(dma_dev))
|
||||
+ dma_dev = dma_dev->parent;
|
||||
+ }
|
||||
+
|
||||
if (dma_dev->of_node) {
|
||||
ret = of_dma_configure(dev, dma_dev->of_node);
|
||||
} else if (has_acpi_companion(dma_dev)) {
|
||||
--- a/drivers/net/bonding/bond_main.c
|
||||
+++ b/drivers/net/bonding/bond_main.c
|
||||
@@ -1337,7 +1337,8 @@ void bond_lower_state_changed(struct sla
|
||||
}
|
||||
|
||||
/* enslave device <slave> to bond device <master> */
|
||||
-int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev)
|
||||
+int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev,
|
||||
+ struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct bonding *bond = netdev_priv(bond_dev);
|
||||
const struct net_device_ops *slave_ops = slave_dev->netdev_ops;
|
||||
@@ -3506,7 +3507,7 @@ static int bond_do_ioctl(struct net_devi
|
||||
switch (cmd) {
|
||||
case BOND_ENSLAVE_OLD:
|
||||
case SIOCBONDENSLAVE:
|
||||
- res = bond_enslave(bond_dev, slave_dev);
|
||||
+ res = bond_enslave(bond_dev, slave_dev, NULL);
|
||||
break;
|
||||
case BOND_RELEASE_OLD:
|
||||
case SIOCBONDRELEASE:
|
||||
--- a/drivers/net/bonding/bond_options.c
|
||||
+++ b/drivers/net/bonding/bond_options.c
|
||||
@@ -1389,7 +1389,7 @@ static int bond_option_slaves_set(struct
|
||||
switch (command[0]) {
|
||||
case '+':
|
||||
netdev_dbg(bond->dev, "Adding slave %s\n", dev->name);
|
||||
- ret = bond_enslave(bond->dev, dev);
|
||||
+ ret = bond_enslave(bond->dev, dev, NULL);
|
||||
break;
|
||||
|
||||
case '-':
|
||||
--- a/drivers/net/team/team.c
|
||||
+++ b/drivers/net/team/team.c
|
||||
@@ -1934,7 +1934,8 @@ static int team_netpoll_setup(struct net
|
||||
}
|
||||
#endif
|
||||
|
||||
-static int team_add_slave(struct net_device *dev, struct net_device *port_dev)
|
||||
+static int team_add_slave(struct net_device *dev, struct net_device *port_dev,
|
||||
+ struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct team *team = netdev_priv(dev);
|
||||
int err;
|
||||
--- a/drivers/net/vrf.c
|
||||
+++ b/drivers/net/vrf.c
|
||||
@@ -791,7 +791,8 @@ err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev)
|
||||
+static int vrf_add_slave(struct net_device *dev, struct net_device *port_dev,
|
||||
+ struct netlink_ext_ack *extack)
|
||||
{
|
||||
if (netif_is_l3_master(port_dev) || netif_is_l3_slave(port_dev))
|
||||
return -EINVAL;
|
||||
--- a/drivers/of/device.c
|
||||
+++ b/drivers/of/device.c
|
||||
@@ -15,6 +15,9 @@
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include "of_private.h"
|
||||
+#ifdef CONFIG_FSL_MC_BUS
|
||||
+#include <linux/fsl/mc.h>
|
||||
+#endif
|
||||
|
||||
/**
|
||||
* of_match_device - Tell if a struct device matches an of_device_id list
|
||||
@@ -105,6 +108,9 @@ int of_dma_configure(struct device *dev,
|
||||
#ifdef CONFIG_ARM_AMBA
|
||||
dev->bus != &amba_bustype &&
|
||||
#endif
|
||||
+#ifdef CONFIG_FSL_MC_BUS
|
||||
+ dev->bus != &fsl_mc_bus_type &&
|
||||
+#endif
|
||||
dev->bus != &platform_bus_type)
|
||||
return ret == -ENODEV ? 0 : ret;
|
||||
|
||||
@@ -155,7 +161,12 @@ int of_dma_configure(struct device *dev,
|
||||
dev->coherent_dma_mask &= mask;
|
||||
*dev->dma_mask &= mask;
|
||||
|
||||
- coherent = of_dma_is_coherent(np);
|
||||
+#ifdef CONFIG_FSL_MC_BUS
|
||||
+ if (dev_is_fsl_mc(dev))
|
||||
+ coherent = fsl_mc_is_dev_coherent(dev);
|
||||
+ else
|
||||
+#endif
|
||||
+ coherent = of_dma_is_coherent(np);
|
||||
dev_dbg(dev, "device is%sdma coherent\n",
|
||||
coherent ? " " : " not ");
|
||||
|
||||
--- a/drivers/soc/fsl/guts.c
|
||||
+++ b/drivers/soc/fsl/guts.c
|
||||
@@ -213,6 +213,9 @@ static const struct of_device_id fsl_gut
|
||||
{ .compatible = "fsl,ls1021a-dcfg", },
|
||||
{ .compatible = "fsl,ls1043a-dcfg", },
|
||||
{ .compatible = "fsl,ls2080a-dcfg", },
|
||||
+ { .compatible = "fsl,ls1088a-dcfg", },
|
||||
+ { .compatible = "fsl,ls1012a-dcfg", },
|
||||
+ { .compatible = "fsl,ls1046a-dcfg", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
|
||||
--- a/include/linux/fsl_devices.h
|
||||
+++ b/include/linux/fsl_devices.h
|
||||
@@ -99,7 +99,9 @@ struct fsl_usb2_platform_data {
|
||||
unsigned suspended:1;
|
||||
unsigned already_suspended:1;
|
||||
unsigned has_fsl_erratum_a007792:1;
|
||||
+ unsigned has_fsl_erratum_14:1;
|
||||
unsigned has_fsl_erratum_a005275:1;
|
||||
+ unsigned has_fsl_erratum_a006918:1;
|
||||
unsigned has_fsl_erratum_a005697:1;
|
||||
unsigned check_phy_clk_valid:1;
|
||||
|
||||
--- a/include/linux/netdevice.h
|
||||
+++ b/include/linux/netdevice.h
|
||||
@@ -1260,7 +1260,8 @@ struct net_device_ops {
|
||||
u32 flow_id);
|
||||
#endif
|
||||
int (*ndo_add_slave)(struct net_device *dev,
|
||||
- struct net_device *slave_dev);
|
||||
+ struct net_device *slave_dev,
|
||||
+ struct netlink_ext_ack *extack);
|
||||
int (*ndo_del_slave)(struct net_device *dev,
|
||||
struct net_device *slave_dev);
|
||||
netdev_features_t (*ndo_fix_features)(struct net_device *dev,
|
||||
@@ -2341,7 +2342,8 @@ int register_netdevice_notifier(struct n
|
||||
int unregister_netdevice_notifier(struct notifier_block *nb);
|
||||
|
||||
struct netdev_notifier_info {
|
||||
- struct net_device *dev;
|
||||
+ struct net_device *dev;
|
||||
+ struct netlink_ext_ack *extack;
|
||||
};
|
||||
|
||||
struct netdev_notifier_info_ext {
|
||||
@@ -2373,6 +2375,7 @@ static inline void netdev_notifier_info_
|
||||
struct net_device *dev)
|
||||
{
|
||||
info->dev = dev;
|
||||
+ info->extack = NULL;
|
||||
}
|
||||
|
||||
static inline struct net_device *
|
||||
@@ -2381,6 +2384,12 @@ netdev_notifier_info_to_dev(const struct
|
||||
return info->dev;
|
||||
}
|
||||
|
||||
+static inline struct netlink_ext_ack *
|
||||
+netdev_notifier_info_to_extack(const struct netdev_notifier_info *info)
|
||||
+{
|
||||
+ return info->extack;
|
||||
+}
|
||||
+
|
||||
int call_netdevice_notifiers(unsigned long val, struct net_device *dev);
|
||||
|
||||
|
||||
--- a/include/linux/skbuff.h
|
||||
+++ b/include/linux/skbuff.h
|
||||
@@ -964,6 +964,7 @@ void kfree_skb_list(struct sk_buff *segs
|
||||
void skb_tx_error(struct sk_buff *skb);
|
||||
void consume_skb(struct sk_buff *skb);
|
||||
void __consume_stateless_skb(struct sk_buff *skb);
|
||||
+void skb_recycle(struct sk_buff *skb);
|
||||
void __kfree_skb(struct sk_buff *skb);
|
||||
extern struct kmem_cache *skbuff_head_cache;
|
||||
|
||||
@@ -3293,6 +3294,7 @@ static inline void skb_free_datagram_loc
|
||||
}
|
||||
int skb_kill_datagram(struct sock *sk, struct sk_buff *skb, unsigned int flags);
|
||||
int skb_copy_bits(const struct sk_buff *skb, int offset, void *to, int len);
|
||||
+void copy_skb_header(struct sk_buff *new, const struct sk_buff *old);
|
||||
int skb_store_bits(struct sk_buff *skb, int offset, const void *from, int len);
|
||||
__wsum skb_copy_and_csum_bits(const struct sk_buff *skb, int offset, u8 *to,
|
||||
int len, __wsum csum);
|
||||
--- a/include/net/bonding.h
|
||||
+++ b/include/net/bonding.h
|
||||
@@ -592,7 +592,8 @@ void bond_destroy_sysfs(struct bond_net
|
||||
void bond_prepare_sysfs_group(struct bonding *bond);
|
||||
int bond_sysfs_slave_add(struct slave *slave);
|
||||
void bond_sysfs_slave_del(struct slave *slave);
|
||||
-int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev);
|
||||
+int bond_enslave(struct net_device *bond_dev, struct net_device *slave_dev,
|
||||
+ struct netlink_ext_ack *extack);
|
||||
int bond_release(struct net_device *bond_dev, struct net_device *slave_dev);
|
||||
u32 bond_xmit_hash(struct bonding *bond, struct sk_buff *skb);
|
||||
int bond_set_carrier(struct bonding *bond);
|
||||
--- a/net/batman-adv/soft-interface.c
|
||||
+++ b/net/batman-adv/soft-interface.c
|
||||
@@ -872,7 +872,8 @@ free_bat_counters:
|
||||
* Return: 0 if successful or error otherwise.
|
||||
*/
|
||||
static int batadv_softif_slave_add(struct net_device *dev,
|
||||
- struct net_device *slave_dev)
|
||||
+ struct net_device *slave_dev,
|
||||
+ struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct batadv_hard_iface *hard_iface;
|
||||
struct net *net = dev_net(dev);
|
||||
--- a/net/bridge/br_device.c
|
||||
+++ b/net/bridge/br_device.c
|
||||
@@ -324,7 +324,8 @@ void br_netpoll_disable(struct net_bridg
|
||||
|
||||
#endif
|
||||
|
||||
-static int br_add_slave(struct net_device *dev, struct net_device *slave_dev)
|
||||
+static int br_add_slave(struct net_device *dev, struct net_device *slave_dev,
|
||||
+ struct netlink_ext_ack *extack)
|
||||
|
||||
{
|
||||
struct net_bridge *br = netdev_priv(dev);
|
||||
--- a/net/core/dev.c
|
||||
+++ b/net/core/dev.c
|
||||
@@ -162,7 +162,6 @@ static struct list_head offload_base __r
|
||||
|
||||
static int netif_rx_internal(struct sk_buff *skb);
|
||||
static int call_netdevice_notifiers_info(unsigned long val,
|
||||
- struct net_device *dev,
|
||||
struct netdev_notifier_info *info);
|
||||
static struct napi_struct *napi_by_id(unsigned int napi_id);
|
||||
|
||||
@@ -1312,10 +1311,11 @@ EXPORT_SYMBOL(netdev_features_change);
|
||||
void netdev_state_change(struct net_device *dev)
|
||||
{
|
||||
if (dev->flags & IFF_UP) {
|
||||
- struct netdev_notifier_change_info change_info;
|
||||
+ struct netdev_notifier_change_info change_info = {
|
||||
+ .info.dev = dev,
|
||||
+ };
|
||||
|
||||
- change_info.flags_changed = 0;
|
||||
- call_netdevice_notifiers_info(NETDEV_CHANGE, dev,
|
||||
+ call_netdevice_notifiers_info(NETDEV_CHANGE,
|
||||
&change_info.info);
|
||||
rtmsg_ifinfo(RTM_NEWLINK, dev, 0, GFP_KERNEL);
|
||||
}
|
||||
@@ -1536,9 +1536,10 @@ EXPORT_SYMBOL(dev_disable_lro);
|
||||
static int call_netdevice_notifier(struct notifier_block *nb, unsigned long val,
|
||||
struct net_device *dev)
|
||||
{
|
||||
- struct netdev_notifier_info info;
|
||||
+ struct netdev_notifier_info info = {
|
||||
+ .dev = dev,
|
||||
+ };
|
||||
|
||||
- netdev_notifier_info_init(&info, dev);
|
||||
return nb->notifier_call(nb, val, &info);
|
||||
}
|
||||
|
||||
@@ -1663,11 +1664,9 @@ EXPORT_SYMBOL(unregister_netdevice_notif
|
||||
*/
|
||||
|
||||
static int call_netdevice_notifiers_info(unsigned long val,
|
||||
- struct net_device *dev,
|
||||
struct netdev_notifier_info *info)
|
||||
{
|
||||
ASSERT_RTNL();
|
||||
- netdev_notifier_info_init(info, dev);
|
||||
return raw_notifier_call_chain(&netdev_chain, val, info);
|
||||
}
|
||||
|
||||
@@ -1682,9 +1681,11 @@ static int call_netdevice_notifiers_info
|
||||
|
||||
int call_netdevice_notifiers(unsigned long val, struct net_device *dev)
|
||||
{
|
||||
- struct netdev_notifier_info info;
|
||||
+ struct netdev_notifier_info info = {
|
||||
+ .dev = dev,
|
||||
+ };
|
||||
|
||||
- return call_netdevice_notifiers_info(val, dev, &info);
|
||||
+ return call_netdevice_notifiers_info(val, &info);
|
||||
}
|
||||
EXPORT_SYMBOL(call_netdevice_notifiers);
|
||||
|
||||
@@ -1707,7 +1708,7 @@ static int call_netdevice_notifiers_mtu(
|
||||
|
||||
BUILD_BUG_ON(offsetof(struct netdev_notifier_info_ext, info) != 0);
|
||||
|
||||
- return call_netdevice_notifiers_info(val, dev, &info.info);
|
||||
+ return call_netdevice_notifiers_info(val, &info.info);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_NET_INGRESS
|
||||
@@ -6338,7 +6339,15 @@ static int __netdev_upper_dev_link(struc
|
||||
struct net_device *upper_dev, bool master,
|
||||
void *upper_priv, void *upper_info)
|
||||
{
|
||||
- struct netdev_notifier_changeupper_info changeupper_info;
|
||||
+ struct netdev_notifier_changeupper_info changeupper_info = {
|
||||
+ .info = {
|
||||
+ .dev = dev,
|
||||
+ },
|
||||
+ .upper_dev = upper_dev,
|
||||
+ .master = master,
|
||||
+ .linking = true,
|
||||
+ .upper_info = upper_info,
|
||||
+ };
|
||||
int ret = 0;
|
||||
|
||||
ASSERT_RTNL();
|
||||
@@ -6356,12 +6365,7 @@ static int __netdev_upper_dev_link(struc
|
||||
if (master && netdev_master_upper_dev_get(dev))
|
||||
return -EBUSY;
|
||||
|
||||
- changeupper_info.upper_dev = upper_dev;
|
||||
- changeupper_info.master = master;
|
||||
- changeupper_info.linking = true;
|
||||
- changeupper_info.upper_info = upper_info;
|
||||
-
|
||||
- ret = call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER, dev,
|
||||
+ ret = call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER,
|
||||
&changeupper_info.info);
|
||||
ret = notifier_to_errno(ret);
|
||||
if (ret)
|
||||
@@ -6373,7 +6377,7 @@ static int __netdev_upper_dev_link(struc
|
||||
return ret;
|
||||
|
||||
netdev_update_addr_mask(dev);
|
||||
- ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, dev,
|
||||
+ ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
|
||||
&changeupper_info.info);
|
||||
ret = notifier_to_errno(ret);
|
||||
if (ret)
|
||||
@@ -6437,21 +6441,25 @@ EXPORT_SYMBOL(netdev_master_upper_dev_li
|
||||
void netdev_upper_dev_unlink(struct net_device *dev,
|
||||
struct net_device *upper_dev)
|
||||
{
|
||||
- struct netdev_notifier_changeupper_info changeupper_info;
|
||||
+ struct netdev_notifier_changeupper_info changeupper_info = {
|
||||
+ .info = {
|
||||
+ .dev = dev,
|
||||
+ },
|
||||
+ .upper_dev = upper_dev,
|
||||
+ .linking = false,
|
||||
+ };
|
||||
|
||||
ASSERT_RTNL();
|
||||
|
||||
- changeupper_info.upper_dev = upper_dev;
|
||||
changeupper_info.master = netdev_master_upper_dev_get(dev) == upper_dev;
|
||||
- changeupper_info.linking = false;
|
||||
|
||||
- call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER, dev,
|
||||
+ call_netdevice_notifiers_info(NETDEV_PRECHANGEUPPER,
|
||||
&changeupper_info.info);
|
||||
|
||||
__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
|
||||
|
||||
netdev_update_addr_mask(dev);
|
||||
- call_netdevice_notifiers_info(NETDEV_CHANGEUPPER, dev,
|
||||
+ call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
|
||||
&changeupper_info.info);
|
||||
}
|
||||
EXPORT_SYMBOL(netdev_upper_dev_unlink);
|
||||
@@ -6467,11 +6475,13 @@ EXPORT_SYMBOL(netdev_upper_dev_unlink);
|
||||
void netdev_bonding_info_change(struct net_device *dev,
|
||||
struct netdev_bonding_info *bonding_info)
|
||||
{
|
||||
- struct netdev_notifier_bonding_info info;
|
||||
+ struct netdev_notifier_bonding_info info = {
|
||||
+ .info.dev = dev,
|
||||
+ };
|
||||
|
||||
memcpy(&info.bonding_info, bonding_info,
|
||||
sizeof(struct netdev_bonding_info));
|
||||
- call_netdevice_notifiers_info(NETDEV_BONDING_INFO, dev,
|
||||
+ call_netdevice_notifiers_info(NETDEV_BONDING_INFO,
|
||||
&info.info);
|
||||
}
|
||||
EXPORT_SYMBOL(netdev_bonding_info_change);
|
||||
@@ -6597,11 +6607,13 @@ EXPORT_SYMBOL(dev_get_nest_level);
|
||||
void netdev_lower_state_changed(struct net_device *lower_dev,
|
||||
void *lower_state_info)
|
||||
{
|
||||
- struct netdev_notifier_changelowerstate_info changelowerstate_info;
|
||||
+ struct netdev_notifier_changelowerstate_info changelowerstate_info = {
|
||||
+ .info.dev = lower_dev,
|
||||
+ };
|
||||
|
||||
ASSERT_RTNL();
|
||||
changelowerstate_info.lower_state_info = lower_state_info;
|
||||
- call_netdevice_notifiers_info(NETDEV_CHANGELOWERSTATE, lower_dev,
|
||||
+ call_netdevice_notifiers_info(NETDEV_CHANGELOWERSTATE,
|
||||
&changelowerstate_info.info);
|
||||
}
|
||||
EXPORT_SYMBOL(netdev_lower_state_changed);
|
||||
@@ -6892,11 +6904,14 @@ void __dev_notify_flags(struct net_devic
|
||||
|
||||
if (dev->flags & IFF_UP &&
|
||||
(changes & ~(IFF_UP | IFF_PROMISC | IFF_ALLMULTI | IFF_VOLATILE))) {
|
||||
- struct netdev_notifier_change_info change_info;
|
||||
+ struct netdev_notifier_change_info change_info = {
|
||||
+ .info = {
|
||||
+ .dev = dev,
|
||||
+ },
|
||||
+ .flags_changed = changes,
|
||||
+ };
|
||||
|
||||
- change_info.flags_changed = changes;
|
||||
- call_netdevice_notifiers_info(NETDEV_CHANGE, dev,
|
||||
- &change_info.info);
|
||||
+ call_netdevice_notifiers_info(NETDEV_CHANGE, &change_info.info);
|
||||
}
|
||||
}
|
||||
|
||||
--- a/net/core/rtnetlink.c
|
||||
+++ b/net/core/rtnetlink.c
|
||||
@@ -1912,7 +1912,8 @@ static int do_setvfinfo(struct net_devic
|
||||
return err;
|
||||
}
|
||||
|
||||
-static int do_set_master(struct net_device *dev, int ifindex)
|
||||
+static int do_set_master(struct net_device *dev, int ifindex,
|
||||
+ struct netlink_ext_ack *extack)
|
||||
{
|
||||
struct net_device *upper_dev = netdev_master_upper_dev_get(dev);
|
||||
const struct net_device_ops *ops;
|
||||
@@ -1937,7 +1938,7 @@ static int do_set_master(struct net_devi
|
||||
return -EINVAL;
|
||||
ops = upper_dev->netdev_ops;
|
||||
if (ops->ndo_add_slave) {
|
||||
- err = ops->ndo_add_slave(upper_dev, dev);
|
||||
+ err = ops->ndo_add_slave(upper_dev, dev, extack);
|
||||
if (err)
|
||||
return err;
|
||||
} else {
|
||||
@@ -2074,7 +2075,7 @@ static int do_setlink(const struct sk_bu
|
||||
}
|
||||
|
||||
if (tb[IFLA_MASTER]) {
|
||||
- err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]));
|
||||
+ err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]), extack);
|
||||
if (err)
|
||||
goto errout;
|
||||
status |= DO_SETLINK_MODIFIED;
|
||||
@@ -2723,7 +2724,8 @@ replay:
|
||||
goto out_unregister;
|
||||
}
|
||||
if (tb[IFLA_MASTER]) {
|
||||
- err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]));
|
||||
+ err = do_set_master(dev, nla_get_u32(tb[IFLA_MASTER]),
|
||||
+ extack);
|
||||
if (err)
|
||||
goto out_unregister;
|
||||
}
|
||||
--- a/net/core/skbuff.c
|
||||
+++ b/net/core/skbuff.c
|
||||
@@ -799,6 +799,32 @@ void napi_consume_skb(struct sk_buff *sk
|
||||
}
|
||||
EXPORT_SYMBOL(napi_consume_skb);
|
||||
|
||||
+/**
|
||||
+ * skb_recycle - clean up an skb for reuse
|
||||
+ * @skb: buffer
|
||||
+ *
|
||||
+ * Recycles the skb to be reused as a receive buffer. This
|
||||
+ * function does any necessary reference count dropping, and
|
||||
+ * cleans up the skbuff as if it just came from __alloc_skb().
|
||||
+ */
|
||||
+void skb_recycle(struct sk_buff *skb)
|
||||
+{
|
||||
+ struct skb_shared_info *shinfo;
|
||||
+ u8 head_frag = skb->head_frag;
|
||||
+
|
||||
+ skb_release_head_state(skb);
|
||||
+
|
||||
+ shinfo = skb_shinfo(skb);
|
||||
+ memset(shinfo, 0, offsetof(struct skb_shared_info, dataref));
|
||||
+ atomic_set(&shinfo->dataref, 1);
|
||||
+
|
||||
+ memset(skb, 0, offsetof(struct sk_buff, tail));
|
||||
+ skb->data = skb->head + NET_SKB_PAD;
|
||||
+ skb->head_frag = head_frag;
|
||||
+ skb_reset_tail_pointer(skb);
|
||||
+}
|
||||
+EXPORT_SYMBOL(skb_recycle);
|
||||
+
|
||||
/* Make sure a field is enclosed inside headers_start/headers_end section */
|
||||
#define CHECK_SKB_FIELD(field) \
|
||||
BUILD_BUG_ON(offsetof(struct sk_buff, field) < \
|
||||
@@ -1318,7 +1344,7 @@ static void skb_headers_offset_update(st
|
||||
skb->inner_mac_header += off;
|
||||
}
|
||||
|
||||
-static void copy_skb_header(struct sk_buff *new, const struct sk_buff *old)
|
||||
+void copy_skb_header(struct sk_buff *new, const struct sk_buff *old)
|
||||
{
|
||||
__copy_skb_header(new, old);
|
||||
|
||||
@@ -1326,6 +1352,7 @@ static void copy_skb_header(struct sk_bu
|
||||
skb_shinfo(new)->gso_segs = skb_shinfo(old)->gso_segs;
|
||||
skb_shinfo(new)->gso_type = skb_shinfo(old)->gso_type;
|
||||
}
|
||||
+EXPORT_SYMBOL(copy_skb_header);
|
||||
|
||||
static inline int skb_alloc_rx_flag(const struct sk_buff *skb)
|
||||
{
|
||||
--- a/samples/bpf/Makefile
|
||||
+++ b/samples/bpf/Makefile
|
||||
@@ -178,6 +178,12 @@ HOSTLOADLIBES_syscall_tp += -lelf
|
||||
LLC ?= llc
|
||||
CLANG ?= clang
|
||||
|
||||
+# Detect that we're cross compiling and use the cross compiler
|
||||
+ifdef CROSS_COMPILE
|
||||
+HOSTCC = $(CROSS_COMPILE)gcc
|
||||
+CLANG_ARCH_ARGS = -target $(ARCH)
|
||||
+endif
|
||||
+
|
||||
# Trick to allow make to be run from this directory
|
||||
all: $(LIBBPF)
|
||||
$(MAKE) -C ../../ $(CURDIR)/
|
||||
@@ -228,9 +234,9 @@ $(obj)/tracex5_kern.o: $(obj)/syscall_nr
|
||||
$(obj)/%.o: $(src)/%.c
|
||||
$(CLANG) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) $(EXTRA_CFLAGS) -I$(obj) \
|
||||
-I$(srctree)/tools/testing/selftests/bpf/ \
|
||||
- -D__KERNEL__ -D__ASM_SYSREG_H -Wno-unused-value -Wno-pointer-sign \
|
||||
- -Wno-compare-distinct-pointer-types \
|
||||
+ -D__KERNEL__ -Wno-unused-value -Wno-pointer-sign \
|
||||
+ -D__TARGET_ARCH_$(ARCH) -Wno-compare-distinct-pointer-types \
|
||||
-Wno-gnu-variable-sized-type-not-at-end \
|
||||
-Wno-address-of-packed-member -Wno-tautological-compare \
|
||||
- -Wno-unknown-warning-option \
|
||||
+ -Wno-unknown-warning-option $(CLANG_ARCH_ARGS) \
|
||||
-O2 -emit-llvm -c $< -o -| $(LLC) -march=bpf -filetype=obj -o $@
|
||||
--- a/samples/bpf/map_perf_test_kern.c
|
||||
+++ b/samples/bpf/map_perf_test_kern.c
|
||||
@@ -266,7 +266,7 @@ int stress_hash_map_lookup(struct pt_reg
|
||||
return 0;
|
||||
}
|
||||
|
||||
-SEC("kprobe/sys_getpgrp")
|
||||
+SEC("kprobe/sys_getppid")
|
||||
int stress_array_map_lookup(struct pt_regs *ctx)
|
||||
{
|
||||
u32 key = 1, i;
|
||||
--- a/samples/bpf/map_perf_test_user.c
|
||||
+++ b/samples/bpf/map_perf_test_user.c
|
||||
@@ -282,7 +282,7 @@ static void test_array_lookup(int cpu)
|
||||
|
||||
start_time = time_get_ns();
|
||||
for (i = 0; i < max_cnt; i++)
|
||||
- syscall(__NR_getpgrp, 0);
|
||||
+ syscall(__NR_getppid, 0);
|
||||
printf("%d:array_lookup %lld lookups per sec\n",
|
||||
cpu, max_cnt * 1000000000ll * 64 / (time_get_ns() - start_time));
|
||||
}
|
||||
--- a/tools/testing/selftests/bpf/bpf_helpers.h
|
||||
+++ b/tools/testing/selftests/bpf/bpf_helpers.h
|
||||
@@ -110,7 +110,47 @@ static int (*bpf_skb_under_cgroup)(void
|
||||
static int (*bpf_skb_change_head)(void *, int len, int flags) =
|
||||
(void *) BPF_FUNC_skb_change_head;
|
||||
|
||||
+/* Scan the ARCH passed in from ARCH env variable (see Makefile) */
|
||||
+#if defined(__TARGET_ARCH_x86)
|
||||
+ #define bpf_target_x86
|
||||
+ #define bpf_target_defined
|
||||
+#elif defined(__TARGET_ARCH_s930x)
|
||||
+ #define bpf_target_s930x
|
||||
+ #define bpf_target_defined
|
||||
+#elif defined(__TARGET_ARCH_arm64)
|
||||
+ #define bpf_target_arm64
|
||||
+ #define bpf_target_defined
|
||||
+#elif defined(__TARGET_ARCH_mips)
|
||||
+ #define bpf_target_mips
|
||||
+ #define bpf_target_defined
|
||||
+#elif defined(__TARGET_ARCH_powerpc)
|
||||
+ #define bpf_target_powerpc
|
||||
+ #define bpf_target_defined
|
||||
+#elif defined(__TARGET_ARCH_sparc)
|
||||
+ #define bpf_target_sparc
|
||||
+ #define bpf_target_defined
|
||||
+#else
|
||||
+ #undef bpf_target_defined
|
||||
+#endif
|
||||
+
|
||||
+/* Fall back to what the compiler says */
|
||||
+#ifndef bpf_target_defined
|
||||
#if defined(__x86_64__)
|
||||
+ #define bpf_target_x86
|
||||
+#elif defined(__s390x__)
|
||||
+ #define bpf_target_s930x
|
||||
+#elif defined(__aarch64__)
|
||||
+ #define bpf_target_arm64
|
||||
+#elif defined(__mips__)
|
||||
+ #define bpf_target_mips
|
||||
+#elif defined(__powerpc__)
|
||||
+ #define bpf_target_powerpc
|
||||
+#elif defined(__sparc__)
|
||||
+ #define bpf_target_sparc
|
||||
+#endif
|
||||
+#endif
|
||||
+
|
||||
+#if defined(bpf_target_x86)
|
||||
|
||||
#define PT_REGS_PARM1(x) ((x)->di)
|
||||
#define PT_REGS_PARM2(x) ((x)->si)
|
||||
@@ -123,7 +163,7 @@ static int (*bpf_skb_change_head)(void *
|
||||
#define PT_REGS_SP(x) ((x)->sp)
|
||||
#define PT_REGS_IP(x) ((x)->ip)
|
||||
|
||||
-#elif defined(__s390x__)
|
||||
+#elif defined(bpf_target_s390x)
|
||||
|
||||
#define PT_REGS_PARM1(x) ((x)->gprs[2])
|
||||
#define PT_REGS_PARM2(x) ((x)->gprs[3])
|
||||
@@ -136,7 +176,7 @@ static int (*bpf_skb_change_head)(void *
|
||||
#define PT_REGS_SP(x) ((x)->gprs[15])
|
||||
#define PT_REGS_IP(x) ((x)->psw.addr)
|
||||
|
||||
-#elif defined(__aarch64__)
|
||||
+#elif defined(bpf_target_arm64)
|
||||
|
||||
#define PT_REGS_PARM1(x) ((x)->regs[0])
|
||||
#define PT_REGS_PARM2(x) ((x)->regs[1])
|
||||
@@ -149,7 +189,7 @@ static int (*bpf_skb_change_head)(void *
|
||||
#define PT_REGS_SP(x) ((x)->sp)
|
||||
#define PT_REGS_IP(x) ((x)->pc)
|
||||
|
||||
-#elif defined(__mips__)
|
||||
+#elif defined(bpf_target_mips)
|
||||
|
||||
#define PT_REGS_PARM1(x) ((x)->regs[4])
|
||||
#define PT_REGS_PARM2(x) ((x)->regs[5])
|
||||
@@ -162,7 +202,7 @@ static int (*bpf_skb_change_head)(void *
|
||||
#define PT_REGS_SP(x) ((x)->regs[29])
|
||||
#define PT_REGS_IP(x) ((x)->cp0_epc)
|
||||
|
||||
-#elif defined(__powerpc__)
|
||||
+#elif defined(bpf_target_powerpc)
|
||||
|
||||
#define PT_REGS_PARM1(x) ((x)->gpr[3])
|
||||
#define PT_REGS_PARM2(x) ((x)->gpr[4])
|
||||
@@ -173,7 +213,7 @@ static int (*bpf_skb_change_head)(void *
|
||||
#define PT_REGS_SP(x) ((x)->sp)
|
||||
#define PT_REGS_IP(x) ((x)->nip)
|
||||
|
||||
-#elif defined(__sparc__)
|
||||
+#elif defined(bpf_target_sparc)
|
||||
|
||||
#define PT_REGS_PARM1(x) ((x)->u_regs[UREG_I0])
|
||||
#define PT_REGS_PARM2(x) ((x)->u_regs[UREG_I1])
|
||||
@@ -183,6 +223,8 @@ static int (*bpf_skb_change_head)(void *
|
||||
#define PT_REGS_RET(x) ((x)->u_regs[UREG_I7])
|
||||
#define PT_REGS_RC(x) ((x)->u_regs[UREG_I0])
|
||||
#define PT_REGS_SP(x) ((x)->u_regs[UREG_FP])
|
||||
+
|
||||
+/* Should this also be a bpf_target check for the sparc case? */
|
||||
#if defined(__arch64__)
|
||||
#define PT_REGS_IP(x) ((x)->tpc)
|
||||
#else
|
||||
@@ -191,10 +233,10 @@ static int (*bpf_skb_change_head)(void *
|
||||
|
||||
#endif
|
||||
|
||||
-#ifdef __powerpc__
|
||||
+#ifdef bpf_target_powerpc
|
||||
#define BPF_KPROBE_READ_RET_IP(ip, ctx) ({ (ip) = (ctx)->link; })
|
||||
#define BPF_KRETPROBE_READ_RET_IP BPF_KPROBE_READ_RET_IP
|
||||
-#elif defined(__sparc__)
|
||||
+#elif bpf_target_sparc
|
||||
#define BPF_KPROBE_READ_RET_IP(ip, ctx) ({ (ip) = PT_REGS_RET(ctx); })
|
||||
#define BPF_KRETPROBE_READ_RET_IP BPF_KPROBE_READ_RET_IP
|
||||
#else
|
||||
@ -0,0 +1,325 @@
|
||||
From 6eeff55fd4756f271ad09a914078c9aa45f8359d Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Fri, 16 Nov 2018 14:23:40 +0800
|
||||
Subject: [PATCH 04/39] arch: support layerscape
|
||||
This is an integrated patch of arch for layerscape
|
||||
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Signed-off-by: Alison Wang <alison.wang@freescale.com>
|
||||
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
|
||||
Signed-off-by: Dave Liu <daveliu@freescale.com>
|
||||
Signed-off-by: Guanhua <guanhua.gao@nxp.com>
|
||||
Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
|
||||
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
|
||||
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
|
||||
Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
|
||||
Signed-off-by: Jin Qing <b24347@freescale.com>
|
||||
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
|
||||
Signed-off-by: Li Yang <leoli@freescale.com>
|
||||
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
|
||||
Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
|
||||
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
|
||||
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
||||
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
|
||||
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
|
||||
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
|
||||
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
|
||||
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
|
||||
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
|
||||
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
|
||||
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/delay.h | 16 ++++++++++++++
|
||||
arch/arm/include/asm/io.h | 31 +++++++++++++++++++++++++++
|
||||
arch/arm/include/asm/mach/map.h | 4 ++--
|
||||
arch/arm/include/asm/pgtable.h | 7 ++++++
|
||||
arch/arm/kernel/time.c | 3 +++
|
||||
arch/arm/mm/dma-mapping.c | 1 +
|
||||
arch/arm/mm/ioremap.c | 7 ++++++
|
||||
arch/arm/mm/mmu.c | 9 ++++++++
|
||||
arch/arm64/include/asm/cache.h | 2 +-
|
||||
arch/arm64/include/asm/io.h | 1 +
|
||||
arch/arm64/include/asm/pgtable-prot.h | 3 +++
|
||||
arch/arm64/include/asm/pgtable.h | 5 +++++
|
||||
arch/arm64/mm/dma-mapping.c | 1 +
|
||||
arch/arm64/mm/init.c | 12 +++++++----
|
||||
14 files changed, 95 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/arch/arm/include/asm/delay.h
|
||||
+++ b/arch/arm/include/asm/delay.h
|
||||
@@ -85,6 +85,22 @@ extern void __bad_udelay(void);
|
||||
__const_udelay((n) * UDELAY_MULT)) : \
|
||||
__udelay(n))
|
||||
|
||||
+#define spin_event_timeout(condition, timeout, delay) \
|
||||
+({ \
|
||||
+ typeof(condition) __ret; \
|
||||
+ int i = 0; \
|
||||
+ while (!(__ret = (condition)) && (i++ < timeout)) { \
|
||||
+ if (delay) \
|
||||
+ udelay(delay); \
|
||||
+ else \
|
||||
+ cpu_relax(); \
|
||||
+ udelay(1); \
|
||||
+ } \
|
||||
+ if (!__ret) \
|
||||
+ __ret = (condition); \
|
||||
+ __ret; \
|
||||
+})
|
||||
+
|
||||
/* Loop-based definitions for assembly code. */
|
||||
extern void __loop_delay(unsigned long loops);
|
||||
extern void __loop_udelay(unsigned long usecs);
|
||||
--- a/arch/arm/include/asm/io.h
|
||||
+++ b/arch/arm/include/asm/io.h
|
||||
@@ -128,6 +128,7 @@ static inline u32 __raw_readl(const vola
|
||||
#define MT_DEVICE_NONSHARED 1
|
||||
#define MT_DEVICE_CACHED 2
|
||||
#define MT_DEVICE_WC 3
|
||||
+#define MT_MEMORY_RW_NS 4
|
||||
/*
|
||||
* types 4 onwards can be found in asm/mach/map.h and are undefined
|
||||
* for ioremap
|
||||
@@ -229,6 +230,34 @@ void __iomem *pci_remap_cfgspace(resourc
|
||||
#endif
|
||||
#endif
|
||||
|
||||
+/* access ports */
|
||||
+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
|
||||
+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
|
||||
+
|
||||
+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
|
||||
+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
|
||||
+
|
||||
+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
|
||||
+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
|
||||
+
|
||||
+/* Clear and set bits in one shot. These macros can be used to clear and
|
||||
+ * set multiple bits in a register using a single read-modify-write. These
|
||||
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
|
||||
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
|
||||
+ * in the 'set' parameter.
|
||||
+ */
|
||||
+
|
||||
+#define clrsetbits_be32(addr, clear, set) \
|
||||
+ iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
|
||||
+#define clrsetbits_le32(addr, clear, set) \
|
||||
+ iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
|
||||
+#define clrsetbits_be16(addr, clear, set) \
|
||||
+ iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
|
||||
+#define clrsetbits_le16(addr, clear, set) \
|
||||
+ iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
|
||||
+#define clrsetbits_8(addr, clear, set) \
|
||||
+ iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
|
||||
+
|
||||
/*
|
||||
* IO port access primitives
|
||||
* -------------------------
|
||||
@@ -417,6 +446,8 @@ void __iomem *ioremap_wc(resource_size_t
|
||||
#define ioremap_wc ioremap_wc
|
||||
#define ioremap_wt ioremap_wc
|
||||
|
||||
+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
|
||||
+
|
||||
void iounmap(volatile void __iomem *iomem_cookie);
|
||||
#define iounmap iounmap
|
||||
|
||||
--- a/arch/arm/include/asm/mach/map.h
|
||||
+++ b/arch/arm/include/asm/mach/map.h
|
||||
@@ -21,9 +21,9 @@ struct map_desc {
|
||||
unsigned int type;
|
||||
};
|
||||
|
||||
-/* types 0-3 are defined in asm/io.h */
|
||||
+/* types 0-4 are defined in asm/io.h */
|
||||
enum {
|
||||
- MT_UNCACHED = 4,
|
||||
+ MT_UNCACHED = 5,
|
||||
MT_CACHECLEAN,
|
||||
MT_MINICLEAN,
|
||||
MT_LOW_VECTORS,
|
||||
--- a/arch/arm/include/asm/pgtable.h
|
||||
+++ b/arch/arm/include/asm/pgtable.h
|
||||
@@ -119,6 +119,13 @@ extern pgprot_t pgprot_s2_device;
|
||||
#define pgprot_noncached(prot) \
|
||||
__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
|
||||
|
||||
+#define pgprot_cached(prot) \
|
||||
+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
|
||||
+
|
||||
+#define pgprot_cached_ns(prot) \
|
||||
+ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
|
||||
+ L_PTE_MT_DEV_NONSHARED)
|
||||
+
|
||||
#define pgprot_writecombine(prot) \
|
||||
__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
|
||||
|
||||
--- a/arch/arm/kernel/time.c
|
||||
+++ b/arch/arm/kernel/time.c
|
||||
@@ -12,6 +12,7 @@
|
||||
* reading the RTC at bootup, etc...
|
||||
*/
|
||||
#include <linux/clk-provider.h>
|
||||
+#include <linux/clockchips.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/export.h>
|
||||
@@ -121,5 +122,7 @@ void __init time_init(void)
|
||||
of_clk_init(NULL);
|
||||
#endif
|
||||
timer_probe();
|
||||
+
|
||||
+ tick_setup_hrtimer_broadcast();
|
||||
}
|
||||
}
|
||||
--- a/arch/arm/mm/dma-mapping.c
|
||||
+++ b/arch/arm/mm/dma-mapping.c
|
||||
@@ -2416,6 +2416,7 @@ void arch_setup_dma_ops(struct device *d
|
||||
#endif
|
||||
dev->archdata.dma_ops_setup = true;
|
||||
}
|
||||
+EXPORT_SYMBOL(arch_setup_dma_ops);
|
||||
|
||||
void arch_teardown_dma_ops(struct device *dev)
|
||||
{
|
||||
--- a/arch/arm/mm/ioremap.c
|
||||
+++ b/arch/arm/mm/ioremap.c
|
||||
@@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t
|
||||
}
|
||||
EXPORT_SYMBOL(ioremap_wc);
|
||||
|
||||
+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
|
||||
+{
|
||||
+ return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
|
||||
+ __builtin_return_address(0));
|
||||
+}
|
||||
+EXPORT_SYMBOL(ioremap_cache_ns);
|
||||
+
|
||||
/*
|
||||
* Remap an arbitrary physical address space into the kernel virtual
|
||||
* address space as memory. Needed when the kernel wants to execute
|
||||
--- a/arch/arm/mm/mmu.c
|
||||
+++ b/arch/arm/mm/mmu.c
|
||||
@@ -315,6 +315,13 @@ static struct mem_type mem_types[] __ro_
|
||||
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
|
||||
.domain = DOMAIN_KERNEL,
|
||||
},
|
||||
+ [MT_MEMORY_RW_NS] = {
|
||||
+ .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
|
||||
+ L_PTE_XN,
|
||||
+ .prot_l1 = PMD_TYPE_TABLE,
|
||||
+ .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
|
||||
+ .domain = DOMAIN_KERNEL,
|
||||
+ },
|
||||
[MT_ROM] = {
|
||||
.prot_sect = PMD_TYPE_SECT,
|
||||
.domain = DOMAIN_KERNEL,
|
||||
@@ -651,6 +658,7 @@ static void __init build_mem_type_table(
|
||||
}
|
||||
kern_pgprot |= PTE_EXT_AF;
|
||||
vecs_pgprot |= PTE_EXT_AF;
|
||||
+ mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
|
||||
|
||||
/*
|
||||
* Set PXN for user mappings
|
||||
@@ -679,6 +687,7 @@ static void __init build_mem_type_table(
|
||||
mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
|
||||
mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
|
||||
mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
|
||||
+ mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
|
||||
mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
|
||||
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
|
||||
mem_types[MT_ROM].prot_sect |= cp->pmd;
|
||||
--- a/arch/arm64/include/asm/cache.h
|
||||
+++ b/arch/arm64/include/asm/cache.h
|
||||
@@ -34,7 +34,7 @@
|
||||
#define ICACHE_POLICY_VIPT 2
|
||||
#define ICACHE_POLICY_PIPT 3
|
||||
|
||||
-#define L1_CACHE_SHIFT 7
|
||||
+#define L1_CACHE_SHIFT 6
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
|
||||
/*
|
||||
--- a/arch/arm64/include/asm/io.h
|
||||
+++ b/arch/arm64/include/asm/io.h
|
||||
@@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_
|
||||
#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
|
||||
#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
|
||||
#define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
|
||||
+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
|
||||
#define iounmap __iounmap
|
||||
|
||||
/*
|
||||
--- a/arch/arm64/include/asm/pgtable-prot.h
|
||||
+++ b/arch/arm64/include/asm/pgtable-prot.h
|
||||
@@ -48,6 +48,8 @@
|
||||
#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
|
||||
#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
|
||||
#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
|
||||
+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
|
||||
+
|
||||
|
||||
#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
|
||||
#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
|
||||
@@ -68,6 +70,7 @@
|
||||
#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
|
||||
|
||||
#define PAGE_S2 __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
|
||||
+#define PAGE_S2_NS __pgprot(PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDWR | PTE_TYPE_PAGE | PTE_AF)
|
||||
#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
|
||||
|
||||
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
|
||||
--- a/arch/arm64/include/asm/pgtable.h
|
||||
+++ b/arch/arm64/include/asm/pgtable.h
|
||||
@@ -377,6 +377,11 @@ static inline int pmd_protnone(pmd_t pmd
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
|
||||
#define pgprot_writecombine(prot) \
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
|
||||
+#define pgprot_cached(prot) \
|
||||
+ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
|
||||
+ PTE_PXN | PTE_UXN)
|
||||
+#define pgprot_cached_ns(prot) \
|
||||
+ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
|
||||
#define pgprot_device(prot) \
|
||||
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
|
||||
#define __HAVE_PHYS_MEM_ACCESS_PROT
|
||||
--- a/arch/arm64/mm/dma-mapping.c
|
||||
+++ b/arch/arm64/mm/dma-mapping.c
|
||||
@@ -937,3 +937,4 @@ void arch_setup_dma_ops(struct device *d
|
||||
}
|
||||
#endif
|
||||
}
|
||||
+EXPORT_SYMBOL(arch_setup_dma_ops);
|
||||
--- a/arch/arm64/mm/init.c
|
||||
+++ b/arch/arm64/mm/init.c
|
||||
@@ -457,6 +457,14 @@ void __init arm64_memblock_init(void)
|
||||
* Register the kernel text, kernel data, initrd, and initial
|
||||
* pagetables with memblock.
|
||||
*/
|
||||
+
|
||||
+ /* make this the first reservation so that there are no chances of
|
||||
+ * overlap
|
||||
+ */
|
||||
+ reserve_elfcorehdr();
|
||||
+
|
||||
+ reserve_crashkernel();
|
||||
+
|
||||
memblock_reserve(__pa_symbol(_text), _end - _text);
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
if (initrd_start) {
|
||||
@@ -476,10 +484,6 @@ void __init arm64_memblock_init(void)
|
||||
else
|
||||
arm64_dma_phys_limit = PHYS_MASK + 1;
|
||||
|
||||
- reserve_crashkernel();
|
||||
-
|
||||
- reserve_elfcorehdr();
|
||||
-
|
||||
high_memory = __va(memblock_end_of_DRAM() - 1) + 1;
|
||||
|
||||
dma_contiguous_reserve(arm64_dma_phys_limit);
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,96 @@
|
||||
From 263092cd68368ac6f030b847a1d5b0069bc2cef3 Mon Sep 17 00:00:00 2001
|
||||
From: Mathew McBride <matt@traverse.com.au>
|
||||
Date: Tue, 17 Apr 2018 10:01:03 +1000
|
||||
Subject: [PATCH 05/40] add DTS for Traverse LS1043 Boards
|
||||
|
||||
Signed-off-by: Mathew McBride <matt@traverse.com.au>
|
||||
---
|
||||
arch/arm64/boot/dts/freescale/Makefile | 5 +++-
|
||||
.../boot/dts/freescale/traverse-ls1043s.dts | 29 +++++++++++++++++++
|
||||
.../boot/dts/freescale/traverse-ls1043v.dts | 29 +++++++++++++++++++
|
||||
3 files changed, 62 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/Makefile
|
||||
+++ b/arch/arm64/boot/dts/freescale/Makefile
|
||||
@@ -22,7 +22,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
|
||||
-
|
||||
+
|
||||
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb
|
||||
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb
|
||||
+
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
--- a/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/traverse-ls1043s.dts
|
||||
@@ -330,3 +330,32 @@
|
||||
&sata {
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+/* Additions for Layerscape SDK (4.4/4.9) Kernel only
|
||||
+ * These kernels need additional setup for FMan/QMan DMA shared memory
|
||||
+ */
|
||||
+
|
||||
+#include "qoriq-qman-portals-sdk.dtsi"
|
||||
+#include "qoriq-bman-portals-sdk.dtsi"
|
||||
+
|
||||
+&bman_fbpr {
|
||||
+ compatible = "fsl,bman-fbpr";
|
||||
+ alloc-ranges = <0 0 0x10000 0>;
|
||||
+};
|
||||
+&qman_fqd {
|
||||
+ compatible = "fsl,qman-fqd";
|
||||
+ alloc-ranges = <0 0 0x10000 0>;
|
||||
+};
|
||||
+&qman_pfdr {
|
||||
+ compatible = "fsl,qman-pfdr";
|
||||
+ alloc-ranges = <0 0 0x10000 0>;
|
||||
+};
|
||||
+
|
||||
+&soc {
|
||||
+#include "qoriq-dpaa-eth.dtsi"
|
||||
+#include "qoriq-fman3-0-6oh.dtsi"
|
||||
+};
|
||||
+
|
||||
+&fman0 {
|
||||
+ compatible = "fsl,fman", "simple-bus";
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/traverse-ls1043v.dts
|
||||
@@ -251,3 +251,32 @@
|
||||
&sata {
|
||||
status = "disabled";
|
||||
};
|
||||
+
|
||||
+/* Additions for Layerscape SDK (4.4/4.9) Kernel only
|
||||
+ * These kernels need additional setup for FMan/QMan DMA shared memory
|
||||
+ */
|
||||
+
|
||||
+#include "qoriq-qman-portals-sdk.dtsi"
|
||||
+#include "qoriq-bman-portals-sdk.dtsi"
|
||||
+
|
||||
+&bman_fbpr {
|
||||
+ compatible = "fsl,bman-fbpr";
|
||||
+ alloc-ranges = <0 0 0x10000 0>;
|
||||
+};
|
||||
+&qman_fqd {
|
||||
+ compatible = "fsl,qman-fqd";
|
||||
+ alloc-ranges = <0 0 0x10000 0>;
|
||||
+};
|
||||
+&qman_pfdr {
|
||||
+ compatible = "fsl,qman-pfdr";
|
||||
+ alloc-ranges = <0 0 0x10000 0>;
|
||||
+};
|
||||
+
|
||||
+&soc {
|
||||
+#include "qoriq-dpaa-eth.dtsi"
|
||||
+#include "qoriq-fman3-0-6oh.dtsi"
|
||||
+};
|
||||
+
|
||||
+&fman0 {
|
||||
+ compatible = "fsl,fman", "simple-bus";
|
||||
+};
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
12062
target/linux/layerscape/patches-4.14/708-mc-bus-support-layerscape.patch
Normal file
12062
target/linux/layerscape/patches-4.14/708-mc-bus-support-layerscape.patch
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,550 @@
|
||||
From 48dbe4b3a31795b8efdfff82f69eccd086052eed Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Fri, 16 Nov 2018 10:27:30 +0800
|
||||
Subject: [PATCH 16/39] dpaa-bqman: support layerscape
|
||||
This is an integrated patch of dpaa-bqman for layerscape
|
||||
|
||||
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
|
||||
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
|
||||
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
|
||||
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
|
||||
Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/soc/fsl/qbman/Kconfig | 2 +-
|
||||
drivers/soc/fsl/qbman/bman.c | 24 ++++-
|
||||
drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++++++-
|
||||
drivers/soc/fsl/qbman/bman_portal.c | 12 ++-
|
||||
drivers/soc/fsl/qbman/bman_priv.h | 3 +
|
||||
drivers/soc/fsl/qbman/dpaa_sys.h | 8 +-
|
||||
drivers/soc/fsl/qbman/qman.c | 46 ++++++++-
|
||||
drivers/soc/fsl/qbman/qman_ccsr.c | 140 ++++++++++++++++++++++------
|
||||
drivers/soc/fsl/qbman/qman_portal.c | 12 ++-
|
||||
drivers/soc/fsl/qbman/qman_priv.h | 5 +-
|
||||
drivers/soc/fsl/qbman/qman_test.h | 2 -
|
||||
11 files changed, 236 insertions(+), 53 deletions(-)
|
||||
|
||||
--- a/drivers/soc/fsl/qbman/Kconfig
|
||||
+++ b/drivers/soc/fsl/qbman/Kconfig
|
||||
@@ -1,6 +1,6 @@
|
||||
menuconfig FSL_DPAA
|
||||
bool "Freescale DPAA 1.x support"
|
||||
- depends on FSL_SOC_BOOKE
|
||||
+ depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
|
||||
select GENERIC_ALLOCATOR
|
||||
help
|
||||
The Freescale Data Path Acceleration Architecture (DPAA) is a set of
|
||||
--- a/drivers/soc/fsl/qbman/bman.c
|
||||
+++ b/drivers/soc/fsl/qbman/bman.c
|
||||
@@ -35,6 +35,27 @@
|
||||
|
||||
/* Portal register assists */
|
||||
|
||||
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
|
||||
+/* Cache-inhibited register offsets */
|
||||
+#define BM_REG_RCR_PI_CINH 0x3000
|
||||
+#define BM_REG_RCR_CI_CINH 0x3100
|
||||
+#define BM_REG_RCR_ITR 0x3200
|
||||
+#define BM_REG_CFG 0x3300
|
||||
+#define BM_REG_SCN(n) (0x3400 + ((n) << 6))
|
||||
+#define BM_REG_ISR 0x3e00
|
||||
+#define BM_REG_IER 0x3e40
|
||||
+#define BM_REG_ISDR 0x3e80
|
||||
+#define BM_REG_IIR 0x3ec0
|
||||
+
|
||||
+/* Cache-enabled register offsets */
|
||||
+#define BM_CL_CR 0x0000
|
||||
+#define BM_CL_RR0 0x0100
|
||||
+#define BM_CL_RR1 0x0140
|
||||
+#define BM_CL_RCR 0x1000
|
||||
+#define BM_CL_RCR_PI_CENA 0x3000
|
||||
+#define BM_CL_RCR_CI_CENA 0x3100
|
||||
+
|
||||
+#else
|
||||
/* Cache-inhibited register offsets */
|
||||
#define BM_REG_RCR_PI_CINH 0x0000
|
||||
#define BM_REG_RCR_CI_CINH 0x0004
|
||||
@@ -53,6 +74,7 @@
|
||||
#define BM_CL_RCR 0x1000
|
||||
#define BM_CL_RCR_PI_CENA 0x3000
|
||||
#define BM_CL_RCR_CI_CENA 0x3100
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* Portal modes.
|
||||
@@ -607,7 +629,7 @@ int bman_p_irqsource_add(struct bman_por
|
||||
unsigned long irqflags;
|
||||
|
||||
local_irq_save(irqflags);
|
||||
- set_bits(bits & BM_PIRQ_VISIBLE, &p->irq_sources);
|
||||
+ p->irq_sources |= bits & BM_PIRQ_VISIBLE;
|
||||
bm_out(&p->p, BM_REG_IER, p->irq_sources);
|
||||
local_irq_restore(irqflags);
|
||||
return 0;
|
||||
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
|
||||
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
|
||||
@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platfor
|
||||
{
|
||||
int ret, err_irq;
|
||||
struct device *dev = &pdev->dev;
|
||||
- struct device_node *node = dev->of_node;
|
||||
+ struct device_node *mem_node, *node = dev->of_node;
|
||||
struct resource *res;
|
||||
u16 id, bm_pool_cnt;
|
||||
u8 major, minor;
|
||||
+ u64 size;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platfor
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * If FBPR memory wasn't defined using the qbman compatiable string
|
||||
+ * try using the of_reserved_mem_device method
|
||||
+ */
|
||||
+ if (!fbpr_a) {
|
||||
+ ret = of_reserved_mem_device_init(dev);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "of_reserved_mem_device_init() failed 0x%x\n",
|
||||
+ ret);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
|
||||
+ if (mem_node) {
|
||||
+ ret = of_property_read_u64(mem_node, "size", &size);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "FBPR: of_address_to_resource fails 0x%x\n",
|
||||
+ ret);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ fbpr_sz = size;
|
||||
+ } else {
|
||||
+ dev_err(dev, "No memory-region found for FBPR\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ if (!dma_zalloc_coherent(dev, fbpr_sz, &fbpr_a, 0)) {
|
||||
+ dev_err(dev, "Alloc FBPR memory failed\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
|
||||
+
|
||||
bm_set_memory(fbpr_a, fbpr_sz);
|
||||
|
||||
err_irq = platform_get_irq(pdev, 0);
|
||||
--- a/drivers/soc/fsl/qbman/bman_portal.c
|
||||
+++ b/drivers/soc/fsl/qbman/bman_portal.c
|
||||
@@ -123,7 +123,14 @@ static int bman_portal_probe(struct plat
|
||||
}
|
||||
pcfg->irq = irq;
|
||||
|
||||
- va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
|
||||
+#ifdef CONFIG_PPC
|
||||
+ /* PPC requires a cacheable/non-coherent mapping of the portal */
|
||||
+ va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
|
||||
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
|
||||
+#else
|
||||
+ /* For ARM we can use write combine mapping. */
|
||||
+ va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
|
||||
+#endif
|
||||
if (!va) {
|
||||
dev_err(dev, "ioremap::CE failed\n");
|
||||
goto err_ioremap1;
|
||||
@@ -131,8 +138,7 @@ static int bman_portal_probe(struct plat
|
||||
|
||||
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
|
||||
|
||||
- va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
|
||||
- _PAGE_GUARDED | _PAGE_NO_CACHE);
|
||||
+ va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
|
||||
if (!va) {
|
||||
dev_err(dev, "ioremap::CI failed\n");
|
||||
goto err_ioremap2;
|
||||
--- a/drivers/soc/fsl/qbman/bman_priv.h
|
||||
+++ b/drivers/soc/fsl/qbman/bman_priv.h
|
||||
@@ -33,6 +33,9 @@
|
||||
#include "dpaa_sys.h"
|
||||
|
||||
#include <soc/fsl/bman.h>
|
||||
+#include <linux/dma-contiguous.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/dma-mapping.h>
|
||||
|
||||
/* Portal processing (interrupt) sources */
|
||||
#define BM_PIRQ_RCRI 0x00000002 /* RCR Ring (below threshold) */
|
||||
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
|
||||
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
|
||||
@@ -44,20 +44,18 @@
|
||||
#include <linux/prefetch.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <asm/cacheflush.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/delay.h>
|
||||
|
||||
/* For 2-element tables related to cache-inhibited and cache-enabled mappings */
|
||||
#define DPAA_PORTAL_CE 0
|
||||
#define DPAA_PORTAL_CI 1
|
||||
|
||||
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
|
||||
-#error "Unsupported Cacheline Size"
|
||||
-#endif
|
||||
-
|
||||
static inline void dpaa_flush(void *p)
|
||||
{
|
||||
#ifdef CONFIG_PPC
|
||||
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
|
||||
-#elif defined(CONFIG_ARM32)
|
||||
+#elif defined(CONFIG_ARM)
|
||||
__cpuc_flush_dcache_area(p, 64);
|
||||
#elif defined(CONFIG_ARM64)
|
||||
__flush_dcache_area(p, 64);
|
||||
--- a/drivers/soc/fsl/qbman/qman.c
|
||||
+++ b/drivers/soc/fsl/qbman/qman.c
|
||||
@@ -41,6 +41,43 @@
|
||||
|
||||
/* Portal register assists */
|
||||
|
||||
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
|
||||
+/* Cache-inhibited register offsets */
|
||||
+#define QM_REG_EQCR_PI_CINH 0x3000
|
||||
+#define QM_REG_EQCR_CI_CINH 0x3040
|
||||
+#define QM_REG_EQCR_ITR 0x3080
|
||||
+#define QM_REG_DQRR_PI_CINH 0x3100
|
||||
+#define QM_REG_DQRR_CI_CINH 0x3140
|
||||
+#define QM_REG_DQRR_ITR 0x3180
|
||||
+#define QM_REG_DQRR_DCAP 0x31C0
|
||||
+#define QM_REG_DQRR_SDQCR 0x3200
|
||||
+#define QM_REG_DQRR_VDQCR 0x3240
|
||||
+#define QM_REG_DQRR_PDQCR 0x3280
|
||||
+#define QM_REG_MR_PI_CINH 0x3300
|
||||
+#define QM_REG_MR_CI_CINH 0x3340
|
||||
+#define QM_REG_MR_ITR 0x3380
|
||||
+#define QM_REG_CFG 0x3500
|
||||
+#define QM_REG_ISR 0x3600
|
||||
+#define QM_REG_IER 0x3640
|
||||
+#define QM_REG_ISDR 0x3680
|
||||
+#define QM_REG_IIR 0x36C0
|
||||
+#define QM_REG_ITPR 0x3740
|
||||
+
|
||||
+/* Cache-enabled register offsets */
|
||||
+#define QM_CL_EQCR 0x0000
|
||||
+#define QM_CL_DQRR 0x1000
|
||||
+#define QM_CL_MR 0x2000
|
||||
+#define QM_CL_EQCR_PI_CENA 0x3000
|
||||
+#define QM_CL_EQCR_CI_CENA 0x3040
|
||||
+#define QM_CL_DQRR_PI_CENA 0x3100
|
||||
+#define QM_CL_DQRR_CI_CENA 0x3140
|
||||
+#define QM_CL_MR_PI_CENA 0x3300
|
||||
+#define QM_CL_MR_CI_CENA 0x3340
|
||||
+#define QM_CL_CR 0x3800
|
||||
+#define QM_CL_RR0 0x3900
|
||||
+#define QM_CL_RR1 0x3940
|
||||
+
|
||||
+#else
|
||||
/* Cache-inhibited register offsets */
|
||||
#define QM_REG_EQCR_PI_CINH 0x0000
|
||||
#define QM_REG_EQCR_CI_CINH 0x0004
|
||||
@@ -75,6 +112,7 @@
|
||||
#define QM_CL_CR 0x3800
|
||||
#define QM_CL_RR0 0x3900
|
||||
#define QM_CL_RR1 0x3940
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* BTW, the drivers (and h/w programming model) already obtain the required
|
||||
@@ -909,12 +947,12 @@ static inline int qm_mc_result_timeout(s
|
||||
|
||||
static inline void fq_set(struct qman_fq *fq, u32 mask)
|
||||
{
|
||||
- set_bits(mask, &fq->flags);
|
||||
+ fq->flags |= mask;
|
||||
}
|
||||
|
||||
static inline void fq_clear(struct qman_fq *fq, u32 mask)
|
||||
{
|
||||
- clear_bits(mask, &fq->flags);
|
||||
+ fq->flags &= ~mask;
|
||||
}
|
||||
|
||||
static inline int fq_isset(struct qman_fq *fq, u32 mask)
|
||||
@@ -1566,7 +1604,7 @@ void qman_p_irqsource_add(struct qman_po
|
||||
unsigned long irqflags;
|
||||
|
||||
local_irq_save(irqflags);
|
||||
- set_bits(bits & QM_PIRQ_VISIBLE, &p->irq_sources);
|
||||
+ p->irq_sources |= bits & QM_PIRQ_VISIBLE;
|
||||
qm_out(&p->p, QM_REG_IER, p->irq_sources);
|
||||
local_irq_restore(irqflags);
|
||||
}
|
||||
@@ -1589,7 +1627,7 @@ void qman_p_irqsource_remove(struct qman
|
||||
*/
|
||||
local_irq_save(irqflags);
|
||||
bits &= QM_PIRQ_VISIBLE;
|
||||
- clear_bits(bits, &p->irq_sources);
|
||||
+ p->irq_sources &= ~bits;
|
||||
qm_out(&p->p, QM_REG_IER, p->irq_sources);
|
||||
ier = qm_in(&p->p, QM_REG_IER);
|
||||
/*
|
||||
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
|
||||
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
|
||||
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *d
|
||||
}
|
||||
|
||||
/*
|
||||
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
|
||||
- * (especially if iommu translations ever get involved). Unfortunately, the
|
||||
- * DMA API currently does not allow mapping anything that is not backed with
|
||||
- * a struct page.
|
||||
+ * QMan needs two global memory areas initialized at boot time:
|
||||
+ * 1) FQD: Frame Queue Descriptors used to manage frame queues
|
||||
+ * 2) PFDR: Packed Frame Queue Descriptor Records used to store frames
|
||||
+ * Both areas are reserved using the device tree reserved memory framework
|
||||
+ * and the addresses and sizes are initialized when the QMan device is probed
|
||||
*/
|
||||
static dma_addr_t fqd_a, pfdr_a;
|
||||
static size_t fqd_sz, pfdr_sz;
|
||||
|
||||
+#ifdef CONFIG_PPC
|
||||
+/*
|
||||
+ * Support for PPC Device Tree backward compatibility when compatiable
|
||||
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
|
||||
+ */
|
||||
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
|
||||
+{
|
||||
+ /* map as cacheable, non-guarded */
|
||||
+ void __iomem *tmpp = ioremap_prot(addr, sz, 0);
|
||||
+
|
||||
+ if (!tmpp)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ memset_io(tmpp, 0, sz);
|
||||
+ flush_dcache_range((unsigned long)tmpp,
|
||||
+ (unsigned long)tmpp + sz);
|
||||
+ iounmap(tmpp);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int qman_fqd(struct reserved_mem *rmem)
|
||||
{
|
||||
fqd_a = rmem->base;
|
||||
fqd_sz = rmem->size;
|
||||
|
||||
WARN_ON(!(fqd_a && fqd_sz));
|
||||
-
|
||||
return 0;
|
||||
}
|
||||
RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
|
||||
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem
|
||||
}
|
||||
RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
|
||||
|
||||
+#endif
|
||||
+
|
||||
static unsigned int qm_get_fqid_maxcnt(void)
|
||||
{
|
||||
return fqd_sz / 64;
|
||||
}
|
||||
|
||||
-/*
|
||||
- * Flush this memory range from data cache so that QMAN originated
|
||||
- * transactions for this memory region could be marked non-coherent.
|
||||
- */
|
||||
-static int zero_priv_mem(struct device *dev, struct device_node *node,
|
||||
- phys_addr_t addr, size_t sz)
|
||||
-{
|
||||
- /* map as cacheable, non-guarded */
|
||||
- void __iomem *tmpp = ioremap_prot(addr, sz, 0);
|
||||
-
|
||||
- if (!tmpp)
|
||||
- return -ENOMEM;
|
||||
-
|
||||
- memset_io(tmpp, 0, sz);
|
||||
- flush_dcache_range((unsigned long)tmpp,
|
||||
- (unsigned long)tmpp + sz);
|
||||
- iounmap(tmpp);
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
static void log_edata_bits(struct device *dev, u32 bit_count)
|
||||
{
|
||||
u32 i, j, mask = 0xffffffff;
|
||||
@@ -687,11 +689,12 @@ static int qman_resource_init(struct dev
|
||||
static int fsl_qman_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
- struct device_node *node = dev->of_node;
|
||||
+ struct device_node *mem_node, *node = dev->of_node;
|
||||
struct resource *res;
|
||||
int ret, err_irq;
|
||||
u16 id;
|
||||
u8 major, minor;
|
||||
+ u64 size;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
@@ -717,6 +720,8 @@ static int fsl_qman_probe(struct platfor
|
||||
qman_ip_rev = QMAN_REV30;
|
||||
else if (major == 3 && minor == 1)
|
||||
qman_ip_rev = QMAN_REV31;
|
||||
+ else if (major == 3 && minor == 2)
|
||||
+ qman_ip_rev = QMAN_REV32;
|
||||
else {
|
||||
dev_err(dev, "Unknown QMan version\n");
|
||||
return -ENODEV;
|
||||
@@ -727,10 +732,83 @@ static int fsl_qman_probe(struct platfor
|
||||
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
|
||||
}
|
||||
|
||||
- ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
|
||||
- WARN_ON(ret);
|
||||
- if (ret)
|
||||
- return -ENODEV;
|
||||
+ if (fqd_a) {
|
||||
+#ifdef CONFIG_PPC
|
||||
+ /*
|
||||
+ * For PPC backward DT compatibility
|
||||
+ * FQD memory MUST be zero'd by software
|
||||
+ */
|
||||
+ zero_priv_mem(fqd_a, fqd_sz);
|
||||
+#else
|
||||
+ WARN(1, "Unexpected archiceture using non shared-dma-mem reservations");
|
||||
+#endif
|
||||
+ } else {
|
||||
+ /*
|
||||
+ * Order of memory regions is assumed as FQD followed by PFDR
|
||||
+ * in order to ensure allocations from the correct regions the
|
||||
+ * driver initializes then allocates each piece in order
|
||||
+ */
|
||||
+ ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "of_reserved_mem_device_init_by_idx(0) failed 0x%x\n",
|
||||
+ ret);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
|
||||
+ if (mem_node) {
|
||||
+ ret = of_property_read_u64(mem_node, "size", &size);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "FQD: of_address_to_resource fails 0x%x\n",
|
||||
+ ret);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ fqd_sz = size;
|
||||
+ } else {
|
||||
+ dev_err(dev, "No memory-region found for FQD\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ if (!dma_zalloc_coherent(dev, fqd_sz, &fqd_a, 0)) {
|
||||
+ dev_err(dev, "Alloc FQD memory failed\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Disassociate the FQD reserved memory area from the device
|
||||
+ * because a device can only have one DMA memory area. This
|
||||
+ * should be fine since the memory is allocated and initialized
|
||||
+ * and only ever accessed by the QMan device from now on
|
||||
+ */
|
||||
+ of_reserved_mem_device_release(dev);
|
||||
+ }
|
||||
+ dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
|
||||
+
|
||||
+ if (!pfdr_a) {
|
||||
+ /* Setup PFDR memory */
|
||||
+ ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 1);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "of_reserved_mem_device_init(1) failed 0x%x\n",
|
||||
+ ret);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ mem_node = of_parse_phandle(dev->of_node, "memory-region", 1);
|
||||
+ if (mem_node) {
|
||||
+ ret = of_property_read_u64(mem_node, "size", &size);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "PFDR: of_address_to_resource fails 0x%x\n",
|
||||
+ ret);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ pfdr_sz = size;
|
||||
+ } else {
|
||||
+ dev_err(dev, "No memory-region found for PFDR\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ if (!dma_zalloc_coherent(dev, pfdr_sz, &pfdr_a, 0)) {
|
||||
+ dev_err(dev, "Alloc PFDR Failed size 0x%zx\n", pfdr_sz);
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+ }
|
||||
+ dev_info(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
|
||||
|
||||
ret = qman_init_ccsr(dev);
|
||||
if (ret) {
|
||||
--- a/drivers/soc/fsl/qbman/qman_portal.c
|
||||
+++ b/drivers/soc/fsl/qbman/qman_portal.c
|
||||
@@ -262,7 +262,14 @@ static int qman_portal_probe(struct plat
|
||||
}
|
||||
pcfg->irq = irq;
|
||||
|
||||
- va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
|
||||
+#ifdef CONFIG_PPC
|
||||
+ /* PPC requires a cacheable/non-coherent mapping of the portal */
|
||||
+ va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
|
||||
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
|
||||
+#else
|
||||
+ /* For ARM we can use write combine mapping. */
|
||||
+ va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
|
||||
+#endif
|
||||
if (!va) {
|
||||
dev_err(dev, "ioremap::CE failed\n");
|
||||
goto err_ioremap1;
|
||||
@@ -270,8 +277,7 @@ static int qman_portal_probe(struct plat
|
||||
|
||||
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
|
||||
|
||||
- va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
|
||||
- _PAGE_GUARDED | _PAGE_NO_CACHE);
|
||||
+ va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
|
||||
if (!va) {
|
||||
dev_err(dev, "ioremap::CI failed\n");
|
||||
goto err_ioremap2;
|
||||
--- a/drivers/soc/fsl/qbman/qman_priv.h
|
||||
+++ b/drivers/soc/fsl/qbman/qman_priv.h
|
||||
@@ -28,13 +28,13 @@
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
-
|
||||
#include "dpaa_sys.h"
|
||||
|
||||
#include <soc/fsl/qman.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/iommu.h>
|
||||
+#include <linux/dma-contiguous.h>
|
||||
+#include <linux/of_address.h>
|
||||
|
||||
#if defined(CONFIG_FSL_PAMU)
|
||||
#include <asm/fsl_pamu_stash.h>
|
||||
@@ -187,6 +187,7 @@ struct qm_portal_config {
|
||||
#define QMAN_REV20 0x0200
|
||||
#define QMAN_REV30 0x0300
|
||||
#define QMAN_REV31 0x0301
|
||||
+#define QMAN_REV32 0x0302
|
||||
extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
|
||||
|
||||
#define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
|
||||
--- a/drivers/soc/fsl/qbman/qman_test.h
|
||||
+++ b/drivers/soc/fsl/qbman/qman_test.h
|
||||
@@ -30,7 +30,5 @@
|
||||
|
||||
#include "qman_priv.h"
|
||||
|
||||
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
-
|
||||
int qman_test_stash(void);
|
||||
int qman_test_api(void);
|
||||
@ -0,0 +1,62 @@
|
||||
From b3544990f8496edda965e1ff9a14727360660676 Mon Sep 17 00:00:00 2001
|
||||
From: Mathew McBride <matt@traverse.com.au>
|
||||
Date: Mon, 7 Aug 2017 10:19:48 +1000
|
||||
Subject: [PATCH] Recognize when an RGMII Link is set as fixed (in the device
|
||||
tree) and set up the MAC accordingly
|
||||
|
||||
---
|
||||
drivers/net/ethernet/freescale/sdk_dpaa/mac.c | 1 +
|
||||
.../freescale/sdk_fman/Peripherals/FM/MAC/memac.c | 13 +++++++++++++
|
||||
2 files changed, 14 insertions(+)
|
||||
|
||||
--- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
|
||||
+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
|
||||
@@ -386,6 +386,7 @@ static int __cold mac_probe(struct platf
|
||||
mac_dev->fixed_link->duplex = phy->duplex;
|
||||
mac_dev->fixed_link->pause = phy->pause;
|
||||
mac_dev->fixed_link->asym_pause = phy->asym_pause;
|
||||
+ printk(KERN_INFO "Setting up fixed link, speed %d duplex %d\n", mac_dev->fixed_link->speed, mac_dev->fixed_link->duplex);
|
||||
}
|
||||
|
||||
_errno = mac_dev->init(mac_dev);
|
||||
--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
|
||||
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
|
||||
@@ -36,6 +36,8 @@
|
||||
|
||||
@Description FM mEMAC driver
|
||||
*//***************************************************************************/
|
||||
+#include <../../../../sdk_dpaa/mac.h>
|
||||
+#include <linux/phy_fixed.h>
|
||||
|
||||
#include "std_ext.h"
|
||||
#include "string_ext.h"
|
||||
@@ -48,6 +50,8 @@
|
||||
#include "memac.h"
|
||||
|
||||
|
||||
+static t_Error MemacAdjustLink(t_Handle h_Memac, e_EnetSpeed speed, bool fullDuplex);
|
||||
+
|
||||
/*****************************************************************************/
|
||||
/* Internal routines */
|
||||
/*****************************************************************************/
|
||||
@@ -276,11 +280,20 @@ static t_Error MemacEnable(t_Handle h_Me
|
||||
{
|
||||
t_Memac *p_Memac = (t_Memac *)h_Memac;
|
||||
|
||||
+ struct mac_device *mac_dev = (struct mac_device *)p_Memac->h_App;
|
||||
+
|
||||
SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
|
||||
SANITY_CHECK_RETURN_ERROR(!p_Memac->p_MemacDriverParam, E_INVALID_STATE);
|
||||
|
||||
fman_memac_enable(p_Memac->p_MemMap, (mode & e_COMM_MODE_RX), (mode & e_COMM_MODE_TX));
|
||||
|
||||
+ if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_RGMII) {
|
||||
+ if (mac_dev->fixed_link) {
|
||||
+ printk(KERN_INFO "This is a fixed-link, forcing speed %d duplex %d\n",mac_dev->fixed_link->speed,mac_dev->fixed_link->duplex);
|
||||
+ MemacAdjustLink(h_Memac,mac_dev->fixed_link->speed,mac_dev->fixed_link->duplex);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return E_OK;
|
||||
}
|
||||
|
||||
@ -0,0 +1,68 @@
|
||||
From 918f966af1f0e42ff8ac298e1d7d02e67afcfab4 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:27:42 +0800
|
||||
Subject: [PATCH 18/40] sata: support layerscape
|
||||
This is an integrated patch of sata for layerscape
|
||||
|
||||
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/ata/ahci_qoriq.c | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/drivers/ata/ahci_qoriq.c
|
||||
+++ b/drivers/ata/ahci_qoriq.c
|
||||
@@ -35,6 +35,8 @@
|
||||
|
||||
/* port register default value */
|
||||
#define AHCI_PORT_PHY_1_CFG 0xa003fffe
|
||||
+#define AHCI_PORT_PHY2_CFG 0x28184d1f
|
||||
+#define AHCI_PORT_PHY3_CFG 0x0e081509
|
||||
#define AHCI_PORT_TRANS_CFG 0x08000029
|
||||
#define AHCI_PORT_AXICC_CFG 0x3fffffff
|
||||
|
||||
@@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ah
|
||||
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
|
||||
qpriv->ecc_addr);
|
||||
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
|
||||
+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
|
||||
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
if (qpriv->is_dmacoherent)
|
||||
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
|
||||
@@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ah
|
||||
|
||||
case AHCI_LS2080A:
|
||||
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
|
||||
+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
|
||||
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
if (qpriv->is_dmacoherent)
|
||||
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
|
||||
@@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ah
|
||||
writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
|
||||
qpriv->ecc_addr);
|
||||
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
|
||||
+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
|
||||
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
if (qpriv->is_dmacoherent)
|
||||
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
|
||||
@@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ah
|
||||
writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
|
||||
qpriv->ecc_addr);
|
||||
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
|
||||
+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
|
||||
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
if (qpriv->is_dmacoherent)
|
||||
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
|
||||
@@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ah
|
||||
|
||||
case AHCI_LS2088A:
|
||||
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
|
||||
+ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
|
||||
+ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
|
||||
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
|
||||
if (qpriv->is_dmacoherent)
|
||||
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,449 @@
|
||||
From d586effc9b71ddf240fb294b1ab1205bbe6fec4b Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:32 +0800
|
||||
Subject: [PATCH 20/40] flextimer: support layerscape
|
||||
This is an integrated patch of flextimer for layerscape
|
||||
|
||||
Signed-off-by: Meng Yi <meng.yi@nxp.com>
|
||||
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
|
||||
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
.../bindings/soc/fsl/layerscape/ftm-alarm.txt | 32 ++
|
||||
drivers/clocksource/fsl_ftm_timer.c | 8 +-
|
||||
drivers/soc/fsl/layerscape/ftm_alarm.c | 375 ++++++++++++++++++
|
||||
3 files changed, 411 insertions(+), 4 deletions(-)
|
||||
create mode 100644 Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
|
||||
create mode 100644 drivers/soc/fsl/layerscape/ftm_alarm.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
|
||||
@@ -0,0 +1,32 @@
|
||||
+Freescale FlexTimer Module (FTM) Alarm
|
||||
+
|
||||
+Required properties:
|
||||
+
|
||||
+- compatible : Should be "fsl,ftm-alarm" or "fsl,<chip>-ftm-alarm", the
|
||||
+ supported chips include
|
||||
+ "fsl,ls1012a-ftm-alarm"
|
||||
+ "fsl,ls1021a-ftm-alarm"
|
||||
+ "fsl,ls1043a-ftm-alarm"
|
||||
+ "fsl,ls1046a-ftm-alarm"
|
||||
+ "fsl,ls1088a-ftm-alarm"
|
||||
+ "fsl,ls208xa-ftm-alarm"
|
||||
+- reg : Specifies base physical address and size of the register sets for the
|
||||
+ FlexTimer Module and base physical address of IP Powerdown Exception Control
|
||||
+ Register.
|
||||
+- reg-names: names of the mapped memory regions listed in regs property.
|
||||
+ should include the following entries:
|
||||
+ "ftm": Address of the register sets for FlexTimer Module
|
||||
+ "pmctrl": Address of IP Powerdown Exception Control register
|
||||
+- interrupts : Should be the FlexTimer Module interrupt.
|
||||
+- big-endian: If the host controller is big-endian mode, specify this property.
|
||||
+ The default endian mode is little-endian.
|
||||
+
|
||||
+Example:
|
||||
+ftm0: ftm0@29d0000 {
|
||||
+ compatible = "fsl,ls1043a-ftm-alarm";
|
||||
+ reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
+ <0x0 0x1ee2140 0x0 0x4>;
|
||||
+ reg-names = "ftm", "pmctrl";
|
||||
+ interrupts = <0 86 0x4>;
|
||||
+ big-endian;
|
||||
+};
|
||||
--- a/drivers/clocksource/fsl_ftm_timer.c
|
||||
+++ b/drivers/clocksource/fsl_ftm_timer.c
|
||||
@@ -83,11 +83,11 @@ static inline void ftm_counter_disable(v
|
||||
|
||||
static inline void ftm_irq_acknowledge(void __iomem *base)
|
||||
{
|
||||
- u32 val;
|
||||
+ unsigned int timeout = 100;
|
||||
|
||||
- val = ftm_readl(base + FTM_SC);
|
||||
- val &= ~FTM_SC_TOF;
|
||||
- ftm_writel(val, base + FTM_SC);
|
||||
+ while ((FTM_SC_TOF & ftm_readl(base + FTM_SC)) && timeout--)
|
||||
+ ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF),
|
||||
+ base + FTM_SC);
|
||||
}
|
||||
|
||||
static inline void ftm_irq_enable(void __iomem *base)
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
|
||||
@@ -0,0 +1,375 @@
|
||||
+/*
|
||||
+ * Freescale FlexTimer Module (FTM) Alarm driver.
|
||||
+ *
|
||||
+ * Copyright 2014 Freescale Semiconductor, Inc.
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or
|
||||
+ * modify it under the terms of the GNU General Public License
|
||||
+ * as published by the Free Software Foundation; either version 2
|
||||
+ * of the License, or (at your option) any later version.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/err.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/libata.h>
|
||||
+#include <linux/module.h>
|
||||
+
|
||||
+#define FTM_SC 0x00
|
||||
+#define FTM_SC_CLK_SHIFT 3
|
||||
+#define FTM_SC_CLK_MASK (0x3 << FTM_SC_CLK_SHIFT)
|
||||
+#define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_SHIFT)
|
||||
+#define FTM_SC_PS_MASK 0x7
|
||||
+#define FTM_SC_TOIE BIT(6)
|
||||
+#define FTM_SC_TOF BIT(7)
|
||||
+
|
||||
+#define FTM_SC_CLKS_FIXED_FREQ 0x02
|
||||
+
|
||||
+#define FTM_CNT 0x04
|
||||
+#define FTM_MOD 0x08
|
||||
+#define FTM_CNTIN 0x4C
|
||||
+
|
||||
+#define FIXED_FREQ_CLK 32000
|
||||
+#define MAX_FREQ_DIV (1 << FTM_SC_PS_MASK)
|
||||
+#define MAX_COUNT_VAL 0xffff
|
||||
+
|
||||
+static void __iomem *ftm1_base;
|
||||
+static void __iomem *rcpm_ftm_addr;
|
||||
+static void __iomem *scfg_scrachpad_addr;
|
||||
+static u32 alarm_freq;
|
||||
+static bool big_endian;
|
||||
+
|
||||
+enum pmu_endian_type {
|
||||
+ BIG_ENDIAN,
|
||||
+ LITTLE_ENDIAN,
|
||||
+};
|
||||
+
|
||||
+struct rcpm_cfg {
|
||||
+ enum pmu_endian_type big_endian; /* Big/Little endian of PMU module */
|
||||
+ u32 flextimer_set_bit; /* FTM is not powerdown during device LPM20 */
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_cfg ls1012a_rcpm_cfg = {
|
||||
+ .big_endian = BIG_ENDIAN,
|
||||
+ .flextimer_set_bit = 0x20000,
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_cfg ls1021a_rcpm_cfg = {
|
||||
+ .big_endian = BIG_ENDIAN,
|
||||
+ .flextimer_set_bit = 0x30000000,
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_cfg ls1043a_rcpm_cfg = {
|
||||
+ .big_endian = BIG_ENDIAN,
|
||||
+ .flextimer_set_bit = 0x20000,
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_cfg ls1046a_rcpm_cfg = {
|
||||
+ .big_endian = BIG_ENDIAN,
|
||||
+ .flextimer_set_bit = 0x20000,
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_cfg ls1088a_rcpm_cfg = {
|
||||
+ .big_endian = LITTLE_ENDIAN,
|
||||
+ .flextimer_set_bit = 0x4000,
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_cfg ls208xa_rcpm_cfg = {
|
||||
+ .big_endian = LITTLE_ENDIAN,
|
||||
+ .flextimer_set_bit = 0x4000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id ippdexpcr_of_match[] = {
|
||||
+ { .compatible = "fsl,ls1012a-ftm-alarm", .data = &ls1012a_rcpm_cfg},
|
||||
+ { .compatible = "fsl,ls1021a-ftm-alarm", .data = &ls1021a_rcpm_cfg},
|
||||
+ { .compatible = "fsl,ls1043a-ftm-alarm", .data = &ls1043a_rcpm_cfg},
|
||||
+ { .compatible = "fsl,ls1046a-ftm-alarm", .data = &ls1046a_rcpm_cfg},
|
||||
+ { .compatible = "fsl,ls1088a-ftm-alarm", .data = &ls1088a_rcpm_cfg},
|
||||
+ { .compatible = "fsl,ls208xa-ftm-alarm", .data = &ls208xa_rcpm_cfg},
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, ippdexpcr_of_match);
|
||||
+
|
||||
+static inline u32 ftm_readl(void __iomem *addr)
|
||||
+{
|
||||
+ if (big_endian)
|
||||
+ return ioread32be(addr);
|
||||
+
|
||||
+ return ioread32(addr);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_writel(u32 val, void __iomem *addr)
|
||||
+{
|
||||
+ if (big_endian)
|
||||
+ iowrite32be(val, addr);
|
||||
+ else
|
||||
+ iowrite32(val, addr);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_counter_enable(void __iomem *base)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ /* select and enable counter clock source */
|
||||
+ val = ftm_readl(base + FTM_SC);
|
||||
+ val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
|
||||
+ val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
|
||||
+ ftm_writel(val, base + FTM_SC);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_counter_disable(void __iomem *base)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ /* disable counter clock source */
|
||||
+ val = ftm_readl(base + FTM_SC);
|
||||
+ val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
|
||||
+ ftm_writel(val, base + FTM_SC);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_irq_acknowledge(void __iomem *base)
|
||||
+{
|
||||
+ unsigned int timeout = 100;
|
||||
+
|
||||
+ while ((FTM_SC_TOF & ftm_readl(base + FTM_SC)) && timeout--)
|
||||
+ ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF),
|
||||
+ base + FTM_SC);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_irq_enable(void __iomem *base)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = ftm_readl(base + FTM_SC);
|
||||
+ val |= FTM_SC_TOIE;
|
||||
+ ftm_writel(val, base + FTM_SC);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_irq_disable(void __iomem *base)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = ftm_readl(base + FTM_SC);
|
||||
+ val &= ~FTM_SC_TOIE;
|
||||
+ ftm_writel(val, base + FTM_SC);
|
||||
+}
|
||||
+
|
||||
+static inline void ftm_reset_counter(void __iomem *base)
|
||||
+{
|
||||
+ /*
|
||||
+ * The CNT register contains the FTM counter value.
|
||||
+ * Reset clears the CNT register. Writing any value to COUNT
|
||||
+ * updates the counter with its initial value, CNTIN.
|
||||
+ */
|
||||
+ ftm_writel(0x00, base + FTM_CNT);
|
||||
+}
|
||||
+
|
||||
+static u32 time_to_cycle(unsigned long time)
|
||||
+{
|
||||
+ u32 cycle;
|
||||
+
|
||||
+ cycle = time * alarm_freq;
|
||||
+ if (cycle > MAX_COUNT_VAL) {
|
||||
+ pr_err("Out of alarm range.\n");
|
||||
+ cycle = 0;
|
||||
+ }
|
||||
+
|
||||
+ return cycle;
|
||||
+}
|
||||
+
|
||||
+static u32 cycle_to_time(u32 cycle)
|
||||
+{
|
||||
+ return cycle / alarm_freq + 1;
|
||||
+}
|
||||
+
|
||||
+static void ftm_clean_alarm(void)
|
||||
+{
|
||||
+ ftm_counter_disable(ftm1_base);
|
||||
+
|
||||
+ ftm_writel(0x00, ftm1_base + FTM_CNTIN);
|
||||
+ ftm_writel(~0U, ftm1_base + FTM_MOD);
|
||||
+
|
||||
+ ftm_reset_counter(ftm1_base);
|
||||
+}
|
||||
+
|
||||
+static int ftm_set_alarm(u64 cycle)
|
||||
+{
|
||||
+ ftm_irq_disable(ftm1_base);
|
||||
+
|
||||
+ /*
|
||||
+ * The counter increments until the value of MOD is reached,
|
||||
+ * at which point the counter is reloaded with the value of CNTIN.
|
||||
+ * The TOF (the overflow flag) bit is set when the FTM counter
|
||||
+ * changes from MOD to CNTIN. So we should using the cycle - 1.
|
||||
+ */
|
||||
+ ftm_writel(cycle - 1, ftm1_base + FTM_MOD);
|
||||
+
|
||||
+ ftm_counter_enable(ftm1_base);
|
||||
+
|
||||
+ ftm_irq_enable(ftm1_base);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t ftm_alarm_interrupt(int irq, void *dev_id)
|
||||
+{
|
||||
+ ftm_irq_acknowledge(ftm1_base);
|
||||
+ ftm_irq_disable(ftm1_base);
|
||||
+ ftm_clean_alarm();
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+static ssize_t ftm_alarm_show(struct device *dev,
|
||||
+ struct device_attribute *attr,
|
||||
+ char *buf)
|
||||
+{
|
||||
+ u32 count, val;
|
||||
+
|
||||
+ count = ftm_readl(ftm1_base + FTM_MOD);
|
||||
+ val = ftm_readl(ftm1_base + FTM_CNT);
|
||||
+ val = (count & MAX_COUNT_VAL) - val;
|
||||
+ val = cycle_to_time(val);
|
||||
+
|
||||
+ return sprintf(buf, "%u\n", val);
|
||||
+}
|
||||
+
|
||||
+static ssize_t ftm_alarm_store(struct device *dev,
|
||||
+ struct device_attribute *attr,
|
||||
+ const char *buf, size_t count)
|
||||
+{
|
||||
+ u32 cycle;
|
||||
+ unsigned long time;
|
||||
+
|
||||
+ if (kstrtoul(buf, 0, &time))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ftm_clean_alarm();
|
||||
+
|
||||
+ cycle = time_to_cycle(time);
|
||||
+ if (!cycle)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ftm_set_alarm(cycle);
|
||||
+
|
||||
+ return count;
|
||||
+}
|
||||
+
|
||||
+static struct device_attribute ftm_alarm_attributes = __ATTR(ftm_alarm, 0644,
|
||||
+ ftm_alarm_show, ftm_alarm_store);
|
||||
+
|
||||
+static int ftm_alarm_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ struct resource *r;
|
||||
+ int irq;
|
||||
+ int ret;
|
||||
+ struct rcpm_cfg *rcpm_cfg;
|
||||
+ u32 ippdexpcr, flextimer;
|
||||
+ const struct of_device_id *of_id;
|
||||
+ enum pmu_endian_type endian;
|
||||
+
|
||||
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (!r)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ ftm1_base = devm_ioremap_resource(&pdev->dev, r);
|
||||
+ if (IS_ERR(ftm1_base))
|
||||
+ return PTR_ERR(ftm1_base);
|
||||
+
|
||||
+ of_id = of_match_node(ippdexpcr_of_match, np);
|
||||
+ if (!of_id)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ rcpm_cfg = devm_kzalloc(&pdev->dev, sizeof(*rcpm_cfg), GFP_KERNEL);
|
||||
+ if (!rcpm_cfg)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ rcpm_cfg = (struct rcpm_cfg *)of_id->data;
|
||||
+ endian = rcpm_cfg->big_endian;
|
||||
+ flextimer = rcpm_cfg->flextimer_set_bit;
|
||||
+
|
||||
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmctrl");
|
||||
+ if (r) {
|
||||
+ rcpm_ftm_addr = devm_ioremap_resource(&pdev->dev, r);
|
||||
+ if (IS_ERR(rcpm_ftm_addr))
|
||||
+ return PTR_ERR(rcpm_ftm_addr);
|
||||
+ if (endian == BIG_ENDIAN)
|
||||
+ ippdexpcr = ioread32be(rcpm_ftm_addr);
|
||||
+ else
|
||||
+ ippdexpcr = ioread32(rcpm_ftm_addr);
|
||||
+ ippdexpcr |= flextimer;
|
||||
+ if (endian == BIG_ENDIAN)
|
||||
+ iowrite32be(ippdexpcr, rcpm_ftm_addr);
|
||||
+ else
|
||||
+ iowrite32(ippdexpcr, rcpm_ftm_addr);
|
||||
+
|
||||
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scrachpad");
|
||||
+ if (r) {
|
||||
+ scfg_scrachpad_addr = devm_ioremap_resource(&pdev->dev, r);
|
||||
+ iowrite32(ippdexpcr, scfg_scrachpad_addr);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ irq = irq_of_parse_and_map(np, 0);
|
||||
+ if (irq <= 0) {
|
||||
+ pr_err("ftm: unable to get IRQ from DT, %d\n", irq);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ big_endian = of_property_read_bool(np, "big-endian");
|
||||
+
|
||||
+ ret = devm_request_irq(&pdev->dev, irq, ftm_alarm_interrupt,
|
||||
+ IRQF_NO_SUSPEND, dev_name(&pdev->dev), NULL);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(&pdev->dev, "failed to request irq\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = device_create_file(&pdev->dev, &ftm_alarm_attributes);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "create sysfs fail.\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ alarm_freq = (u32)FIXED_FREQ_CLK / (u32)MAX_FREQ_DIV;
|
||||
+
|
||||
+ ftm_clean_alarm();
|
||||
+
|
||||
+ device_init_wakeup(&pdev->dev, true);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id ftm_alarm_match[] = {
|
||||
+ { .compatible = "fsl,ftm-alarm", },
|
||||
+ { .compatible = "fsl,ls1012a-ftm-alarm", },
|
||||
+ { .compatible = "fsl,ls1021a-ftm-alarm", },
|
||||
+ { .compatible = "fsl,ls1043a-ftm-alarm", },
|
||||
+ { .compatible = "fsl,ls1046a-ftm-alarm", },
|
||||
+ { .compatible = "fsl,ls1088a-ftm-alarm", },
|
||||
+ { .compatible = "fsl,ls208xa-ftm-alarm", },
|
||||
+ { .compatible = "fsl,ftm-timer", },
|
||||
+ { },
|
||||
+};
|
||||
+
|
||||
+static struct platform_driver ftm_alarm_driver = {
|
||||
+ .probe = ftm_alarm_probe,
|
||||
+ .driver = {
|
||||
+ .name = "ftm-alarm",
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .of_match_table = ftm_alarm_match,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init ftm_alarm_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ftm_alarm_driver);
|
||||
+}
|
||||
+device_initcall(ftm_alarm_init);
|
||||
@ -0,0 +1,349 @@
|
||||
From 4f22b58a2f809aff55aa9321c9100b0caf3b6694 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:36 +0800
|
||||
Subject: [PATCH 21/40] i2c: support layerscape
|
||||
This is an integrated patch of i2c for layerscape
|
||||
|
||||
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/i2c/busses/i2c-imx.c | 193 ++++++++++++++++++++++++++++
|
||||
drivers/i2c/muxes/i2c-mux-pca954x.c | 44 ++++++-
|
||||
2 files changed, 236 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/i2c/busses/i2c-imx.c
|
||||
+++ b/drivers/i2c/busses/i2c-imx.c
|
||||
@@ -53,6 +53,11 @@
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
+#include <linux/gpio.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/libata.h>
|
||||
|
||||
/* This will be the driver name the kernel reports */
|
||||
#define DRIVER_NAME "imx-i2c"
|
||||
@@ -117,6 +122,54 @@
|
||||
|
||||
#define I2C_PM_TIMEOUT 10 /* ms */
|
||||
|
||||
+enum pinmux_endian_type {
|
||||
+ BIG_ENDIAN,
|
||||
+ LITTLE_ENDIAN,
|
||||
+};
|
||||
+
|
||||
+struct pinmux_cfg {
|
||||
+ enum pinmux_endian_type endian; /* endian of RCWPMUXCR0 */
|
||||
+ u32 pmuxcr_offset;
|
||||
+ u32 pmuxcr_set_bit; /* pin mux of RCWPMUXCR0 */
|
||||
+};
|
||||
+
|
||||
+static struct pinmux_cfg ls1012a_pinmux_cfg = {
|
||||
+ .endian = BIG_ENDIAN,
|
||||
+ .pmuxcr_offset = 0x430,
|
||||
+ .pmuxcr_set_bit = 0x10,
|
||||
+};
|
||||
+
|
||||
+static struct pinmux_cfg ls1043a_pinmux_cfg = {
|
||||
+ .endian = BIG_ENDIAN,
|
||||
+ .pmuxcr_offset = 0x40C,
|
||||
+ .pmuxcr_set_bit = 0x10,
|
||||
+};
|
||||
+
|
||||
+static struct pinmux_cfg ls1046a_pinmux_cfg = {
|
||||
+ .endian = BIG_ENDIAN,
|
||||
+ .pmuxcr_offset = 0x40C,
|
||||
+ .pmuxcr_set_bit = 0x80000000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id pinmux_of_match[] = {
|
||||
+ { .compatible = "fsl,ls1012a-vf610-i2c", .data = &ls1012a_pinmux_cfg},
|
||||
+ { .compatible = "fsl,ls1043a-vf610-i2c", .data = &ls1043a_pinmux_cfg},
|
||||
+ { .compatible = "fsl,ls1046a-vf610-i2c", .data = &ls1046a_pinmux_cfg},
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, pinmux_of_match);
|
||||
+
|
||||
+/* The SCFG, Supplemental Configuration Unit, provides SoC specific
|
||||
+ * configuration and status registers for the device. There is a
|
||||
+ * SDHC IO VSEL control register on SCFG for some platforms. It's
|
||||
+ * used to support SDHC IO voltage switching.
|
||||
+ */
|
||||
+static const struct of_device_id scfg_device_ids[] = {
|
||||
+ { .compatible = "fsl,ls1012a-scfg", },
|
||||
+ { .compatible = "fsl,ls1043a-scfg", },
|
||||
+ { .compatible = "fsl,ls1046a-scfg", },
|
||||
+ {}
|
||||
+};
|
||||
/*
|
||||
* sorted list of clock divider, register value pairs
|
||||
* taken from table 26-5, p.26-9, Freescale i.MX
|
||||
@@ -210,6 +263,12 @@ struct imx_i2c_struct {
|
||||
struct pinctrl_state *pinctrl_pins_gpio;
|
||||
|
||||
struct imx_i2c_dma *dma;
|
||||
+ int layerscape_bus_recover;
|
||||
+ int gpio;
|
||||
+ int need_set_pmuxcr;
|
||||
+ int pmuxcr_set;
|
||||
+ int pmuxcr_endian;
|
||||
+ void __iomem *pmuxcr_addr;
|
||||
};
|
||||
|
||||
static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
|
||||
@@ -878,6 +937,78 @@ static int i2c_imx_read(struct imx_i2c_s
|
||||
return 0;
|
||||
}
|
||||
|
||||
+/*
|
||||
+ * Based on the I2C specification, if the data line (SDA) is
|
||||
+ * stuck low, the master should send nine * clock pulses.
|
||||
+ * The I2C slave device that held the bus low should release it
|
||||
+ * sometime within * those nine clocks. Due to this erratum,
|
||||
+ * the I2C controller cannot generate nine clock pulses.
|
||||
+ */
|
||||
+static int i2c_imx_recovery_for_layerscape(struct imx_i2c_struct *i2c_imx)
|
||||
+{
|
||||
+ u32 pmuxcr = 0;
|
||||
+ int ret;
|
||||
+ unsigned int i, temp;
|
||||
+
|
||||
+ /* configure IICx_SCL/GPIO pin as a GPIO */
|
||||
+ if (i2c_imx->need_set_pmuxcr == 1) {
|
||||
+ pmuxcr = ioread32be(i2c_imx->pmuxcr_addr);
|
||||
+ if (i2c_imx->pmuxcr_endian == BIG_ENDIAN)
|
||||
+ iowrite32be(i2c_imx->pmuxcr_set|pmuxcr,
|
||||
+ i2c_imx->pmuxcr_addr);
|
||||
+ else
|
||||
+ iowrite32(i2c_imx->pmuxcr_set|pmuxcr,
|
||||
+ i2c_imx->pmuxcr_addr);
|
||||
+ }
|
||||
+
|
||||
+ ret = gpio_request(i2c_imx->gpio, i2c_imx->adapter.name);
|
||||
+ if (ret) {
|
||||
+ dev_err(&i2c_imx->adapter.dev,
|
||||
+ "can't get gpio: %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Configure GPIO pin as an output and open drain. */
|
||||
+ gpio_direction_output(i2c_imx->gpio, 1);
|
||||
+ udelay(10);
|
||||
+
|
||||
+ /* Write data to generate 9 pulses */
|
||||
+ for (i = 0; i < 9; i++) {
|
||||
+ gpio_set_value(i2c_imx->gpio, 1);
|
||||
+ udelay(10);
|
||||
+ gpio_set_value(i2c_imx->gpio, 0);
|
||||
+ udelay(10);
|
||||
+ }
|
||||
+ /* ensure that the last level sent is always high */
|
||||
+ gpio_set_value(i2c_imx->gpio, 1);
|
||||
+
|
||||
+ /*
|
||||
+ * Set I2Cx_IBCR = 0h00 to generate a STOP and then
|
||||
+ * set I2Cx_IBCR = 0h80 to reset
|
||||
+ */
|
||||
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
|
||||
+ temp &= ~(I2CR_MSTA | I2CR_MTX);
|
||||
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
|
||||
+
|
||||
+ /* Restore the saved value of the register SCFG_RCWPMUXCR0 */
|
||||
+ if (i2c_imx->need_set_pmuxcr == 1) {
|
||||
+ if (i2c_imx->pmuxcr_endian == BIG_ENDIAN)
|
||||
+ iowrite32be(pmuxcr, i2c_imx->pmuxcr_addr);
|
||||
+ else
|
||||
+ iowrite32(pmuxcr, i2c_imx->pmuxcr_addr);
|
||||
+ }
|
||||
+ /*
|
||||
+ * Set I2C_IBSR[IBAL] to clear the IBAL bit if-
|
||||
+ * I2C_IBSR[IBAL] = 1
|
||||
+ */
|
||||
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
|
||||
+ if (temp & I2SR_IAL) {
|
||||
+ temp &= ~I2SR_IAL;
|
||||
+ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int i2c_imx_xfer(struct i2c_adapter *adapter,
|
||||
struct i2c_msg *msgs, int num)
|
||||
{
|
||||
@@ -888,6 +1019,19 @@ static int i2c_imx_xfer(struct i2c_adapt
|
||||
|
||||
dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
|
||||
|
||||
+ /*
|
||||
+ * workround for ERR010027: ensure that the I2C BUS is idle
|
||||
+ * before switching to master mode and attempting a Start cycle
|
||||
+ */
|
||||
+ result = i2c_imx_bus_busy(i2c_imx, 0);
|
||||
+ if (result) {
|
||||
+ /* timeout */
|
||||
+ if ((result == -ETIMEDOUT) && (i2c_imx->layerscape_bus_recover == 1))
|
||||
+ i2c_imx_recovery_for_layerscape(i2c_imx);
|
||||
+ else
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
result = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
|
||||
if (result < 0)
|
||||
goto out;
|
||||
@@ -1030,6 +1174,50 @@ static int i2c_imx_init_recovery_info(st
|
||||
return 0;
|
||||
}
|
||||
|
||||
+/*
|
||||
+ * switch SCL and SDA to their GPIO function and do some bitbanging
|
||||
+ * for bus recovery.
|
||||
+ * There are platforms such as Layerscape that don't support pinctrl, so add
|
||||
+ * workaround for layerscape, it has no effect for other platforms.
|
||||
+ */
|
||||
+static int i2c_imx_init_recovery_for_layerscape(
|
||||
+ struct imx_i2c_struct *i2c_imx,
|
||||
+ struct platform_device *pdev)
|
||||
+{
|
||||
+ const struct of_device_id *of_id;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ struct pinmux_cfg *pinmux_cfg;
|
||||
+ struct device_node *scfg_node;
|
||||
+ void __iomem *scfg_base = NULL;
|
||||
+
|
||||
+ i2c_imx->gpio = of_get_named_gpio(np, "fsl-scl-gpio", 0);
|
||||
+ if (!gpio_is_valid(i2c_imx->gpio)) {
|
||||
+ dev_info(&pdev->dev, "fsl-scl-gpio not found\n");
|
||||
+ return 0;
|
||||
+ }
|
||||
+ pinmux_cfg = devm_kzalloc(&pdev->dev, sizeof(*pinmux_cfg), GFP_KERNEL);
|
||||
+ if (!pinmux_cfg)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ i2c_imx->need_set_pmuxcr = 0;
|
||||
+ of_id = of_match_node(pinmux_of_match, np);
|
||||
+ if (of_id) {
|
||||
+ pinmux_cfg = (struct pinmux_cfg *)of_id->data;
|
||||
+ i2c_imx->pmuxcr_endian = pinmux_cfg->endian;
|
||||
+ i2c_imx->pmuxcr_set = pinmux_cfg->pmuxcr_set_bit;
|
||||
+ scfg_node = of_find_matching_node(NULL, scfg_device_ids);
|
||||
+ if (scfg_node) {
|
||||
+ scfg_base = of_iomap(scfg_node, 0);
|
||||
+ if (scfg_base) {
|
||||
+ i2c_imx->pmuxcr_addr = scfg_base + pinmux_cfg->pmuxcr_offset;
|
||||
+ i2c_imx->need_set_pmuxcr = 1;
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+ i2c_imx->layerscape_bus_recover = 1;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static u32 i2c_imx_func(struct i2c_adapter *adapter)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
|
||||
@@ -1085,6 +1273,11 @@ static int i2c_imx_probe(struct platform
|
||||
i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
|
||||
i2c_imx->base = base;
|
||||
|
||||
+ /* Init optional bus recovery for layerscape */
|
||||
+ ret = i2c_imx_init_recovery_for_layerscape(i2c_imx, pdev);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
/* Get I2C clock */
|
||||
i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(i2c_imx->clk)) {
|
||||
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
|
||||
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
|
||||
@@ -85,6 +85,7 @@ struct pca954x {
|
||||
struct irq_domain *irq;
|
||||
unsigned int irq_mask;
|
||||
raw_spinlock_t lock;
|
||||
+ u8 disable_mux; /* do not disable mux if val not 0 */
|
||||
};
|
||||
|
||||
/* Provide specs for the PCA954x types we know about */
|
||||
@@ -221,6 +222,13 @@ static int pca954x_deselect_mux(struct i
|
||||
if (!(data->deselect & (1 << chan)))
|
||||
return 0;
|
||||
|
||||
+#ifdef CONFIG_ARCH_LAYERSCAPE
|
||||
+ if (data->disable_mux != 0)
|
||||
+ data->last_chan = data->chip->nchans;
|
||||
+ else
|
||||
+ data->last_chan = 0;
|
||||
+ return pca954x_reg_write(muxc->parent, client, data->disable_mux);
|
||||
+#endif
|
||||
/* Deselect active channel */
|
||||
data->last_chan = 0;
|
||||
return pca954x_reg_write(muxc->parent, client, data->last_chan);
|
||||
@@ -361,6 +369,28 @@ static int pca954x_probe(struct i2c_clie
|
||||
return -ENOMEM;
|
||||
data = i2c_mux_priv(muxc);
|
||||
|
||||
+#ifdef CONFIG_ARCH_LAYERSCAPE
|
||||
+ /* The point here is that you must not disable a mux if there
|
||||
+ * are no pullups on the input or you mess up the I2C. This
|
||||
+ * needs to be put into the DTS really as the kernel cannot
|
||||
+ * know this otherwise.
|
||||
+ */
|
||||
+ match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
|
||||
+ if (match)
|
||||
+ data->chip = of_device_get_match_data(&client->dev);
|
||||
+ else
|
||||
+ data->chip = &chips[id->driver_data];
|
||||
+
|
||||
+ data->disable_mux = of_node &&
|
||||
+ of_property_read_bool(of_node, "i2c-mux-never-disable") &&
|
||||
+ data->chip->muxtype == pca954x_ismux ?
|
||||
+ data->chip->enable : 0;
|
||||
+ /* force the first selection */
|
||||
+ if (data->disable_mux != 0)
|
||||
+ data->last_chan = data->chip->nchans;
|
||||
+ else
|
||||
+ data->last_chan = 0;
|
||||
+#endif
|
||||
i2c_set_clientdata(client, muxc);
|
||||
data->client = client;
|
||||
|
||||
@@ -373,18 +403,23 @@ static int pca954x_probe(struct i2c_clie
|
||||
* that the mux is in fact present. This also
|
||||
* initializes the mux to disconnected state.
|
||||
*/
|
||||
+#ifdef CONFIG_ARCH_LAYERSCAPE
|
||||
+ if (i2c_smbus_write_byte(client, data->disable_mux) < 0) {
|
||||
+#else
|
||||
if (i2c_smbus_write_byte(client, 0) < 0) {
|
||||
+#endif
|
||||
dev_warn(&client->dev, "probe failed\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
+#ifndef CONFIG_ARCH_LAYERSCAPE
|
||||
match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev);
|
||||
if (match)
|
||||
data->chip = of_device_get_match_data(&client->dev);
|
||||
else
|
||||
data->chip = &chips[id->driver_data];
|
||||
-
|
||||
data->last_chan = 0; /* force the first selection */
|
||||
+#endif
|
||||
|
||||
idle_disconnect_dt = of_node &&
|
||||
of_property_read_bool(of_node, "i2c-mux-idle-disconnect");
|
||||
@@ -454,6 +489,13 @@ static int pca954x_resume(struct device
|
||||
struct i2c_mux_core *muxc = i2c_get_clientdata(client);
|
||||
struct pca954x *data = i2c_mux_priv(muxc);
|
||||
|
||||
+#ifdef CONFIG_ARCH_LAYERSCAPE
|
||||
+ if (data->disable_mux != 0)
|
||||
+ data->last_chan = data->chip->nchans;
|
||||
+ else
|
||||
+ data->last_chan = 0;
|
||||
+ return i2c_smbus_write_byte(client, data->disable_mux);
|
||||
+#endif
|
||||
data->last_chan = 0;
|
||||
return i2c_smbus_write_byte(client, 0);
|
||||
}
|
||||
1951
target/linux/layerscape/patches-4.14/805-qe-support-layerscape.patch
Normal file
1951
target/linux/layerscape/patches-4.14/805-qe-support-layerscape.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,776 @@
|
||||
From f8d89482075e2a4a62fc5cbacf6bea6baf4dc65f Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:27:31 +0800
|
||||
Subject: [PATCH 23/40] rtc: support layerscape
|
||||
This is an integrated patch of rtc for layerscape
|
||||
|
||||
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
|
||||
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
.../devicetree/bindings/rtc/nxp,pcf85263.txt | 42 ++
|
||||
drivers/rtc/Kconfig | 8 +
|
||||
drivers/rtc/Makefile | 1 +
|
||||
drivers/rtc/rtc-pcf85263.c | 664 ++++++++++++++++++
|
||||
include/dt-bindings/rtc/nxp,pcf85263.h | 14 +
|
||||
5 files changed, 729 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/rtc/nxp,pcf85263.txt
|
||||
create mode 100644 drivers/rtc/rtc-pcf85263.c
|
||||
create mode 100644 include/dt-bindings/rtc/nxp,pcf85263.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85263.txt
|
||||
@@ -0,0 +1,42 @@
|
||||
+NXP PCF85263 I2C Real Time Clock
|
||||
+
|
||||
+Required properties:
|
||||
+- compatible: must be: "nxp,rtc-pcf85263"
|
||||
+- reg: must be the I2C address
|
||||
+
|
||||
+Optional properties:
|
||||
+- interrupt-names: Which interrupt signal is used must be "INTA" or "INTB"
|
||||
+ Defaults to "INTA"
|
||||
+
|
||||
+- quartz-load-capacitance: The internal capacitor to select for the quartz:
|
||||
+ PCF85263_QUARTZCAP_7pF [0]
|
||||
+ PCF85263_QUARTZCAP_6pF [1]
|
||||
+ PCF85263_QUARTZCAP_12p5pF [2] DEFAULT
|
||||
+
|
||||
+- quartz-drive-strength: Drive strength for the quartz:
|
||||
+ PCF85263_QUARTZDRIVE_NORMAL [0] DEFAULT
|
||||
+ PCF85263_QUARTZDRIVE_LOW [1]
|
||||
+ PCF85263_QUARTZDRIVE_HIGH [2]
|
||||
+
|
||||
+- quartz-low-jitter: Boolean property, if present enables low jitter mode
|
||||
+which
|
||||
+ reduces jitter at the cost of increased power consumption.
|
||||
+
|
||||
+- wakeup-source: mark the chip as a wakeup source, independently of
|
||||
+ the availability of an IRQ line connected to the SoC.
|
||||
+ This is useful if the IRQ line is connected to a PMIC or other circuit
|
||||
+ that can power up the device rather than to a normal SOC interrupt.
|
||||
+
|
||||
+Example:
|
||||
+
|
||||
+rtc@51 {
|
||||
+ compatible = "nxp,pcf85263";
|
||||
+ reg = <0x51>;
|
||||
+
|
||||
+ interrupt-parent = <&gpio4>;
|
||||
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ interrupt-names = "INTB";
|
||||
+
|
||||
+ quartz-load-capacitance = <PCF85263_QUARTZCAP_12p5pF>;
|
||||
+ quartz-drive-strength = <PCF85263_QUARTZDRIVE_LOW>;
|
||||
+};
|
||||
--- a/drivers/rtc/Kconfig
|
||||
+++ b/drivers/rtc/Kconfig
|
||||
@@ -433,6 +433,14 @@ config RTC_DRV_PCF85063
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called rtc-pcf85063.
|
||||
|
||||
+config RTC_DRV_PCF85263
|
||||
+ tristate "NXP PCF85263"
|
||||
+ help
|
||||
+ If you say yes here you get support for the PCF85263 RTC chip
|
||||
+
|
||||
+ This driver can also be built as a module. If so, the module
|
||||
+ will be called rtc-pcf85263.
|
||||
+
|
||||
config RTC_DRV_PCF8563
|
||||
tristate "Philips PCF8563/Epson RTC8564"
|
||||
help
|
||||
--- a/drivers/rtc/Makefile
|
||||
+++ b/drivers/rtc/Makefile
|
||||
@@ -115,6 +115,7 @@ obj-$(CONFIG_RTC_DRV_PCF2127) += rtc-pcf
|
||||
obj-$(CONFIG_RTC_DRV_PCF50633) += rtc-pcf50633.o
|
||||
obj-$(CONFIG_RTC_DRV_PCF85063) += rtc-pcf85063.o
|
||||
obj-$(CONFIG_RTC_DRV_PCF8523) += rtc-pcf8523.o
|
||||
+obj-$(CONFIG_RTC_DRV_PCF85263) += rtc-pcf85263.o
|
||||
obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o
|
||||
obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o
|
||||
obj-$(CONFIG_RTC_DRV_PIC32) += rtc-pic32.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/rtc/rtc-pcf85263.c
|
||||
@@ -0,0 +1,664 @@
|
||||
+/*
|
||||
+ * rtc-pcf85263 Driver for the NXP PCF85263 RTC
|
||||
+ * Copyright 2016 Parkeon
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/mutex.h>
|
||||
+#include <linux/rtc.h>
|
||||
+#include <linux/i2c.h>
|
||||
+#include <linux/bcd.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/regmap.h>
|
||||
+
|
||||
+
|
||||
+#define DRV_NAME "rtc-pcf85263"
|
||||
+
|
||||
+/* Quartz capacitance */
|
||||
+#define PCF85263_QUARTZCAP_7pF 0
|
||||
+#define PCF85263_QUARTZCAP_6pF 1
|
||||
+#define PCF85263_QUARTZCAP_12p5pF 2
|
||||
+
|
||||
+/* Quartz drive strength */
|
||||
+#define PCF85263_QUARTZDRIVE_NORMAL 0
|
||||
+#define PCF85263_QUARTZDRIVE_LOW 1
|
||||
+#define PCF85263_QUARTZDRIVE_HIGH 2
|
||||
+
|
||||
+
|
||||
+#define PCF85263_REG_RTC_SC 0x01 /* Seconds */
|
||||
+#define PCF85263_REG_RTC_SC_OS BIT(7) /* Oscilator stopped flag */
|
||||
+
|
||||
+#define PCF85263_REG_RTC_MN 0x02 /* Minutes */
|
||||
+#define PCF85263_REG_RTC_HR 0x03 /* Hours */
|
||||
+#define PCF85263_REG_RTC_DT 0x04 /* Day of month 1-31 */
|
||||
+#define PCF85263_REG_RTC_DW 0x05 /* Day of week 0-6 */
|
||||
+#define PCF85263_REG_RTC_MO 0x06 /* Month 1-12 */
|
||||
+#define PCF85263_REG_RTC_YR 0x07 /* Year 0-99 */
|
||||
+
|
||||
+#define PCF85263_REG_ALM1_SC 0x08 /* Seconds */
|
||||
+#define PCF85263_REG_ALM1_MN 0x09 /* Minutes */
|
||||
+#define PCF85263_REG_ALM1_HR 0x0a /* Hours */
|
||||
+#define PCF85263_REG_ALM1_DT 0x0b /* Day of month 1-31 */
|
||||
+#define PCF85263_REG_ALM1_MO 0x0c /* Month 1-12 */
|
||||
+
|
||||
+#define PCF85263_REG_ALM_CTL 0x10
|
||||
+#define PCF85263_REG_ALM_CTL_ALL_A1E 0x1f /* sec,min,hr,day,mon alarm 1 */
|
||||
+
|
||||
+#define PCF85263_REG_OSC 0x25
|
||||
+#define PCF85263_REG_OSC_CL_MASK (BIT(0) | BIT(1))
|
||||
+#define PCF85263_REG_OSC_CL_SHIFT 0
|
||||
+#define PCF85263_REG_OSC_OSCD_MASK (BIT(2) | BIT(3))
|
||||
+#define PCF85263_REG_OSC_OSCD_SHIFT 2
|
||||
+#define PCF85263_REG_OSC_LOWJ BIT(4)
|
||||
+#define PCF85263_REG_OSC_12H BIT(5)
|
||||
+
|
||||
+#define PCF85263_REG_PINIO 0x27
|
||||
+#define PCF85263_REG_PINIO_INTAPM_MASK (BIT(0) | BIT(1))
|
||||
+#define PCF85263_REG_PINIO_INTAPM_SHIFT 0
|
||||
+#define PCF85263_INTAPM_INTA (0x2 << PCF85263_REG_PINIO_INTAPM_SHIFT)
|
||||
+#define PCF85263_INTAPM_HIGHZ (0x3 << PCF85263_REG_PINIO_INTAPM_SHIFT)
|
||||
+#define PCF85263_REG_PINIO_TSPM_MASK (BIT(2) | BIT(3))
|
||||
+#define PCF85263_REG_PINIO_TSPM_SHIFT 2
|
||||
+#define PCF85263_TSPM_DISABLED (0x0 << PCF85263_REG_PINIO_TSPM_SHIFT)
|
||||
+#define PCF85263_TSPM_INTB (0x1 << PCF85263_REG_PINIO_TSPM_SHIFT)
|
||||
+#define PCF85263_REG_PINIO_CLKDISABLE BIT(7)
|
||||
+
|
||||
+#define PCF85263_REG_FUNCTION 0x28
|
||||
+#define PCF85263_REG_FUNCTION_COF_MASK 0x7
|
||||
+#define PCF85263_REG_FUNCTION_COF_OFF 0x7 /* No clock output */
|
||||
+
|
||||
+#define PCF85263_REG_INTA_CTL 0x29
|
||||
+#define PCF85263_REG_INTB_CTL 0x2A
|
||||
+#define PCF85263_REG_INTx_CTL_A1E BIT(4) /* Alarm 1 */
|
||||
+#define PCF85263_REG_INTx_CTL_ILP BIT(7) /* 0=pulse, 1=level */
|
||||
+
|
||||
+#define PCF85263_REG_FLAGS 0x2B
|
||||
+#define PCF85263_REG_FLAGS_A1F BIT(5)
|
||||
+
|
||||
+#define PCF85263_REG_RAM_BYTE 0x2c
|
||||
+
|
||||
+#define PCF85263_REG_STOPENABLE 0x2e
|
||||
+#define PCF85263_REG_STOPENABLE_STOP BIT(0)
|
||||
+
|
||||
+#define PCF85263_REG_RESET 0x2f /* Reset command */
|
||||
+#define PCF85263_REG_RESET_CMD_CPR 0xa4 /* Clear prescaler */
|
||||
+
|
||||
+#define PCF85263_MAX_REG 0x2f
|
||||
+
|
||||
+#define PCF85263_HR_PM BIT(5)
|
||||
+
|
||||
+enum pcf85263_irqpin {
|
||||
+ PCF85263_IRQPIN_NONE,
|
||||
+ PCF85263_IRQPIN_INTA,
|
||||
+ PCF85263_IRQPIN_INTB
|
||||
+};
|
||||
+
|
||||
+static const char *const pcf85263_irqpin_names[] = {
|
||||
+ [PCF85263_IRQPIN_NONE] = "None",
|
||||
+ [PCF85263_IRQPIN_INTA] = "INTA",
|
||||
+ [PCF85263_IRQPIN_INTB] = "INTB"
|
||||
+};
|
||||
+
|
||||
+struct pcf85263 {
|
||||
+ struct device *dev;
|
||||
+ struct rtc_device *rtc;
|
||||
+ struct regmap *regmap;
|
||||
+ enum pcf85263_irqpin irq_pin;
|
||||
+ int irq;
|
||||
+ bool mode_12h;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * Helpers to convert 12h to 24h and vice versa.
|
||||
+ * Values in register are stored in BCD with a PM flag in bit 5
|
||||
+ *
|
||||
+ * 23:00 <=> 11PM <=> 0x31
|
||||
+ * 00:00 <=> 12AM <=> 0x12
|
||||
+ * 01:00 <=> 1AM <=> 0x01
|
||||
+ * 12:00 <=> 12PM <=> 0x32
|
||||
+ * 13:00 <=> 1PM <=> 0x21
|
||||
+ */
|
||||
+static int pcf85263_bcd12h_to_bin24h(int regval)
|
||||
+{
|
||||
+ int hr = bcd2bin(regval & 0x1f);
|
||||
+ bool pm = regval & PCF85263_HR_PM;
|
||||
+
|
||||
+ if (hr == 12)
|
||||
+ return pm ? 12 : 0;
|
||||
+
|
||||
+ return pm ? hr + 12 : hr;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_bin24h_to_bcd12h(int hr24)
|
||||
+{
|
||||
+ bool pm = hr24 >= 12;
|
||||
+ int hr12 = hr24 % 12;
|
||||
+
|
||||
+ if (!hr12)
|
||||
+ hr12++;
|
||||
+
|
||||
+ return bin2bcd(hr12) | pm ? 0 : PCF85263_HR_PM;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_read_time(struct device *dev, struct rtc_time *tm)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+ const int first = PCF85263_REG_RTC_SC;
|
||||
+ const int last = PCF85263_REG_RTC_YR;
|
||||
+ const int len = last - first + 1;
|
||||
+ u8 regs[len];
|
||||
+ u8 hr_reg;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (regs[PCF85263_REG_RTC_SC - first] & PCF85263_REG_RTC_SC_OS) {
|
||||
+ dev_warn(dev, "Oscillator stop detected, date/time is not reliable.\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ tm->tm_sec = bcd2bin(regs[PCF85263_REG_RTC_SC - first] & 0x7f);
|
||||
+ tm->tm_min = bcd2bin(regs[PCF85263_REG_RTC_MN - first] & 0x7f);
|
||||
+
|
||||
+ hr_reg = regs[PCF85263_REG_RTC_HR - first];
|
||||
+ if (pcf85263->mode_12h)
|
||||
+ tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
|
||||
+ else
|
||||
+ tm->tm_hour = bcd2bin(hr_reg & 0x3f);
|
||||
+
|
||||
+ tm->tm_mday = bcd2bin(regs[PCF85263_REG_RTC_DT - first]);
|
||||
+ tm->tm_wday = bcd2bin(regs[PCF85263_REG_RTC_DW - first]);
|
||||
+ tm->tm_mon = bcd2bin(regs[PCF85263_REG_RTC_MO - first]) - 1;
|
||||
+ tm->tm_year = bcd2bin(regs[PCF85263_REG_RTC_YR - first]);
|
||||
+
|
||||
+ tm->tm_year += 100; /* Assume 21st century */
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_set_time(struct device *dev, struct rtc_time *tm)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+
|
||||
+ /*
|
||||
+ * Before setting time need to stop RTC and disable prescaler
|
||||
+ * Do this all in a single I2C transaction exploiting wraparound
|
||||
+ * as described in data sheet.
|
||||
+ * This means that the array below must be in register order
|
||||
+ */
|
||||
+ u8 regs[] = {
|
||||
+ PCF85263_REG_STOPENABLE_STOP, /* STOP */
|
||||
+ PCF85263_REG_RESET_CMD_CPR, /* Disable prescaler */
|
||||
+ /* Wrap around to register 0 (1/100s) */
|
||||
+ 0, /* 1/100s always zero. */
|
||||
+ bin2bcd(tm->tm_sec),
|
||||
+ bin2bcd(tm->tm_min),
|
||||
+ bin2bcd(tm->tm_hour), /* 24-hour */
|
||||
+ bin2bcd(tm->tm_mday),
|
||||
+ bin2bcd(tm->tm_wday + 1),
|
||||
+ bin2bcd(tm->tm_mon + 1),
|
||||
+ bin2bcd(tm->tm_year % 100)
|
||||
+ };
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regmap_bulk_write(pcf85263->regmap, PCF85263_REG_STOPENABLE,
|
||||
+ regs, sizeof(regs));
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* As we have set the time in 24H update the hardware for that */
|
||||
+ if (pcf85263->mode_12h) {
|
||||
+ pcf85263->mode_12h = false;
|
||||
+ ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_OSC,
|
||||
+ PCF85263_REG_OSC_12H, 0);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Start it again */
|
||||
+ return regmap_write(pcf85263->regmap, PCF85263_REG_STOPENABLE, 0);
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_enable_alarm(struct pcf85263 *pcf85263, bool enable)
|
||||
+{
|
||||
+ int reg;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_ALM_CTL,
|
||||
+ PCF85263_REG_ALM_CTL_ALL_A1E,
|
||||
+ enable ? PCF85263_REG_ALM_CTL_ALL_A1E : 0);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ switch (pcf85263->irq_pin) {
|
||||
+ case PCF85263_IRQPIN_NONE:
|
||||
+ return 0;
|
||||
+
|
||||
+ case PCF85263_IRQPIN_INTA:
|
||||
+ reg = PCF85263_REG_INTA_CTL;
|
||||
+ break;
|
||||
+
|
||||
+ case PCF85263_IRQPIN_INTB:
|
||||
+ reg = PCF85263_REG_INTB_CTL;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return regmap_update_bits(pcf85263->regmap, reg,
|
||||
+ PCF85263_REG_INTx_CTL_A1E,
|
||||
+ enable ? PCF85263_REG_INTx_CTL_A1E : 0);
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+ struct rtc_time *tm = &alarm->time;
|
||||
+ const int first = PCF85263_REG_ALM1_SC;
|
||||
+ const int last = PCF85263_REG_ALM1_MO;
|
||||
+ const int len = last - first + 1;
|
||||
+ u8 regs[len];
|
||||
+ u8 hr_reg;
|
||||
+ unsigned int regval;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ tm->tm_sec = bcd2bin(regs[PCF85263_REG_ALM1_SC - first] & 0x7f);
|
||||
+ tm->tm_min = bcd2bin(regs[PCF85263_REG_ALM1_MN - first] & 0x7f);
|
||||
+
|
||||
+ hr_reg = regs[PCF85263_REG_ALM1_HR - first];
|
||||
+ if (pcf85263->mode_12h)
|
||||
+ tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
|
||||
+ else
|
||||
+ tm->tm_hour = bcd2bin(hr_reg & 0x3f);
|
||||
+
|
||||
+ tm->tm_mday = bcd2bin(regs[PCF85263_REG_ALM1_DT - first]);
|
||||
+ tm->tm_mon = bcd2bin(regs[PCF85263_REG_ALM1_MO - first]) - 1;
|
||||
+ tm->tm_year = -1;
|
||||
+ tm->tm_wday = -1;
|
||||
+
|
||||
+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_ALM_CTL, ®val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ alarm->enabled = !!(regval & PCF85263_REG_ALM_CTL_ALL_A1E);
|
||||
+
|
||||
+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, ®val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ alarm->pending = !!(regval & PCF85263_REG_FLAGS_A1F);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+ struct rtc_time *tm = &alarm->time;
|
||||
+ const int first = PCF85263_REG_ALM1_SC;
|
||||
+ const int last = PCF85263_REG_ALM1_MO;
|
||||
+ const int len = last - first + 1;
|
||||
+ u8 regs[len];
|
||||
+ int ret;
|
||||
+
|
||||
+ /* Disable alarm comparison during update */
|
||||
+ ret = pcf85263_enable_alarm(pcf85263, false);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Clear any pending alarm (write 0=>clr, 1=>no change) */
|
||||
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
|
||||
+ (unsigned int)(~PCF85263_REG_FLAGS_A1F));
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Set the alarm time registers */
|
||||
+ regs[PCF85263_REG_ALM1_SC - first] = bin2bcd(tm->tm_sec);
|
||||
+ regs[PCF85263_REG_ALM1_MN - first] = bin2bcd(tm->tm_min);
|
||||
+ regs[PCF85263_REG_ALM1_HR - first] = pcf85263->mode_12h ?
|
||||
+ pcf85263_bin24h_to_bcd12h(tm->tm_hour) :
|
||||
+ bin2bcd(tm->tm_hour);
|
||||
+ regs[PCF85263_REG_ALM1_DT - first] = bin2bcd(tm->tm_mday);
|
||||
+ regs[PCF85263_REG_ALM1_MO - first] = bin2bcd(tm->tm_mon + 1);
|
||||
+
|
||||
+ ret = regmap_bulk_write(pcf85263->regmap, first, regs, sizeof(regs));
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (alarm->enabled)
|
||||
+ ret = pcf85263_enable_alarm(pcf85263, true);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_alarm_irq_enable(struct device *dev, unsigned int enable)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+
|
||||
+ return pcf85263_enable_alarm(pcf85263, !!enable);
|
||||
+}
|
||||
+
|
||||
+static irqreturn_t pcf85263_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = data;
|
||||
+ unsigned int regval;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, ®val);
|
||||
+ if (ret)
|
||||
+ return IRQ_NONE;
|
||||
+
|
||||
+ if (regval & PCF85263_REG_FLAGS_A1F) {
|
||||
+ regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
|
||||
+ (unsigned int)(~PCF85263_REG_FLAGS_A1F));
|
||||
+
|
||||
+ rtc_update_irq(pcf85263->rtc, 1, RTC_IRQF | RTC_AF);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+ }
|
||||
+
|
||||
+ return IRQ_NONE;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_check_osc_stopped(struct pcf85263 *pcf85263)
|
||||
+{
|
||||
+ unsigned int regval;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_RTC_SC, ®val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = regval & PCF85263_REG_RTC_SC_OS ? 1 : 0;
|
||||
+ if (ret)
|
||||
+ dev_warn(pcf85263->dev, "Oscillator stop detected, date/time is not reliable.\n");
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_RTC_INTF_DEV
|
||||
+static int pcf85263_ioctl(struct device *dev,
|
||||
+ unsigned int cmd, unsigned long arg)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+ int ret;
|
||||
+
|
||||
+ switch (cmd) {
|
||||
+ case RTC_VL_READ:
|
||||
+ ret = pcf85263_check_osc_stopped(pcf85263);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (copy_to_user((void __user *)arg, &ret, sizeof(int)))
|
||||
+ return -EFAULT;
|
||||
+ return 0;
|
||||
+
|
||||
+ case RTC_VL_CLR:
|
||||
+ return regmap_update_bits(pcf85263->regmap,
|
||||
+ PCF85263_REG_RTC_SC,
|
||||
+ PCF85263_REG_RTC_SC_OS, 0);
|
||||
+ default:
|
||||
+ return -ENOIOCTLCMD;
|
||||
+ }
|
||||
+}
|
||||
+#else
|
||||
+#define pcf85263_ioctl NULL
|
||||
+#endif
|
||||
+
|
||||
+static int pcf85263_init_hw(struct pcf85263 *pcf85263)
|
||||
+{
|
||||
+ struct device_node *np = pcf85263->dev->of_node;
|
||||
+ unsigned int regval;
|
||||
+ u32 propval;
|
||||
+ int ret;
|
||||
+
|
||||
+ /* Determine if oscilator has been stopped (probably low power) */
|
||||
+ ret = pcf85263_check_osc_stopped(pcf85263);
|
||||
+ if (ret < 0) {
|
||||
+ /* Log here since this is the first hw access on probe */
|
||||
+ dev_err(pcf85263->dev, "Unable to read register\n");
|
||||
+
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Determine 12/24H mode */
|
||||
+ ret = regmap_read(pcf85263->regmap, PCF85263_REG_OSC, ®val);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ pcf85263->mode_12h = !!(regval & PCF85263_REG_OSC_12H);
|
||||
+
|
||||
+ /* Set oscilator register */
|
||||
+ regval &= ~PCF85263_REG_OSC_12H; /* keep current 12/24 h setting */
|
||||
+
|
||||
+ propval = PCF85263_QUARTZCAP_12p5pF;
|
||||
+ of_property_read_u32(np, "quartz-load-capacitance", &propval);
|
||||
+ regval |= ((propval << PCF85263_REG_OSC_CL_SHIFT)
|
||||
+ & PCF85263_REG_OSC_CL_MASK);
|
||||
+
|
||||
+ propval = PCF85263_QUARTZDRIVE_NORMAL;
|
||||
+ of_property_read_u32(np, "quartz-drive-strength", &propval);
|
||||
+ regval |= ((propval << PCF85263_REG_OSC_OSCD_SHIFT)
|
||||
+ & PCF85263_REG_OSC_OSCD_MASK);
|
||||
+
|
||||
+ if (of_property_read_bool(np, "quartz-low-jitter"))
|
||||
+ regval |= PCF85263_REG_OSC_LOWJ;
|
||||
+
|
||||
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_OSC, regval);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Set function register (RTC mode, 1s tick, clock output static) */
|
||||
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_FUNCTION,
|
||||
+ PCF85263_REG_FUNCTION_COF_OFF);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Set all interrupts to disabled, level mode */
|
||||
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTA_CTL,
|
||||
+ PCF85263_REG_INTx_CTL_ILP);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTB_CTL,
|
||||
+ PCF85263_REG_INTx_CTL_ILP);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Setup IO pin config register */
|
||||
+ regval = PCF85263_REG_PINIO_CLKDISABLE;
|
||||
+ switch (pcf85263->irq_pin) {
|
||||
+ case PCF85263_IRQPIN_INTA:
|
||||
+ regval |= (PCF85263_INTAPM_INTA | PCF85263_TSPM_DISABLED);
|
||||
+ break;
|
||||
+ case PCF85263_IRQPIN_INTB:
|
||||
+ regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_INTB);
|
||||
+ break;
|
||||
+ case PCF85263_IRQPIN_NONE:
|
||||
+ regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_DISABLED);
|
||||
+ break;
|
||||
+ }
|
||||
+ ret = regmap_write(pcf85263->regmap, PCF85263_REG_PINIO, regval);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rtc_class_ops rtc_ops = {
|
||||
+ .ioctl = pcf85263_ioctl,
|
||||
+ .read_time = pcf85263_read_time,
|
||||
+ .set_time = pcf85263_set_time,
|
||||
+ .read_alarm = pcf85263_read_alarm,
|
||||
+ .set_alarm = pcf85263_set_alarm,
|
||||
+ .alarm_irq_enable = pcf85263_alarm_irq_enable,
|
||||
+};
|
||||
+
|
||||
+static const struct regmap_config pcf85263_regmap_cfg = {
|
||||
+ .reg_bits = 8,
|
||||
+ .val_bits = 8,
|
||||
+ .max_register = PCF85263_MAX_REG,
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * On some boards the interrupt line may not be wired to the CPU but only to
|
||||
+ * a power supply circuit.
|
||||
+ * In that case no interrupt will be specified in the device tree but the
|
||||
+ * wakeup-source DT property may be used to enable wakeup programming in
|
||||
+ * sysfs
|
||||
+ */
|
||||
+static bool pcf85263_can_wakeup_machine(struct pcf85263 *pcf85263)
|
||||
+{
|
||||
+ return pcf85263->irq ||
|
||||
+ of_property_read_bool(pcf85263->dev->of_node, "wakeup-source");
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_probe(struct i2c_client *client,
|
||||
+ const struct i2c_device_id *id)
|
||||
+{
|
||||
+ struct device *dev = &client->dev;
|
||||
+ struct pcf85263 *pcf85263;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
|
||||
+ I2C_FUNC_SMBUS_BYTE_DATA |
|
||||
+ I2C_FUNC_SMBUS_I2C_BLOCK))
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ pcf85263 = devm_kzalloc(dev, sizeof(*pcf85263), GFP_KERNEL);
|
||||
+ if (!pcf85263)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ pcf85263->dev = dev;
|
||||
+ pcf85263->irq = client->irq;
|
||||
+ dev_set_drvdata(dev, pcf85263);
|
||||
+
|
||||
+ pcf85263->regmap = devm_regmap_init_i2c(client, &pcf85263_regmap_cfg);
|
||||
+ if (IS_ERR(pcf85263->regmap)) {
|
||||
+ ret = PTR_ERR(pcf85263->regmap);
|
||||
+ dev_err(dev, "regmap allocation failed (%d)\n", ret);
|
||||
+
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ /* Determine which interrupt pin the board uses */
|
||||
+ if (pcf85263_can_wakeup_machine(pcf85263)) {
|
||||
+ if (of_property_match_string(dev->of_node,
|
||||
+ "interrupt-names", "INTB") >= 0)
|
||||
+ pcf85263->irq_pin = PCF85263_IRQPIN_INTB;
|
||||
+ else
|
||||
+ pcf85263->irq_pin = PCF85263_IRQPIN_INTA;
|
||||
+ } else {
|
||||
+ pcf85263->irq_pin = PCF85263_IRQPIN_NONE;
|
||||
+ }
|
||||
+
|
||||
+ ret = pcf85263_init_hw(pcf85263);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ if (pcf85263->irq) {
|
||||
+ ret = devm_request_threaded_irq(dev, pcf85263->irq, NULL,
|
||||
+ pcf85263_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ dev->driver->name, pcf85263);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "irq %d unavailable (%d)\n",
|
||||
+ pcf85263->irq, ret);
|
||||
+ pcf85263->irq = 0;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (pcf85263_can_wakeup_machine(pcf85263))
|
||||
+ device_init_wakeup(dev, true);
|
||||
+
|
||||
+ pcf85263->rtc = devm_rtc_device_register(dev, dev->driver->name,
|
||||
+ &rtc_ops, THIS_MODULE);
|
||||
+ ret = PTR_ERR_OR_ZERO(pcf85263->rtc);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* We cannot support UIE mode if we do not have an IRQ line */
|
||||
+ if (!pcf85263->irq)
|
||||
+ pcf85263->rtc->uie_unsupported = 1;
|
||||
+
|
||||
+ dev_info(pcf85263->dev,
|
||||
+ "PCF85263 RTC (irqpin=%s irq=%d)\n",
|
||||
+ pcf85263_irqpin_names[pcf85263->irq_pin],
|
||||
+ pcf85263->irq);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_remove(struct i2c_client *client)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = i2c_get_clientdata(client);
|
||||
+
|
||||
+ if (pcf85263_can_wakeup_machine(pcf85263))
|
||||
+ device_init_wakeup(pcf85263->dev, false);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_PM_SLEEP
|
||||
+static int pcf85263_suspend(struct device *dev)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ if (device_may_wakeup(dev))
|
||||
+ ret = enable_irq_wake(pcf85263->irq);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int pcf85263_resume(struct device *dev)
|
||||
+{
|
||||
+ struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
|
||||
+ int ret = 0;
|
||||
+
|
||||
+ if (device_may_wakeup(dev))
|
||||
+ ret = disable_irq_wake(pcf85263->irq);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+#endif
|
||||
+
|
||||
+static const struct i2c_device_id pcf85263_id[] = {
|
||||
+ { "pcf85263", 0 },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(i2c, pcf85263_id);
|
||||
+
|
||||
+#ifdef CONFIG_OF
|
||||
+static const struct of_device_id pcf85263_of_match[] = {
|
||||
+ { .compatible = "nxp,pcf85263" },
|
||||
+ {}
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, pcf85263_of_match);
|
||||
+#endif
|
||||
+
|
||||
+static SIMPLE_DEV_PM_OPS(pcf85263_pm_ops, pcf85263_suspend, pcf85263_resume);
|
||||
+
|
||||
+static struct i2c_driver pcf85263_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "rtc-pcf85263",
|
||||
+ .of_match_table = of_match_ptr(pcf85263_of_match),
|
||||
+ .pm = &pcf85263_pm_ops,
|
||||
+ },
|
||||
+ .probe = pcf85263_probe,
|
||||
+ .remove = pcf85263_remove,
|
||||
+ .id_table = pcf85263_id,
|
||||
+};
|
||||
+
|
||||
+module_i2c_driver(pcf85263_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Martin Fuzzey <mfuzzey@parkeon.com>");
|
||||
+MODULE_DESCRIPTION("PCF85263 RTC Driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/rtc/nxp,pcf85263.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+#ifndef _DT_BINDINGS_RTC_NXP_PCF85263_H
|
||||
+#define _DT_BINDINGS_RTC_NXP_PCF85263_H
|
||||
+
|
||||
+/* Quartz capacitance */
|
||||
+#define PCF85263_QUARTZCAP_7pF 0
|
||||
+#define PCF85263_QUARTZCAP_6pF 1
|
||||
+#define PCF85263_QUARTZCAP_12p5pF 2
|
||||
+
|
||||
+/* Quartz drive strength */
|
||||
+#define PCF85263_QUARTZDRIVE_NORMAL 0
|
||||
+#define PCF85263_QUARTZDRIVE_LOW 1
|
||||
+#define PCF85263_QUARTZDRIVE_HIGH 2
|
||||
+
|
||||
+#endif /* _DT_BINDINGS_RTC_NXP_PCF85263_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,595 @@
|
||||
From 3ed707fde8a33f2b888f75ac2f5e0a98e7774dad Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:27 +0800
|
||||
Subject: [PATCH 26/40] flexcan: support layerscape
|
||||
This is an integrated patch of flexcan for layerscape
|
||||
|
||||
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
|
||||
Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
|
||||
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
|
||||
Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/net/can/flexcan.c | 240 ++++++++++++++++++++++----------------
|
||||
1 file changed, 138 insertions(+), 102 deletions(-)
|
||||
|
||||
--- a/drivers/net/can/flexcan.c
|
||||
+++ b/drivers/net/can/flexcan.c
|
||||
@@ -190,6 +190,7 @@
|
||||
* MX53 FlexCAN2 03.00.00.00 yes no no no no
|
||||
* MX6s FlexCAN3 10.00.12.00 yes yes no no yes
|
||||
* VF610 FlexCAN3 ? no yes no yes yes?
|
||||
+ * LS1021A FlexCAN2 03.00.04.00 no yes no yes
|
||||
*
|
||||
* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
|
||||
*/
|
||||
@@ -279,6 +280,10 @@ struct flexcan_priv {
|
||||
struct clk *clk_per;
|
||||
const struct flexcan_devtype_data *devtype_data;
|
||||
struct regulator *reg_xceiver;
|
||||
+
|
||||
+ /* Read and Write APIs */
|
||||
+ u32 (*read)(void __iomem *addr);
|
||||
+ void (*write)(u32 val, void __iomem *addr);
|
||||
};
|
||||
|
||||
static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
|
||||
@@ -301,6 +306,11 @@ static const struct flexcan_devtype_data
|
||||
FLEXCAN_QUIRK_BROKEN_PERR_STATE,
|
||||
};
|
||||
|
||||
+static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
|
||||
+ .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
|
||||
+ FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
|
||||
+};
|
||||
+
|
||||
static const struct can_bittiming_const flexcan_bittiming_const = {
|
||||
.name = DRV_NAME,
|
||||
.tseg1_min = 4,
|
||||
@@ -313,39 +323,45 @@ static const struct can_bittiming_const
|
||||
.brp_inc = 1,
|
||||
};
|
||||
|
||||
-/* Abstract off the read/write for arm versus ppc. This
|
||||
- * assumes that PPC uses big-endian registers and everything
|
||||
- * else uses little-endian registers, independent of CPU
|
||||
- * endianness.
|
||||
+/* FlexCAN module is essentially modelled as a little-endian IP in most
|
||||
+ * SoCs, i.e the registers as well as the message buffer areas are
|
||||
+ * implemented in a little-endian fashion.
|
||||
+ *
|
||||
+ * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
|
||||
+ * module in a big-endian fashion (i.e the registers as well as the
|
||||
+ * message buffer areas are implemented in a big-endian way).
|
||||
+ *
|
||||
+ * In addition, the FlexCAN module can be found on SoCs having ARM or
|
||||
+ * PPC cores. So, we need to abstract off the register read/write
|
||||
+ * functions, ensuring that these cater to all the combinations of module
|
||||
+ * endianness and underlying CPU endianness.
|
||||
*/
|
||||
-#if defined(CONFIG_PPC)
|
||||
-static inline u32 flexcan_read(void __iomem *addr)
|
||||
+static inline u32 flexcan_read_be(void __iomem *addr)
|
||||
{
|
||||
- return in_be32(addr);
|
||||
+ return ioread32be(addr);
|
||||
}
|
||||
|
||||
-static inline void flexcan_write(u32 val, void __iomem *addr)
|
||||
+static inline void flexcan_write_be(u32 val, void __iomem *addr)
|
||||
{
|
||||
- out_be32(addr, val);
|
||||
+ iowrite32be(val, addr);
|
||||
}
|
||||
-#else
|
||||
-static inline u32 flexcan_read(void __iomem *addr)
|
||||
+
|
||||
+static inline u32 flexcan_read_le(void __iomem *addr)
|
||||
{
|
||||
- return readl(addr);
|
||||
+ return ioread32(addr);
|
||||
}
|
||||
|
||||
-static inline void flexcan_write(u32 val, void __iomem *addr)
|
||||
+static inline void flexcan_write_le(u32 val, void __iomem *addr)
|
||||
{
|
||||
- writel(val, addr);
|
||||
+ iowrite32(val, addr);
|
||||
}
|
||||
-#endif
|
||||
|
||||
static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
|
||||
{
|
||||
struct flexcan_regs __iomem *regs = priv->regs;
|
||||
u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
|
||||
|
||||
- flexcan_write(reg_ctrl, ®s->ctrl);
|
||||
+ priv->write(reg_ctrl, ®s->ctrl);
|
||||
}
|
||||
|
||||
static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
|
||||
@@ -353,7 +369,7 @@ static inline void flexcan_error_irq_dis
|
||||
struct flexcan_regs __iomem *regs = priv->regs;
|
||||
u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
|
||||
|
||||
- flexcan_write(reg_ctrl, ®s->ctrl);
|
||||
+ priv->write(reg_ctrl, ®s->ctrl);
|
||||
}
|
||||
|
||||
static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
|
||||
@@ -378,14 +394,14 @@ static int flexcan_chip_enable(struct fl
|
||||
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
||||
u32 reg;
|
||||
|
||||
- reg = flexcan_read(®s->mcr);
|
||||
+ reg = priv->read(®s->mcr);
|
||||
reg &= ~FLEXCAN_MCR_MDIS;
|
||||
- flexcan_write(reg, ®s->mcr);
|
||||
+ priv->write(reg, ®s->mcr);
|
||||
|
||||
- while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
||||
+ while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
||||
udelay(10);
|
||||
|
||||
- if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
|
||||
+ if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
@@ -397,14 +413,14 @@ static int flexcan_chip_disable(struct f
|
||||
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
||||
u32 reg;
|
||||
|
||||
- reg = flexcan_read(®s->mcr);
|
||||
+ reg = priv->read(®s->mcr);
|
||||
reg |= FLEXCAN_MCR_MDIS;
|
||||
- flexcan_write(reg, ®s->mcr);
|
||||
+ priv->write(reg, ®s->mcr);
|
||||
|
||||
- while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
||||
+ while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
||||
udelay(10);
|
||||
|
||||
- if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
||||
+ if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
@@ -416,14 +432,14 @@ static int flexcan_chip_freeze(struct fl
|
||||
unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
|
||||
u32 reg;
|
||||
|
||||
- reg = flexcan_read(®s->mcr);
|
||||
+ reg = priv->read(®s->mcr);
|
||||
reg |= FLEXCAN_MCR_HALT;
|
||||
- flexcan_write(reg, ®s->mcr);
|
||||
+ priv->write(reg, ®s->mcr);
|
||||
|
||||
- while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
||||
+ while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
||||
udelay(100);
|
||||
|
||||
- if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
||||
+ if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
@@ -435,14 +451,14 @@ static int flexcan_chip_unfreeze(struct
|
||||
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
||||
u32 reg;
|
||||
|
||||
- reg = flexcan_read(®s->mcr);
|
||||
+ reg = priv->read(®s->mcr);
|
||||
reg &= ~FLEXCAN_MCR_HALT;
|
||||
- flexcan_write(reg, ®s->mcr);
|
||||
+ priv->write(reg, ®s->mcr);
|
||||
|
||||
- while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
||||
+ while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
|
||||
udelay(10);
|
||||
|
||||
- if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
|
||||
+ if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
@@ -453,11 +469,11 @@ static int flexcan_chip_softreset(struct
|
||||
struct flexcan_regs __iomem *regs = priv->regs;
|
||||
unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
|
||||
|
||||
- flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
|
||||
- while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
|
||||
+ priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
|
||||
+ while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
|
||||
udelay(10);
|
||||
|
||||
- if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
|
||||
+ if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
|
||||
return -ETIMEDOUT;
|
||||
|
||||
return 0;
|
||||
@@ -468,7 +484,7 @@ static int __flexcan_get_berr_counter(co
|
||||
{
|
||||
const struct flexcan_priv *priv = netdev_priv(dev);
|
||||
struct flexcan_regs __iomem *regs = priv->regs;
|
||||
- u32 reg = flexcan_read(®s->ecr);
|
||||
+ u32 reg = priv->read(®s->ecr);
|
||||
|
||||
bec->txerr = (reg >> 0) & 0xff;
|
||||
bec->rxerr = (reg >> 8) & 0xff;
|
||||
@@ -524,24 +540,24 @@ static int flexcan_start_xmit(struct sk_
|
||||
|
||||
if (cf->can_dlc > 0) {
|
||||
data = be32_to_cpup((__be32 *)&cf->data[0]);
|
||||
- flexcan_write(data, &priv->tx_mb->data[0]);
|
||||
+ priv->write(data, &priv->tx_mb->data[0]);
|
||||
}
|
||||
if (cf->can_dlc > 4) {
|
||||
data = be32_to_cpup((__be32 *)&cf->data[4]);
|
||||
- flexcan_write(data, &priv->tx_mb->data[1]);
|
||||
+ priv->write(data, &priv->tx_mb->data[1]);
|
||||
}
|
||||
|
||||
can_put_echo_skb(skb, dev, 0);
|
||||
|
||||
- flexcan_write(can_id, &priv->tx_mb->can_id);
|
||||
- flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
|
||||
+ priv->write(can_id, &priv->tx_mb->can_id);
|
||||
+ priv->write(ctrl, &priv->tx_mb->can_ctrl);
|
||||
|
||||
/* Errata ERR005829 step8:
|
||||
* Write twice INACTIVE(0x8) code to first MB.
|
||||
*/
|
||||
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
&priv->tx_mb_reserved->can_ctrl);
|
||||
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
&priv->tx_mb_reserved->can_ctrl);
|
||||
|
||||
return NETDEV_TX_OK;
|
||||
@@ -660,7 +676,7 @@ static unsigned int flexcan_mailbox_read
|
||||
u32 code;
|
||||
|
||||
do {
|
||||
- reg_ctrl = flexcan_read(&mb->can_ctrl);
|
||||
+ reg_ctrl = priv->read(&mb->can_ctrl);
|
||||
} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
|
||||
|
||||
/* is this MB empty? */
|
||||
@@ -675,17 +691,17 @@ static unsigned int flexcan_mailbox_read
|
||||
offload->dev->stats.rx_errors++;
|
||||
}
|
||||
} else {
|
||||
- reg_iflag1 = flexcan_read(®s->iflag1);
|
||||
+ reg_iflag1 = priv->read(®s->iflag1);
|
||||
if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
|
||||
return 0;
|
||||
|
||||
- reg_ctrl = flexcan_read(&mb->can_ctrl);
|
||||
+ reg_ctrl = priv->read(&mb->can_ctrl);
|
||||
}
|
||||
|
||||
/* increase timstamp to full 32 bit */
|
||||
*timestamp = reg_ctrl << 16;
|
||||
|
||||
- reg_id = flexcan_read(&mb->can_id);
|
||||
+ reg_id = priv->read(&mb->can_id);
|
||||
if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
|
||||
cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
|
||||
else
|
||||
@@ -695,19 +711,19 @@ static unsigned int flexcan_mailbox_read
|
||||
cf->can_id |= CAN_RTR_FLAG;
|
||||
cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
|
||||
|
||||
- *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
|
||||
- *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
|
||||
+ *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
|
||||
+ *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
|
||||
|
||||
/* mark as read */
|
||||
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
|
||||
/* Clear IRQ */
|
||||
if (n < 32)
|
||||
- flexcan_write(BIT(n), ®s->iflag1);
|
||||
+ priv->write(BIT(n), ®s->iflag1);
|
||||
else
|
||||
- flexcan_write(BIT(n - 32), ®s->iflag2);
|
||||
+ priv->write(BIT(n - 32), ®s->iflag2);
|
||||
} else {
|
||||
- flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
|
||||
- flexcan_read(®s->timer);
|
||||
+ priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
|
||||
+ priv->read(®s->timer);
|
||||
}
|
||||
|
||||
return 1;
|
||||
@@ -719,8 +735,8 @@ static inline u64 flexcan_read_reg_iflag
|
||||
struct flexcan_regs __iomem *regs = priv->regs;
|
||||
u32 iflag1, iflag2;
|
||||
|
||||
- iflag2 = flexcan_read(®s->iflag2) & priv->reg_imask2_default;
|
||||
- iflag1 = flexcan_read(®s->iflag1) & priv->reg_imask1_default &
|
||||
+ iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default;
|
||||
+ iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default &
|
||||
~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
|
||||
|
||||
return (u64)iflag2 << 32 | iflag1;
|
||||
@@ -736,7 +752,7 @@ static irqreturn_t flexcan_irq(int irq,
|
||||
u32 reg_iflag1, reg_esr;
|
||||
enum can_state last_state = priv->can.state;
|
||||
|
||||
- reg_iflag1 = flexcan_read(®s->iflag1);
|
||||
+ reg_iflag1 = priv->read(®s->iflag1);
|
||||
|
||||
/* reception interrupt */
|
||||
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
|
||||
@@ -759,7 +775,8 @@ static irqreturn_t flexcan_irq(int irq,
|
||||
/* FIFO overflow interrupt */
|
||||
if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
|
||||
handled = IRQ_HANDLED;
|
||||
- flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
|
||||
+ priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
|
||||
+ ®s->iflag1);
|
||||
dev->stats.rx_over_errors++;
|
||||
dev->stats.rx_errors++;
|
||||
}
|
||||
@@ -773,18 +790,18 @@ static irqreturn_t flexcan_irq(int irq,
|
||||
can_led_event(dev, CAN_LED_EVENT_TX);
|
||||
|
||||
/* after sending a RTR frame MB is in RX mode */
|
||||
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
- &priv->tx_mb->can_ctrl);
|
||||
- flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
|
||||
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
+ &priv->tx_mb->can_ctrl);
|
||||
+ priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
|
||||
netif_wake_queue(dev);
|
||||
}
|
||||
|
||||
- reg_esr = flexcan_read(®s->esr);
|
||||
+ reg_esr = priv->read(®s->esr);
|
||||
|
||||
/* ACK all bus error and state change IRQ sources */
|
||||
if (reg_esr & FLEXCAN_ESR_ALL_INT) {
|
||||
handled = IRQ_HANDLED;
|
||||
- flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
|
||||
+ priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
|
||||
}
|
||||
|
||||
/* state change interrupt or broken error state quirk fix is enabled */
|
||||
@@ -846,7 +863,7 @@ static void flexcan_set_bittiming(struct
|
||||
struct flexcan_regs __iomem *regs = priv->regs;
|
||||
u32 reg;
|
||||
|
||||
- reg = flexcan_read(®s->ctrl);
|
||||
+ reg = priv->read(®s->ctrl);
|
||||
reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
|
||||
FLEXCAN_CTRL_RJW(0x3) |
|
||||
FLEXCAN_CTRL_PSEG1(0x7) |
|
||||
@@ -870,11 +887,11 @@ static void flexcan_set_bittiming(struct
|
||||
reg |= FLEXCAN_CTRL_SMP;
|
||||
|
||||
netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
|
||||
- flexcan_write(reg, ®s->ctrl);
|
||||
+ priv->write(reg, ®s->ctrl);
|
||||
|
||||
/* print chip status */
|
||||
netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
|
||||
- flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
|
||||
+ priv->read(®s->mcr), priv->read(®s->ctrl));
|
||||
}
|
||||
|
||||
/* flexcan_chip_start
|
||||
@@ -913,7 +930,7 @@ static int flexcan_chip_start(struct net
|
||||
* choose format C
|
||||
* set max mailbox number
|
||||
*/
|
||||
- reg_mcr = flexcan_read(®s->mcr);
|
||||
+ reg_mcr = priv->read(®s->mcr);
|
||||
reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
|
||||
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
|
||||
FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
|
||||
@@ -927,7 +944,7 @@ static int flexcan_chip_start(struct net
|
||||
FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
|
||||
}
|
||||
netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
|
||||
- flexcan_write(reg_mcr, ®s->mcr);
|
||||
+ priv->write(reg_mcr, ®s->mcr);
|
||||
|
||||
/* CTRL
|
||||
*
|
||||
@@ -940,7 +957,7 @@ static int flexcan_chip_start(struct net
|
||||
* enable bus off interrupt
|
||||
* (== FLEXCAN_CTRL_ERR_STATE)
|
||||
*/
|
||||
- reg_ctrl = flexcan_read(®s->ctrl);
|
||||
+ reg_ctrl = priv->read(®s->ctrl);
|
||||
reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
|
||||
reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
|
||||
FLEXCAN_CTRL_ERR_STATE;
|
||||
@@ -960,45 +977,45 @@ static int flexcan_chip_start(struct net
|
||||
/* leave interrupts disabled for now */
|
||||
reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
|
||||
netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
|
||||
- flexcan_write(reg_ctrl, ®s->ctrl);
|
||||
+ priv->write(reg_ctrl, ®s->ctrl);
|
||||
|
||||
if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
|
||||
- reg_ctrl2 = flexcan_read(®s->ctrl2);
|
||||
+ reg_ctrl2 = priv->read(®s->ctrl2);
|
||||
reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
|
||||
- flexcan_write(reg_ctrl2, ®s->ctrl2);
|
||||
+ priv->write(reg_ctrl2, ®s->ctrl2);
|
||||
}
|
||||
|
||||
/* clear and invalidate all mailboxes first */
|
||||
for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
|
||||
- flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
|
||||
- ®s->mb[i].can_ctrl);
|
||||
+ priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
|
||||
+ ®s->mb[i].can_ctrl);
|
||||
}
|
||||
|
||||
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
|
||||
for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
|
||||
- flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
|
||||
- ®s->mb[i].can_ctrl);
|
||||
+ priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
|
||||
+ ®s->mb[i].can_ctrl);
|
||||
}
|
||||
|
||||
/* Errata ERR005829: mark first TX mailbox as INACTIVE */
|
||||
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
- &priv->tx_mb_reserved->can_ctrl);
|
||||
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
+ &priv->tx_mb_reserved->can_ctrl);
|
||||
|
||||
/* mark TX mailbox as INACTIVE */
|
||||
- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
- &priv->tx_mb->can_ctrl);
|
||||
+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
+ &priv->tx_mb->can_ctrl);
|
||||
|
||||
/* acceptance mask/acceptance code (accept everything) */
|
||||
- flexcan_write(0x0, ®s->rxgmask);
|
||||
- flexcan_write(0x0, ®s->rx14mask);
|
||||
- flexcan_write(0x0, ®s->rx15mask);
|
||||
+ priv->write(0x0, ®s->rxgmask);
|
||||
+ priv->write(0x0, ®s->rx14mask);
|
||||
+ priv->write(0x0, ®s->rx15mask);
|
||||
|
||||
if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
|
||||
- flexcan_write(0x0, ®s->rxfgmask);
|
||||
+ priv->write(0x0, ®s->rxfgmask);
|
||||
|
||||
/* clear acceptance filters */
|
||||
for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
|
||||
- flexcan_write(0, ®s->rximr[i]);
|
||||
+ priv->write(0, ®s->rximr[i]);
|
||||
|
||||
/* On Vybrid, disable memory error detection interrupts
|
||||
* and freeze mode.
|
||||
@@ -1011,16 +1028,16 @@ static int flexcan_chip_start(struct net
|
||||
* and Correction of Memory Errors" to write to
|
||||
* MECR register
|
||||
*/
|
||||
- reg_ctrl2 = flexcan_read(®s->ctrl2);
|
||||
+ reg_ctrl2 = priv->read(®s->ctrl2);
|
||||
reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
|
||||
- flexcan_write(reg_ctrl2, ®s->ctrl2);
|
||||
+ priv->write(reg_ctrl2, ®s->ctrl2);
|
||||
|
||||
- reg_mecr = flexcan_read(®s->mecr);
|
||||
+ reg_mecr = priv->read(®s->mecr);
|
||||
reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
|
||||
- flexcan_write(reg_mecr, ®s->mecr);
|
||||
+ priv->write(reg_mecr, ®s->mecr);
|
||||
reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
|
||||
FLEXCAN_MECR_FANCEI_MSK);
|
||||
- flexcan_write(reg_mecr, ®s->mecr);
|
||||
+ priv->write(reg_mecr, ®s->mecr);
|
||||
}
|
||||
|
||||
err = flexcan_transceiver_enable(priv);
|
||||
@@ -1036,14 +1053,14 @@ static int flexcan_chip_start(struct net
|
||||
|
||||
/* enable interrupts atomically */
|
||||
disable_irq(dev->irq);
|
||||
- flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
|
||||
- flexcan_write(priv->reg_imask1_default, ®s->imask1);
|
||||
- flexcan_write(priv->reg_imask2_default, ®s->imask2);
|
||||
+ priv->write(priv->reg_ctrl_default, ®s->ctrl);
|
||||
+ priv->write(priv->reg_imask1_default, ®s->imask1);
|
||||
+ priv->write(priv->reg_imask2_default, ®s->imask2);
|
||||
enable_irq(dev->irq);
|
||||
|
||||
/* print chip status */
|
||||
netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
|
||||
- flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
|
||||
+ priv->read(®s->mcr), priv->read(®s->ctrl));
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1068,10 +1085,10 @@ static void flexcan_chip_stop(struct net
|
||||
flexcan_chip_disable(priv);
|
||||
|
||||
/* Disable all interrupts */
|
||||
- flexcan_write(0, ®s->imask2);
|
||||
- flexcan_write(0, ®s->imask1);
|
||||
- flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
|
||||
- ®s->ctrl);
|
||||
+ priv->write(0, ®s->imask2);
|
||||
+ priv->write(0, ®s->imask1);
|
||||
+ priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
|
||||
+ ®s->ctrl);
|
||||
|
||||
flexcan_transceiver_disable(priv);
|
||||
priv->can.state = CAN_STATE_STOPPED;
|
||||
@@ -1186,26 +1203,26 @@ static int register_flexcandev(struct ne
|
||||
err = flexcan_chip_disable(priv);
|
||||
if (err)
|
||||
goto out_disable_per;
|
||||
- reg = flexcan_read(®s->ctrl);
|
||||
+ reg = priv->read(®s->ctrl);
|
||||
reg |= FLEXCAN_CTRL_CLK_SRC;
|
||||
- flexcan_write(reg, ®s->ctrl);
|
||||
+ priv->write(reg, ®s->ctrl);
|
||||
|
||||
err = flexcan_chip_enable(priv);
|
||||
if (err)
|
||||
goto out_chip_disable;
|
||||
|
||||
/* set freeze, halt and activate FIFO, restrict register access */
|
||||
- reg = flexcan_read(®s->mcr);
|
||||
+ reg = priv->read(®s->mcr);
|
||||
reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
|
||||
FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
|
||||
- flexcan_write(reg, ®s->mcr);
|
||||
+ priv->write(reg, ®s->mcr);
|
||||
|
||||
/* Currently we only support newer versions of this core
|
||||
* featuring a RX hardware FIFO (although this driver doesn't
|
||||
* make use of it on some cores). Older cores, found on some
|
||||
* Coldfire derivates are not tested.
|
||||
*/
|
||||
- reg = flexcan_read(®s->mcr);
|
||||
+ reg = priv->read(®s->mcr);
|
||||
if (!(reg & FLEXCAN_MCR_FEN)) {
|
||||
netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
|
||||
err = -ENODEV;
|
||||
@@ -1233,8 +1250,12 @@ static void unregister_flexcandev(struct
|
||||
static const struct of_device_id flexcan_of_match[] = {
|
||||
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
|
||||
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
|
||||
+ { .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
|
||||
+ { .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
|
||||
+ { .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
|
||||
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
|
||||
{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
|
||||
+ { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, flexcan_of_match);
|
||||
@@ -1314,6 +1335,21 @@ static int flexcan_probe(struct platform
|
||||
dev->flags |= IFF_ECHO;
|
||||
|
||||
priv = netdev_priv(dev);
|
||||
+
|
||||
+ if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
|
||||
+ priv->read = flexcan_read_be;
|
||||
+ priv->write = flexcan_write_be;
|
||||
+ } else {
|
||||
+ if (of_device_is_compatible(pdev->dev.of_node,
|
||||
+ "fsl,p1010-flexcan")) {
|
||||
+ priv->read = flexcan_read_be;
|
||||
+ priv->write = flexcan_write_be;
|
||||
+ } else {
|
||||
+ priv->read = flexcan_read_le;
|
||||
+ priv->write = flexcan_write_le;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
priv->can.clock.freq = clock_freq;
|
||||
priv->can.bittiming_const = &flexcan_bittiming_const;
|
||||
priv->can.do_set_mode = flexcan_set_mode;
|
||||
@ -0,0 +1,208 @@
|
||||
From 621f2c4753b03170213e178cdafd66e78b212b3c Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:41 +0800
|
||||
Subject: [PATCH 27/40] kvm: support layerscape
|
||||
This is an integrated patch of kvm for layerscape
|
||||
|
||||
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
|
||||
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
|
||||
Signed-off-by: Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
arch/arm/include/asm/kvm_mmu.h | 3 +-
|
||||
arch/arm64/include/asm/kvm_mmu.h | 14 ++++++--
|
||||
arch/powerpc/kvm/booke.c | 5 +++
|
||||
virt/kvm/arm/mmu.c | 56 ++++++++++++++++++++++++++++++--
|
||||
virt/kvm/arm/vgic/vgic-its.c | 2 +-
|
||||
virt/kvm/arm/vgic/vgic-v2.c | 3 +-
|
||||
6 files changed, 74 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/arch/arm/include/asm/kvm_mmu.h
|
||||
+++ b/arch/arm/include/asm/kvm_mmu.h
|
||||
@@ -55,7 +55,8 @@ void stage2_unmap_vm(struct kvm *kvm);
|
||||
int kvm_alloc_stage2_pgd(struct kvm *kvm);
|
||||
void kvm_free_stage2_pgd(struct kvm *kvm);
|
||||
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
|
||||
- phys_addr_t pa, unsigned long size, bool writable);
|
||||
+ phys_addr_t pa, unsigned long size, bool writable,
|
||||
+ pgprot_t prot);
|
||||
|
||||
int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
|
||||
|
||||
--- a/arch/arm64/include/asm/kvm_mmu.h
|
||||
+++ b/arch/arm64/include/asm/kvm_mmu.h
|
||||
@@ -167,7 +167,8 @@ void stage2_unmap_vm(struct kvm *kvm);
|
||||
int kvm_alloc_stage2_pgd(struct kvm *kvm);
|
||||
void kvm_free_stage2_pgd(struct kvm *kvm);
|
||||
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
|
||||
- phys_addr_t pa, unsigned long size, bool writable);
|
||||
+ phys_addr_t pa, unsigned long size, bool writable,
|
||||
+ pgprot_t prot);
|
||||
|
||||
int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
|
||||
|
||||
@@ -270,8 +271,15 @@ static inline void __coherent_cache_gues
|
||||
|
||||
static inline void __kvm_flush_dcache_pte(pte_t pte)
|
||||
{
|
||||
- struct page *page = pte_page(pte);
|
||||
- kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
|
||||
+ if (pfn_valid(pte_pfn(pte))) {
|
||||
+ struct page *page = pte_page(pte);
|
||||
+ kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
|
||||
+ } else {
|
||||
+ void __iomem *va = ioremap_cache_ns(pte_pfn(pte) << PAGE_SHIFT, PAGE_SIZE);
|
||||
+
|
||||
+ kvm_flush_dcache_to_poc(va, PAGE_SIZE);
|
||||
+ iounmap(va);
|
||||
+ }
|
||||
}
|
||||
|
||||
static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
|
||||
--- a/arch/powerpc/kvm/booke.c
|
||||
+++ b/arch/powerpc/kvm/booke.c
|
||||
@@ -305,6 +305,11 @@ void kvmppc_core_queue_fpunavail(struct
|
||||
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
|
||||
}
|
||||
|
||||
+void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu)
|
||||
+{
|
||||
+ kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
|
||||
+}
|
||||
+
|
||||
void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DECREMENTER);
|
||||
--- a/virt/kvm/arm/mmu.c
|
||||
+++ b/virt/kvm/arm/mmu.c
|
||||
@@ -1027,9 +1027,11 @@ static int stage2_pmdp_test_and_clear_yo
|
||||
* @guest_ipa: The IPA at which to insert the mapping
|
||||
* @pa: The physical address of the device
|
||||
* @size: The size of the mapping
|
||||
+ * @prot: S2 page translation bits
|
||||
*/
|
||||
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
|
||||
- phys_addr_t pa, unsigned long size, bool writable)
|
||||
+ phys_addr_t pa, unsigned long size, bool writable,
|
||||
+ pgprot_t prot)
|
||||
{
|
||||
phys_addr_t addr, end;
|
||||
int ret = 0;
|
||||
@@ -1040,7 +1042,7 @@ int kvm_phys_addr_ioremap(struct kvm *kv
|
||||
pfn = __phys_to_pfn(pa);
|
||||
|
||||
for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
|
||||
- pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
|
||||
+ pte_t pte = pfn_pte(pfn, prot);
|
||||
|
||||
if (writable)
|
||||
pte = kvm_s2pte_mkwrite(pte);
|
||||
@@ -1064,6 +1066,30 @@ out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_ARM64
|
||||
+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
|
||||
+{
|
||||
+ switch (pgprot_val(prot) & PTE_ATTRINDX_MASK) {
|
||||
+ case PTE_ATTRINDX(MT_DEVICE_nGnRE):
|
||||
+ case PTE_ATTRINDX(MT_DEVICE_nGnRnE):
|
||||
+ case PTE_ATTRINDX(MT_DEVICE_GRE):
|
||||
+ return PAGE_S2_DEVICE;
|
||||
+ case PTE_ATTRINDX(MT_NORMAL_NC):
|
||||
+ case PTE_ATTRINDX(MT_NORMAL):
|
||||
+ return (pgprot_val(prot) & PTE_SHARED)
|
||||
+ ? PAGE_S2
|
||||
+ : PAGE_S2_NS;
|
||||
+ }
|
||||
+
|
||||
+ return PAGE_S2_DEVICE;
|
||||
+}
|
||||
+#else
|
||||
+static pgprot_t stage1_to_stage2_pgprot(pgprot_t prot)
|
||||
+{
|
||||
+ return PAGE_S2_DEVICE;
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
static bool transparent_hugepage_adjust(kvm_pfn_t *pfnp, phys_addr_t *ipap)
|
||||
{
|
||||
kvm_pfn_t pfn = *pfnp;
|
||||
@@ -1334,6 +1360,18 @@ static int user_mem_abort(struct kvm_vcp
|
||||
hugetlb = true;
|
||||
gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
|
||||
} else {
|
||||
+ pte_t *pte;
|
||||
+ spinlock_t *ptl;
|
||||
+ pgprot_t prot;
|
||||
+
|
||||
+ pte = get_locked_pte(current->mm, memslot->userspace_addr, &ptl);
|
||||
+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
|
||||
+ pte_unmap_unlock(pte, ptl);
|
||||
+#ifdef CONFIG_ARM64
|
||||
+ if (pgprot_val(prot) == pgprot_val(PAGE_S2_NS))
|
||||
+ mem_type = PAGE_S2_NS;
|
||||
+#endif
|
||||
+
|
||||
/*
|
||||
* Pages belonging to memslots that don't have the same
|
||||
* alignment for userspace and IPA cannot be mapped using
|
||||
@@ -1375,6 +1413,11 @@ static int user_mem_abort(struct kvm_vcp
|
||||
if (is_error_noslot_pfn(pfn))
|
||||
return -EFAULT;
|
||||
|
||||
+#ifdef CONFIG_ARM64
|
||||
+ if (pgprot_val(mem_type) == pgprot_val(PAGE_S2_NS)) {
|
||||
+ flags |= KVM_S2PTE_FLAG_IS_IOMAP;
|
||||
+ } else
|
||||
+#endif
|
||||
if (kvm_is_device_pfn(pfn)) {
|
||||
mem_type = PAGE_S2_DEVICE;
|
||||
flags |= KVM_S2PTE_FLAG_IS_IOMAP;
|
||||
@@ -1911,6 +1954,9 @@ int kvm_arch_prepare_memory_region(struc
|
||||
gpa_t gpa = mem->guest_phys_addr +
|
||||
(vm_start - mem->userspace_addr);
|
||||
phys_addr_t pa;
|
||||
+ pgprot_t prot;
|
||||
+ pte_t *pte;
|
||||
+ spinlock_t *ptl;
|
||||
|
||||
pa = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT;
|
||||
pa += vm_start - vma->vm_start;
|
||||
@@ -1921,9 +1967,13 @@ int kvm_arch_prepare_memory_region(struc
|
||||
goto out;
|
||||
}
|
||||
|
||||
+ pte = get_locked_pte(current->mm, mem->userspace_addr, &ptl);
|
||||
+ prot = stage1_to_stage2_pgprot(__pgprot(pte_val(*pte)));
|
||||
+ pte_unmap_unlock(pte, ptl);
|
||||
+
|
||||
ret = kvm_phys_addr_ioremap(kvm, gpa, pa,
|
||||
vm_end - vm_start,
|
||||
- writable);
|
||||
+ writable, prot);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
--- a/virt/kvm/arm/vgic/vgic-its.c
|
||||
+++ b/virt/kvm/arm/vgic/vgic-its.c
|
||||
@@ -243,7 +243,7 @@ static struct its_ite *find_ite(struct v
|
||||
#define GIC_LPI_OFFSET 8192
|
||||
|
||||
#define VITS_TYPER_IDBITS 16
|
||||
-#define VITS_TYPER_DEVBITS 16
|
||||
+#define VITS_TYPER_DEVBITS 17
|
||||
#define VITS_DTE_MAX_DEVID_OFFSET (BIT(14) - 1)
|
||||
#define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16) - 1)
|
||||
|
||||
--- a/virt/kvm/arm/vgic/vgic-v2.c
|
||||
+++ b/virt/kvm/arm/vgic/vgic-v2.c
|
||||
@@ -304,7 +304,8 @@ int vgic_v2_map_resources(struct kvm *kv
|
||||
if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
|
||||
ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
|
||||
kvm_vgic_global_state.vcpu_base,
|
||||
- KVM_VGIC_V2_CPU_SIZE, true);
|
||||
+ KVM_VGIC_V2_CPU_SIZE, true,
|
||||
+ PAGE_S2_DEVICE);
|
||||
if (ret) {
|
||||
kvm_err("Unable to remap VGIC CPU to VCPU\n");
|
||||
goto out;
|
||||
@ -0,0 +1,37 @@
|
||||
From d94f8863307c0f7fb7aeb2084cc666c47991d78b Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Mon, 19 Nov 2018 10:26:57 +0800
|
||||
Subject: [PATCH] clock: support layerscape
|
||||
This is an integrated patch of clock for layerscape
|
||||
|
||||
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/clk/clk-qoriq.c | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/clk-qoriq.c
|
||||
+++ b/drivers/clk/clk-qoriq.c
|
||||
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
|
||||
};
|
||||
|
||||
struct clockgen_pll {
|
||||
- struct clockgen_pll_div div[4];
|
||||
+ struct clockgen_pll_div div[8];
|
||||
};
|
||||
|
||||
#define CLKSEL_VALID 1
|
||||
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
+ /*
|
||||
+ * For platform PLL, there are 8 divider clocks.
|
||||
+ * For core PLL, there are 4 divider clocks at most.
|
||||
+ */
|
||||
+ if (idx != 0 && i >= 4)
|
||||
+ break;
|
||||
+
|
||||
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
|
||||
"cg-pll%d-div%d", idx, i + 1);
|
||||
|
||||
@ -0,0 +1,182 @@
|
||||
From 31d0f8f19246c9a2fbecb5ca0a03ef6bb70eee2d Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Fri, 9 Nov 2018 19:32:53 +0800
|
||||
Subject: [PATCH] flexspi: support layerscape
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This is an integrated patch of flexspi for layerscape
|
||||
|
||||
Signed-off-by: Alistair Strachan <astrachan@google.com>
|
||||
Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com>
|
||||
Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
Signed-off-by: Joe Thornber <ejt@redhat.com>
|
||||
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
|
||||
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
|
||||
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
Signed-off-by: Mike Snitzer <snitzer@redhat.com>
|
||||
Signed-off-by: Peng Li <lipeng321@huawei.com>
|
||||
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
|
||||
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
|
||||
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
||||
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
|
||||
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/md/dm-thin.c | 13 +++++++++++++
|
||||
drivers/net/ethernet/qlogic/qed/qed_mcp.c | 7 +++++++
|
||||
drivers/net/phy/xilinx_gmii2rgmii.c | 5 +++++
|
||||
drivers/spi/spi-tegra20-slink.c | 18 ++++++++++++++++++
|
||||
drivers/staging/android/ashmem.c | 6 ++++++
|
||||
drivers/tty/serial/imx.c | 8 ++++++++
|
||||
kernel/events/core.c | 6 ++++++
|
||||
sound/soc/soc-dapm.c | 7 +++++++
|
||||
8 files changed, 70 insertions(+)
|
||||
|
||||
--- a/drivers/md/dm-thin.c
|
||||
+++ b/drivers/md/dm-thin.c
|
||||
@@ -3643,6 +3643,19 @@ static int process_create_thin_mesg(unsi
|
||||
return r;
|
||||
}
|
||||
|
||||
+ r = dm_pool_get_free_metadata_block_count(pool->pmd, &free_blocks);
|
||||
+ if (r) {
|
||||
+ metadata_operation_failed(pool, "dm_pool_get_free_metadata_block_count", r);
|
||||
+ return r;
|
||||
+ }
|
||||
+
|
||||
+ if (!free_blocks) {
|
||||
+ /* Let's commit before we use up the metadata reserve. */
|
||||
+ r = commit(pool);
|
||||
+ if (r)
|
||||
+ return r;
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/drivers/net/ethernet/qlogic/qed/qed_mcp.c
|
||||
+++ b/drivers/net/ethernet/qlogic/qed/qed_mcp.c
|
||||
@@ -616,6 +616,13 @@ static int qed_mcp_cmd_and_union(struct
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
+ if (p_hwfn->mcp_info->b_block_cmd) {
|
||||
+ DP_NOTICE(p_hwfn,
|
||||
+ "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
|
||||
+ p_mb_params->cmd, p_mb_params->param);
|
||||
+ return -EBUSY;
|
||||
+ }
|
||||
+
|
||||
if (p_mb_params->data_src_size > union_data_size ||
|
||||
p_mb_params->data_dst_size > union_data_size) {
|
||||
DP_ERR(p_hwfn,
|
||||
--- a/drivers/net/phy/xilinx_gmii2rgmii.c
|
||||
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
|
||||
@@ -89,6 +89,11 @@ static int xgmiitorgmii_probe(struct mdi
|
||||
return -EPROBE_DEFER;
|
||||
}
|
||||
|
||||
+ if (!priv->phy_dev->drv) {
|
||||
+ dev_info(dev, "Attached phy not ready\n");
|
||||
+ return -EPROBE_DEFER;
|
||||
+ }
|
||||
+
|
||||
priv->addr = mdiodev->addr;
|
||||
priv->phy_drv = priv->phy_dev->drv;
|
||||
memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
|
||||
--- a/drivers/spi/spi-tegra20-slink.c
|
||||
+++ b/drivers/spi/spi-tegra20-slink.c
|
||||
@@ -1081,6 +1081,24 @@ static int tegra_slink_probe(struct plat
|
||||
goto exit_free_master;
|
||||
}
|
||||
|
||||
+ /* disabled clock may cause interrupt storm upon request */
|
||||
+ tspi->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
+ if (IS_ERR(tspi->clk)) {
|
||||
+ ret = PTR_ERR(tspi->clk);
|
||||
+ dev_err(&pdev->dev, "Can not get clock %d\n", ret);
|
||||
+ goto exit_free_master;
|
||||
+ }
|
||||
+ ret = clk_prepare(tspi->clk);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(&pdev->dev, "Clock prepare failed %d\n", ret);
|
||||
+ goto exit_free_master;
|
||||
+ }
|
||||
+ ret = clk_enable(tspi->clk);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(&pdev->dev, "Clock enable failed %d\n", ret);
|
||||
+ goto exit_free_master;
|
||||
+ }
|
||||
+
|
||||
spi_irq = platform_get_irq(pdev, 0);
|
||||
tspi->irq = spi_irq;
|
||||
ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
|
||||
--- a/drivers/staging/android/ashmem.c
|
||||
+++ b/drivers/staging/android/ashmem.c
|
||||
@@ -380,6 +380,12 @@ static int ashmem_mmap(struct file *file
|
||||
goto out;
|
||||
}
|
||||
|
||||
+ /* requested mapping size larger than object size */
|
||||
+ if (vma->vm_end - vma->vm_start > PAGE_ALIGN(asma->size)) {
|
||||
+ ret = -EINVAL;
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
/* requested protection bits must match our allowed protection mask */
|
||||
if (unlikely((vma->vm_flags & ~calc_vm_prot_bits(asma->prot_mask, 0)) &
|
||||
calc_vm_prot_bits(PROT_MASK, 0))) {
|
||||
--- a/drivers/tty/serial/imx.c
|
||||
+++ b/drivers/tty/serial/imx.c
|
||||
@@ -2221,6 +2221,14 @@ static int serial_imx_probe(struct platf
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
+
|
||||
+ ret = devm_request_irq(&pdev->dev, rtsirq, imx_rtsint, 0,
|
||||
+ dev_name(&pdev->dev), sport);
|
||||
+ if (ret) {
|
||||
+ dev_err(&pdev->dev, "failed to request rts irq: %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
} else {
|
||||
ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
|
||||
dev_name(&pdev->dev), sport);
|
||||
--- a/kernel/events/core.c
|
||||
+++ b/kernel/events/core.c
|
||||
@@ -3763,6 +3763,12 @@ int perf_event_read_local(struct perf_ev
|
||||
goto out;
|
||||
}
|
||||
|
||||
+ /* If this is a pinned event it must be running on this CPU */
|
||||
+ if (event->attr.pinned && event->oncpu != smp_processor_id()) {
|
||||
+ ret = -EBUSY;
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
/*
|
||||
* If the event is currently on this CPU, its either a per-task event,
|
||||
* or local to this CPU. Furthermore it means its ACTIVE (otherwise
|
||||
--- a/sound/soc/soc-dapm.c
|
||||
+++ b/sound/soc/soc-dapm.c
|
||||
@@ -4012,6 +4012,13 @@ int snd_soc_dapm_link_dai_widgets(struct
|
||||
continue;
|
||||
}
|
||||
|
||||
+ /* let users know there is no DAI to link */
|
||||
+ if (!dai_w->priv) {
|
||||
+ dev_dbg(card->dev, "dai widget %s has no DAI\n",
|
||||
+ dai_w->name);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
dai = dai_w->priv;
|
||||
|
||||
/* ...find all widgets with the same stream and link them */
|
||||
@ -0,0 +1,356 @@
|
||||
From 780865643e5dbf41fe950924a68f7ee4fea8af3e Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:39 +0800
|
||||
Subject: [PATCH 30/40] ifc-nor-nand: support layerscape
|
||||
This is an integrated patch of ifc-nor-nand for
|
||||
layerscape
|
||||
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/memory/fsl_ifc.c | 263 +++++++++++++++++++++++++++++
|
||||
drivers/mtd/maps/physmap_of_core.c | 4 +
|
||||
include/linux/fsl_ifc.h | 7 +
|
||||
3 files changed, 274 insertions(+)
|
||||
|
||||
--- a/drivers/memory/fsl_ifc.c
|
||||
+++ b/drivers/memory/fsl_ifc.c
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/spinlock.h>
|
||||
+#include <linux/delay.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
@@ -37,6 +38,8 @@
|
||||
|
||||
struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
|
||||
EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
|
||||
+#define FSL_IFC_V1_3_0 0x01030000
|
||||
+#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
|
||||
|
||||
/*
|
||||
* convert_ifc_address - convert the base address
|
||||
@@ -311,6 +314,261 @@ err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_PM_SLEEP
|
||||
+/* save ifc registers */
|
||||
+static int fsl_ifc_suspend(struct device *dev)
|
||||
+{
|
||||
+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
|
||||
+ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
|
||||
+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
|
||||
+ __be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
|
||||
+ gpcm_evter_intr_en;
|
||||
+ uint32_t ifc_bank, i;
|
||||
+
|
||||
+ ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
|
||||
+ if (!ctrl->saved_gregs)
|
||||
+ return -ENOMEM;
|
||||
+ ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
|
||||
+ if (!ctrl->saved_rregs)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
|
||||
+ nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
|
||||
+ nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
|
||||
+ gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
|
||||
+
|
||||
+/* IFC interrupts disabled */
|
||||
+
|
||||
+ ifc_out32(0x0, &fcm->cm_evter_intr_en);
|
||||
+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
|
||||
+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
|
||||
+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
||||
+
|
||||
+ if (ctrl->saved_gregs) {
|
||||
+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
|
||||
+ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
|
||||
+ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
|
||||
+ ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
|
||||
+ ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
|
||||
+ ctrl->saved_gregs->amask_cs[ifc_bank].amask =
|
||||
+ ifc_in32(&fcm->amask_cs[ifc_bank].amask);
|
||||
+ ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
|
||||
+ ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
|
||||
+ ctrl->saved_gregs->csor_cs[ifc_bank].csor =
|
||||
+ ifc_in32(&fcm->csor_cs[ifc_bank].csor);
|
||||
+ for (i = 0; i < 4; i++) {
|
||||
+ ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
|
||||
+ ifc_in32(
|
||||
+ &fcm->ftim_cs[ifc_bank].ftim[i]);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
|
||||
+ ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
|
||||
+ ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
|
||||
+ ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
|
||||
+ ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
|
||||
+ }
|
||||
+
|
||||
+ if (ctrl->saved_rregs) {
|
||||
+ /* IFC controller NAND machine registers */
|
||||
+ ctrl->saved_rregs->ifc_nand.ncfgr =
|
||||
+ ifc_in32(&runtime->ifc_nand.ncfgr);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_fcr0 =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_fcr0);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_fcr1 =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_fcr1);
|
||||
+ ctrl->saved_rregs->ifc_nand.row0 =
|
||||
+ ifc_in32(&runtime->ifc_nand.row0);
|
||||
+ ctrl->saved_rregs->ifc_nand.row1 =
|
||||
+ ifc_in32(&runtime->ifc_nand.row1);
|
||||
+ ctrl->saved_rregs->ifc_nand.col0 =
|
||||
+ ifc_in32(&runtime->ifc_nand.col0);
|
||||
+ ctrl->saved_rregs->ifc_nand.col1 =
|
||||
+ ifc_in32(&runtime->ifc_nand.col1);
|
||||
+ ctrl->saved_rregs->ifc_nand.row2 =
|
||||
+ ifc_in32(&runtime->ifc_nand.row2);
|
||||
+ ctrl->saved_rregs->ifc_nand.col2 =
|
||||
+ ifc_in32(&runtime->ifc_nand.col2);
|
||||
+ ctrl->saved_rregs->ifc_nand.row3 =
|
||||
+ ifc_in32(&runtime->ifc_nand.row3);
|
||||
+ ctrl->saved_rregs->ifc_nand.col3 =
|
||||
+ ifc_in32(&runtime->ifc_nand.col3);
|
||||
+
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_fbcr =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_fbcr);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_fir0 =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_fir0);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_fir1 =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_fir1);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_fir2 =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_fir2);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_csel =
|
||||
+ ifc_in32(&runtime->ifc_nand.nand_csel);
|
||||
+ ctrl->saved_rregs->ifc_nand.nandseq_strt =
|
||||
+ ifc_in32(
|
||||
+ &runtime->ifc_nand.nandseq_strt);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_evter_en =
|
||||
+ ifc_in32(
|
||||
+ &runtime->ifc_nand.nand_evter_en);
|
||||
+ ctrl->saved_rregs->ifc_nand.nanndcr =
|
||||
+ ifc_in32(&runtime->ifc_nand.nanndcr);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
|
||||
+ ifc_in32(
|
||||
+ &runtime->ifc_nand.nand_dll_lowcfg0);
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
|
||||
+ ifc_in32(
|
||||
+ &runtime->ifc_nand.nand_dll_lowcfg1);
|
||||
+
|
||||
+ /* IFC controller NOR machine registers */
|
||||
+ ctrl->saved_rregs->ifc_nor.nor_evter_en =
|
||||
+ ifc_in32(
|
||||
+ &runtime->ifc_nor.nor_evter_en);
|
||||
+ ctrl->saved_rregs->ifc_nor.norcr =
|
||||
+ ifc_in32(&runtime->ifc_nor.norcr);
|
||||
+
|
||||
+ /* IFC controller GPCM Machine registers */
|
||||
+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
|
||||
+ ifc_in32(
|
||||
+ &runtime->ifc_gpcm.gpcm_evter_en);
|
||||
+ }
|
||||
+
|
||||
+/* save the interrupt values */
|
||||
+ ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
|
||||
+ ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
|
||||
+ ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
|
||||
+ ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/* restore ifc registers */
|
||||
+static int fsl_ifc_resume(struct device *dev)
|
||||
+{
|
||||
+ struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
|
||||
+ struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
|
||||
+ struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
|
||||
+ struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
|
||||
+ struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
|
||||
+ uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
|
||||
+
|
||||
+/*
|
||||
+ * IFC interrupts disabled
|
||||
+ */
|
||||
+ ifc_out32(0x0, &fcm->cm_evter_intr_en);
|
||||
+ ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
|
||||
+ ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
|
||||
+ ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
||||
+
|
||||
+
|
||||
+ if (ctrl->saved_gregs) {
|
||||
+ for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
|
||||
+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
|
||||
+ &fcm->cspr_cs[ifc_bank].cspr_ext);
|
||||
+ ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
|
||||
+ &fcm->cspr_cs[ifc_bank].cspr);
|
||||
+ ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
|
||||
+ &fcm->amask_cs[ifc_bank].amask);
|
||||
+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
|
||||
+ &fcm->csor_cs[ifc_bank].csor_ext);
|
||||
+ ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
|
||||
+ &fcm->csor_cs[ifc_bank].csor);
|
||||
+ for (i = 0; i < 4; i++) {
|
||||
+ ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
|
||||
+ &fcm->ftim_cs[ifc_bank].ftim[i]);
|
||||
+ }
|
||||
+ }
|
||||
+ ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
|
||||
+ ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
|
||||
+ ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
|
||||
+ ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
|
||||
+ ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
|
||||
+ }
|
||||
+
|
||||
+ if (ctrl->saved_rregs) {
|
||||
+ /* IFC controller NAND machine registers */
|
||||
+ ifc_out32(savd_rregs->ifc_nand.ncfgr,
|
||||
+ &runtime->ifc_nand.ncfgr);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
|
||||
+ &runtime->ifc_nand.nand_fcr0);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
|
||||
+ &runtime->ifc_nand.nand_fcr1);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
|
||||
+ &runtime->ifc_nand.nand_fbcr);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_fir0,
|
||||
+ &runtime->ifc_nand.nand_fir0);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_fir1,
|
||||
+ &runtime->ifc_nand.nand_fir1);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_fir2,
|
||||
+ &runtime->ifc_nand.nand_fir2);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_csel,
|
||||
+ &runtime->ifc_nand.nand_csel);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
|
||||
+ &runtime->ifc_nand.nandseq_strt);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
|
||||
+ &runtime->ifc_nand.nand_evter_en);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nanndcr,
|
||||
+ &runtime->ifc_nand.nanndcr);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
|
||||
+ &runtime->ifc_nand.nand_dll_lowcfg0);
|
||||
+ ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
|
||||
+ &runtime->ifc_nand.nand_dll_lowcfg1);
|
||||
+
|
||||
+ /* IFC controller NOR machine registers */
|
||||
+ ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
|
||||
+ &runtime->ifc_nor.nor_evter_en);
|
||||
+ ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
|
||||
+
|
||||
+ /* IFC controller GPCM Machine registers */
|
||||
+ ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
|
||||
+ &runtime->ifc_gpcm.gpcm_evter_en);
|
||||
+
|
||||
+ /* IFC interrupts enabled */
|
||||
+ ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
|
||||
+ &fcm->cm_evter_intr_en);
|
||||
+ ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
|
||||
+ &runtime->ifc_nand.nand_evter_intr_en);
|
||||
+ ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
|
||||
+ &runtime->ifc_nor.nor_evter_intr_en);
|
||||
+ ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
|
||||
+ &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
||||
+
|
||||
+ kfree(ctrl->saved_gregs);
|
||||
+ kfree(ctrl->saved_rregs);
|
||||
+ ctrl->saved_gregs = NULL;
|
||||
+ ctrl->saved_rregs = NULL;
|
||||
+ }
|
||||
+
|
||||
+ ver = ifc_in32(&fcm->ifc_rev);
|
||||
+ ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
|
||||
+ if (ver >= FSL_IFC_V1_3_0) {
|
||||
+
|
||||
+ ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
|
||||
+ &runtime->ifc_nand.ncfgr);
|
||||
+ /* wait for SRAM_INIT bit to be clear or timeout */
|
||||
+ timeout = 10;
|
||||
+ while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
|
||||
+ IFC_NAND_SRAM_INIT_EN) && timeout) {
|
||||
+ mdelay(IFC_TIMEOUT_MSECS);
|
||||
+ timeout--;
|
||||
+ }
|
||||
+
|
||||
+ if (!timeout)
|
||||
+ dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+#endif /* CONFIG_PM_SLEEP */
|
||||
+
|
||||
static const struct of_device_id fsl_ifc_match[] = {
|
||||
{
|
||||
.compatible = "fsl,ifc",
|
||||
@@ -318,10 +576,15 @@ static const struct of_device_id fsl_ifc
|
||||
{},
|
||||
};
|
||||
|
||||
+static const struct dev_pm_ops ifc_pm_ops = {
|
||||
+ SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
|
||||
+};
|
||||
+
|
||||
static struct platform_driver fsl_ifc_ctrl_driver = {
|
||||
.driver = {
|
||||
.name = "fsl-ifc",
|
||||
.of_match_table = fsl_ifc_match,
|
||||
+ .pm = &ifc_pm_ops,
|
||||
},
|
||||
.probe = fsl_ifc_ctrl_probe,
|
||||
.remove = fsl_ifc_ctrl_remove,
|
||||
--- a/drivers/mtd/maps/physmap_of_core.c
|
||||
+++ b/drivers/mtd/maps/physmap_of_core.c
|
||||
@@ -20,6 +20,7 @@
|
||||
#include <linux/mtd/map.h>
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/concat.h>
|
||||
+#include <linux/mtd/cfi_endian.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
@@ -205,6 +206,9 @@ static int of_flash_probe(struct platfor
|
||||
info->list[i].map.bankwidth = be32_to_cpup(width);
|
||||
info->list[i].map.device_node = dp;
|
||||
|
||||
+ if (of_property_read_bool(dp->parent, "big-endian"))
|
||||
+ info->list[i].map.swap = CFI_BIG_ENDIAN;
|
||||
+
|
||||
err = of_flash_probe_gemini(dev, dp, &info->list[i].map);
|
||||
if (err)
|
||||
goto err_out;
|
||||
--- a/include/linux/fsl_ifc.h
|
||||
+++ b/include/linux/fsl_ifc.h
|
||||
@@ -274,6 +274,8 @@
|
||||
*/
|
||||
/* Auto Boot Mode */
|
||||
#define IFC_NAND_NCFGR_BOOT 0x80000000
|
||||
+/* SRAM INIT EN */
|
||||
+#define IFC_NAND_SRAM_INIT_EN 0x20000000
|
||||
/* Addressing Mode-ROW0+n/COL0 */
|
||||
#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
|
||||
/* Addressing Mode-ROW0+n/COL0+n */
|
||||
@@ -857,6 +859,11 @@ struct fsl_ifc_ctrl {
|
||||
u32 nand_stat;
|
||||
wait_queue_head_t nand_wait;
|
||||
bool little_endian;
|
||||
+#ifdef CONFIG_PM_SLEEP
|
||||
+ /*save regs when system goes to deep sleep*/
|
||||
+ struct fsl_ifc_global *saved_gregs;
|
||||
+ struct fsl_ifc_runtime *saved_rregs;
|
||||
+#endif
|
||||
};
|
||||
|
||||
extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
|
||||
@ -0,0 +1,316 @@
|
||||
From c64d8ab6260330fa2fe9a2d676256697e4e2a83c Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:44 +0800
|
||||
Subject: [PATCH 31/40] ls2-console: support layerscape
|
||||
This is an integrated patch of ls2-console for
|
||||
layerscape
|
||||
|
||||
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/soc/fsl/ls2-console/Kconfig | 4 +
|
||||
drivers/soc/fsl/ls2-console/Makefile | 1 +
|
||||
drivers/soc/fsl/ls2-console/ls2-console.c | 284 ++++++++++++++++++++++
|
||||
3 files changed, 289 insertions(+)
|
||||
create mode 100644 drivers/soc/fsl/ls2-console/Kconfig
|
||||
create mode 100644 drivers/soc/fsl/ls2-console/Makefile
|
||||
create mode 100644 drivers/soc/fsl/ls2-console/ls2-console.c
|
||||
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/ls2-console/Kconfig
|
||||
@@ -0,0 +1,4 @@
|
||||
+config FSL_LS2_CONSOLE
|
||||
+ tristate "Layerscape MC and AIOP console support"
|
||||
+ depends on ARCH_LAYERSCAPE
|
||||
+ default y
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/ls2-console/Makefile
|
||||
@@ -0,0 +1 @@
|
||||
+obj-$(CONFIG_FSL_LS2_CONSOLE) += ls2-console.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/ls2-console/ls2-console.c
|
||||
@@ -0,0 +1,284 @@
|
||||
+/* Copyright 2015-2016 Freescale Semiconductor Inc.
|
||||
+ *
|
||||
+ * Redistribution and use in source and binary forms, with or without
|
||||
+ * modification, are permitted provided that the following conditions are met:
|
||||
+ * * Redistributions of source code must retain the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer.
|
||||
+ * * Redistributions in binary form must reproduce the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer in the
|
||||
+ * documentation and/or other materials provided with the distribution.
|
||||
+ * * Neither the name of the above-listed copyright holders nor the
|
||||
+ * names of any contributors may be used to endorse or promote products
|
||||
+ * derived from this software without specific prior written permission.
|
||||
+ *
|
||||
+ *
|
||||
+ * ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
+ * GNU General Public License ("GPL") as published by the Free Software
|
||||
+ * Foundation, either version 2 of that License or (at your option) any
|
||||
+ * later version.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
|
||||
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
+ * POSSIBILITY OF SUCH DAMAGE.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/miscdevice.h>
|
||||
+#include <linux/uaccess.h>
|
||||
+#include <linux/poll.h>
|
||||
+#include <linux/compat.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/slab.h>
|
||||
+#include <linux/io.h>
|
||||
+
|
||||
+/* SoC address for the MC firmware base low/high registers */
|
||||
+#define SOC_CCSR_MC_FW_BASE_ADDR_REGS 0x8340020
|
||||
+#define SOC_CCSR_MC_FW_BASE_ADDR_REGS_SIZE 2
|
||||
+/* MC firmware base low/high registers indexes */
|
||||
+#define MCFBALR_OFFSET 0
|
||||
+#define MCFBAHR_OFFSET 1
|
||||
+
|
||||
+/* Bit mask used to obtain the most significant part of the MC base address */
|
||||
+#define MC_FW_HIGH_ADDR_MASK 0x1FFFF
|
||||
+/* Bit mask used to obtain the least significant part of the MC base address */
|
||||
+#define MC_FW_LOW_ADDR_MASK 0xE0000000
|
||||
+
|
||||
+#define MC_BUFFER_OFFSET 0x01000000
|
||||
+#define MC_BUFFER_SIZE (1024*1024*16)
|
||||
+#define MC_OFFSET_DELTA (MC_BUFFER_OFFSET)
|
||||
+
|
||||
+#define AIOP_BUFFER_OFFSET 0x06000000
|
||||
+#define AIOP_BUFFER_SIZE (1024*1024*16)
|
||||
+#define AIOP_OFFSET_DELTA (0)
|
||||
+
|
||||
+struct log_header {
|
||||
+ char magic_word[8]; /* magic word */
|
||||
+ uint32_t buf_start; /* holds the 32-bit little-endian
|
||||
+ * offset of the start of the buffer
|
||||
+ */
|
||||
+ uint32_t buf_length; /* holds the 32-bit little-endian
|
||||
+ * length of the buffer
|
||||
+ */
|
||||
+ uint32_t last_byte; /* holds the 32-bit little-endian offset
|
||||
+ * of the byte after the last byte that
|
||||
+ * was written
|
||||
+ */
|
||||
+ char reserved[44];
|
||||
+};
|
||||
+
|
||||
+#define LOG_HEADER_FLAG_BUFFER_WRAPAROUND 0x80000000
|
||||
+#define LOG_VERSION_MAJOR 1
|
||||
+#define LOG_VERSION_MINOR 0
|
||||
+
|
||||
+
|
||||
+#define invalidate(p) { asm volatile("dc ivac, %0" : : "r" (p) : "memory"); }
|
||||
+
|
||||
+struct console_data {
|
||||
+ char *map_addr;
|
||||
+ struct log_header *hdr;
|
||||
+ char *start_addr; /* Start of buffer */
|
||||
+ char *end_addr; /* End of buffer */
|
||||
+ char *end_of_data; /* Current end of data */
|
||||
+ char *cur_ptr; /* Last data sent to console */
|
||||
+};
|
||||
+
|
||||
+#define LAST_BYTE(a) ((a) & ~(LOG_HEADER_FLAG_BUFFER_WRAPAROUND))
|
||||
+
|
||||
+static inline void __adjust_end(struct console_data *cd)
|
||||
+{
|
||||
+ cd->end_of_data = cd->start_addr
|
||||
+ + LAST_BYTE(le32_to_cpu(cd->hdr->last_byte));
|
||||
+}
|
||||
+
|
||||
+static inline void adjust_end(struct console_data *cd)
|
||||
+{
|
||||
+ invalidate(cd->hdr);
|
||||
+ __adjust_end(cd);
|
||||
+}
|
||||
+
|
||||
+static inline uint64_t get_mc_fw_base_address(void)
|
||||
+{
|
||||
+ u32 *mcfbaregs = (u32 *) ioremap(SOC_CCSR_MC_FW_BASE_ADDR_REGS,
|
||||
+ SOC_CCSR_MC_FW_BASE_ADDR_REGS_SIZE);
|
||||
+ u64 mcfwbase = 0ULL;
|
||||
+
|
||||
+ mcfwbase = readl(mcfbaregs + MCFBAHR_OFFSET) & MC_FW_HIGH_ADDR_MASK;
|
||||
+ mcfwbase <<= 32;
|
||||
+ mcfwbase |= readl(mcfbaregs + MCFBALR_OFFSET) & MC_FW_LOW_ADDR_MASK;
|
||||
+ iounmap(mcfbaregs);
|
||||
+ pr_info("fsl-ls2-console: MC base address at 0x%016llx\n", mcfwbase);
|
||||
+ return mcfwbase;
|
||||
+}
|
||||
+
|
||||
+static int fsl_ls2_generic_console_open(struct inode *node, struct file *fp,
|
||||
+ u64 offset, u64 size,
|
||||
+ uint8_t *emagic, uint8_t magic_len,
|
||||
+ u32 offset_delta)
|
||||
+{
|
||||
+ struct console_data *cd;
|
||||
+ uint8_t *magic;
|
||||
+ uint32_t wrapped;
|
||||
+
|
||||
+ cd = kmalloc(sizeof(*cd), GFP_KERNEL);
|
||||
+ if (cd == NULL)
|
||||
+ return -ENOMEM;
|
||||
+ fp->private_data = cd;
|
||||
+ cd->map_addr = ioremap(get_mc_fw_base_address() + offset, size);
|
||||
+
|
||||
+ cd->hdr = (struct log_header *) cd->map_addr;
|
||||
+ invalidate(cd->hdr);
|
||||
+
|
||||
+ magic = cd->hdr->magic_word;
|
||||
+ if (memcmp(magic, emagic, magic_len)) {
|
||||
+ pr_info("magic didn't match!\n");
|
||||
+ pr_info("expected: %02x %02x %02x %02x %02x %02x %02x %02x\n",
|
||||
+ emagic[0], emagic[1], emagic[2], emagic[3],
|
||||
+ emagic[4], emagic[5], emagic[6], emagic[7]);
|
||||
+ pr_info(" seen: %02x %02x %02x %02x %02x %02x %02x %02x\n",
|
||||
+ magic[0], magic[1], magic[2], magic[3],
|
||||
+ magic[4], magic[5], magic[6], magic[7]);
|
||||
+ kfree(cd);
|
||||
+ iounmap(cd->map_addr);
|
||||
+ return -EIO;
|
||||
+ }
|
||||
+
|
||||
+ cd->start_addr = cd->map_addr
|
||||
+ + le32_to_cpu(cd->hdr->buf_start) - offset_delta;
|
||||
+ cd->end_addr = cd->start_addr + le32_to_cpu(cd->hdr->buf_length);
|
||||
+
|
||||
+ wrapped = le32_to_cpu(cd->hdr->last_byte)
|
||||
+ & LOG_HEADER_FLAG_BUFFER_WRAPAROUND;
|
||||
+
|
||||
+ __adjust_end(cd);
|
||||
+ if (wrapped && (cd->end_of_data != cd->end_addr))
|
||||
+ cd->cur_ptr = cd->end_of_data+1;
|
||||
+ else
|
||||
+ cd->cur_ptr = cd->start_addr;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int fsl_ls2_mc_console_open(struct inode *node, struct file *fp)
|
||||
+{
|
||||
+ uint8_t magic_word[] = { 0, 1, 'C', 'M' };
|
||||
+
|
||||
+ return fsl_ls2_generic_console_open(node, fp,
|
||||
+ MC_BUFFER_OFFSET, MC_BUFFER_SIZE,
|
||||
+ magic_word, sizeof(magic_word),
|
||||
+ MC_OFFSET_DELTA);
|
||||
+}
|
||||
+
|
||||
+static int fsl_ls2_aiop_console_open(struct inode *node, struct file *fp)
|
||||
+{
|
||||
+ uint8_t magic_word[] = { 'P', 'O', 'I', 'A' };
|
||||
+
|
||||
+ return fsl_ls2_generic_console_open(node, fp,
|
||||
+ AIOP_BUFFER_OFFSET, AIOP_BUFFER_SIZE,
|
||||
+ magic_word, sizeof(magic_word),
|
||||
+ AIOP_OFFSET_DELTA);
|
||||
+}
|
||||
+
|
||||
+static int fsl_ls2_console_close(struct inode *node, struct file *fp)
|
||||
+{
|
||||
+ struct console_data *cd = fp->private_data;
|
||||
+
|
||||
+ iounmap(cd->map_addr);
|
||||
+ kfree(cd);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+ssize_t fsl_ls2_console_read(struct file *fp, char __user *buf, size_t count,
|
||||
+ loff_t *f_pos)
|
||||
+{
|
||||
+ struct console_data *cd = fp->private_data;
|
||||
+ size_t bytes = 0;
|
||||
+ char data;
|
||||
+
|
||||
+ /* Check if we need to adjust the end of data addr */
|
||||
+ adjust_end(cd);
|
||||
+
|
||||
+ while ((count != bytes) && (cd->end_of_data != cd->cur_ptr)) {
|
||||
+ if (((u64)cd->cur_ptr) % 64 == 0)
|
||||
+ invalidate(cd->cur_ptr);
|
||||
+
|
||||
+ data = *(cd->cur_ptr);
|
||||
+ if (copy_to_user(&buf[bytes], &data, 1))
|
||||
+ return -EFAULT;
|
||||
+ cd->cur_ptr++;
|
||||
+ if (cd->cur_ptr >= cd->end_addr)
|
||||
+ cd->cur_ptr = cd->start_addr;
|
||||
+ ++bytes;
|
||||
+ }
|
||||
+ return bytes;
|
||||
+}
|
||||
+
|
||||
+static const struct file_operations fsl_ls2_mc_console_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .open = fsl_ls2_mc_console_open,
|
||||
+ .release = fsl_ls2_console_close,
|
||||
+ .read = fsl_ls2_console_read,
|
||||
+};
|
||||
+
|
||||
+static struct miscdevice fsl_ls2_mc_console_dev = {
|
||||
+ .minor = MISC_DYNAMIC_MINOR,
|
||||
+ .name = "fsl_mc_console",
|
||||
+ .fops = &fsl_ls2_mc_console_fops
|
||||
+};
|
||||
+
|
||||
+static const struct file_operations fsl_ls2_aiop_console_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .open = fsl_ls2_aiop_console_open,
|
||||
+ .release = fsl_ls2_console_close,
|
||||
+ .read = fsl_ls2_console_read,
|
||||
+};
|
||||
+
|
||||
+static struct miscdevice fsl_ls2_aiop_console_dev = {
|
||||
+ .minor = MISC_DYNAMIC_MINOR,
|
||||
+ .name = "fsl_aiop_console",
|
||||
+ .fops = &fsl_ls2_aiop_console_fops
|
||||
+};
|
||||
+
|
||||
+static int __init fsl_ls2_console_init(void)
|
||||
+{
|
||||
+ int err = 0;
|
||||
+
|
||||
+ pr_info("Freescale LS2 console driver\n");
|
||||
+ err = misc_register(&fsl_ls2_mc_console_dev);
|
||||
+ if (err) {
|
||||
+ pr_err("fsl_mc_console: cannot register device\n");
|
||||
+ return err;
|
||||
+ }
|
||||
+ pr_info("fsl-ls2-console: device %s registered\n",
|
||||
+ fsl_ls2_mc_console_dev.name);
|
||||
+
|
||||
+ err = misc_register(&fsl_ls2_aiop_console_dev);
|
||||
+ if (err) {
|
||||
+ pr_err("fsl_aiop_console: cannot register device\n");
|
||||
+ return err;
|
||||
+ }
|
||||
+ pr_info("fsl-ls2-console: device %s registered\n",
|
||||
+ fsl_ls2_aiop_console_dev.name);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void __exit fsl_ls2_console_exit(void)
|
||||
+{
|
||||
+ misc_deregister(&fsl_ls2_mc_console_dev);
|
||||
+
|
||||
+ misc_deregister(&fsl_ls2_aiop_console_dev);
|
||||
+}
|
||||
+
|
||||
+module_init(fsl_ls2_console_init);
|
||||
+module_exit(fsl_ls2_console_exit);
|
||||
+
|
||||
+MODULE_AUTHOR("Roy Pledge <roy.pledge@freescale.com>");
|
||||
+MODULE_LICENSE("Dual BSD/GPL");
|
||||
+MODULE_DESCRIPTION("Freescale LS2 console driver");
|
||||
@ -0,0 +1,33 @@
|
||||
From 56d12979923250799d651b75029ff281928635a4 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:53 +0800
|
||||
Subject: [PATCH 32/40] msi: support layerscape
|
||||
This is an integrated patch of msi for layerscape
|
||||
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 1 +
|
||||
drivers/irqchip/irq-ls-scfg-msi.c | 1 +
|
||||
2 files changed, 2 insertions(+)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
|
||||
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
|
||||
@@ -8,6 +8,7 @@ Required properties:
|
||||
"fsl,ls1043a-msi"
|
||||
"fsl,ls1046a-msi"
|
||||
"fsl,ls1043a-v1.1-msi"
|
||||
+ "fsl,ls1012a-msi"
|
||||
- msi-controller: indicates that this is a PCIe MSI controller node
|
||||
- reg: physical base address of the controller and length of memory mapped.
|
||||
- interrupts: an interrupt to the parent interrupt controller.
|
||||
--- a/drivers/irqchip/irq-ls-scfg-msi.c
|
||||
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
|
||||
@@ -319,6 +319,7 @@ static const struct of_device_id ls_scfg
|
||||
{ .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
|
||||
{ .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
|
||||
|
||||
+ { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
|
||||
{ .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
|
||||
{ .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
|
||||
{ .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
|
||||
@ -0,0 +1,596 @@
|
||||
From c503e92983f2e18c1e18e21b15d5bedd6d0be8ac Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:26:56 +0800
|
||||
Subject: [PATCH 33/40] pcie: support layerscape
|
||||
This is an integrated patch of pcie for layerscape
|
||||
|
||||
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
|
||||
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
|
||||
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
||||
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
|
||||
Signed-off-by: Po Liu <po.liu@nxp.com>
|
||||
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
.../bindings/pci/layerscape-pci.txt | 14 +-
|
||||
arch/arm/kernel/bios32.c | 43 ++++++
|
||||
arch/arm64/kernel/pci.c | 43 ++++++
|
||||
drivers/misc/pci_endpoint_test.c | 20 +--
|
||||
drivers/pci/dwc/Kconfig | 8 ++
|
||||
drivers/pci/dwc/pci-layerscape.c | 132 +++++++++++++++++-
|
||||
drivers/pci/endpoint/functions/pci-epf-test.c | 2 +-
|
||||
drivers/pci/endpoint/pci-epf-core.c | 8 +-
|
||||
drivers/pci/pcie/portdrv_core.c | 29 ++++
|
||||
drivers/pci/quirks.c | 15 ++
|
||||
include/linux/pci.h | 1 +
|
||||
11 files changed, 292 insertions(+), 23 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
|
||||
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
|
||||
@@ -18,11 +18,16 @@ Required properties:
|
||||
"fsl,ls2088a-pcie"
|
||||
"fsl,ls1088a-pcie"
|
||||
"fsl,ls1046a-pcie"
|
||||
+ "fsl,ls1012a-pcie"
|
||||
- reg: base addresses and lengths of the PCIe controller register blocks.
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
-- interrupt-names: Must include the following entries:
|
||||
- "intr": The interrupt that is asserted for controller interrupts
|
||||
+- interrupt-names: It could include the following entries:
|
||||
+ "aer": Asserted for aer interrupt when chip support the aer interrupt with
|
||||
+ none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
|
||||
+ "pme": Asserted for pme interrupt when chip support the pme interrupt with
|
||||
+ none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
|
||||
+ ......
|
||||
- fsl,pcie-scfg: Must include two entries.
|
||||
The first entry must be a link to the SCFG device node
|
||||
The second entry must be '0' or '1' based on physical PCIe controller index.
|
||||
@@ -38,8 +43,9 @@ Example:
|
||||
reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
||||
- interrupt-names = "intr";
|
||||
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */
|
||||
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */
|
||||
+ interrupt-names = "aer", "pme";
|
||||
fsl,pcie-scfg = <&scfg 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
--- a/arch/arm/kernel/bios32.c
|
||||
+++ b/arch/arm/kernel/bios32.c
|
||||
@@ -12,6 +12,8 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/pcieport_if.h>
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/map.h>
|
||||
@@ -65,6 +67,47 @@ void pcibios_report_status(u_int status_
|
||||
}
|
||||
|
||||
/*
|
||||
+ * Check device tree if the service interrupts are there
|
||||
+ */
|
||||
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
|
||||
+{
|
||||
+ int ret, count = 0;
|
||||
+ struct device_node *np = NULL;
|
||||
+
|
||||
+ if (dev->bus->dev.of_node)
|
||||
+ np = dev->bus->dev.of_node;
|
||||
+
|
||||
+ if (np == NULL)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!IS_ENABLED(CONFIG_OF_IRQ))
|
||||
+ return 0;
|
||||
+
|
||||
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
|
||||
+ * request irq for aer
|
||||
+ */
|
||||
+ if (mask & PCIE_PORT_SERVICE_AER) {
|
||||
+ ret = of_irq_get_byname(np, "aer");
|
||||
+ if (ret > 0) {
|
||||
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
|
||||
+ count++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (mask & PCIE_PORT_SERVICE_PME) {
|
||||
+ ret = of_irq_get_byname(np, "pme");
|
||||
+ if (ret > 0) {
|
||||
+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
|
||||
+ count++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* TODO: add more service interrupts if there it is in the device tree*/
|
||||
+
|
||||
+ return count;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
* We don't use this to fix the device, but initialisation of it.
|
||||
* It's not the correct use for this, but it works.
|
||||
* Note that the arbiter/ISA bridge appears to be buggy, specifically in
|
||||
--- a/arch/arm64/kernel/pci.c
|
||||
+++ b/arch/arm64/kernel/pci.c
|
||||
@@ -17,6 +17,8 @@
|
||||
#include <linux/mm.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
+#include <linux/of_irq.h>
|
||||
+#include <linux/pcieport_if.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/pci-acpi.h>
|
||||
#include <linux/pci-ecam.h>
|
||||
@@ -36,6 +38,47 @@ int pcibios_alloc_irq(struct pci_dev *de
|
||||
#endif
|
||||
|
||||
/*
|
||||
+ * Check device tree if the service interrupts are there
|
||||
+ */
|
||||
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
|
||||
+{
|
||||
+ int ret, count = 0;
|
||||
+ struct device_node *np = NULL;
|
||||
+
|
||||
+ if (dev->bus->dev.of_node)
|
||||
+ np = dev->bus->dev.of_node;
|
||||
+
|
||||
+ if (np == NULL)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (!IS_ENABLED(CONFIG_OF_IRQ))
|
||||
+ return 0;
|
||||
+
|
||||
+ /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
|
||||
+ * request irq for aer
|
||||
+ */
|
||||
+ if (mask & PCIE_PORT_SERVICE_AER) {
|
||||
+ ret = of_irq_get_byname(np, "aer");
|
||||
+ if (ret > 0) {
|
||||
+ irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
|
||||
+ count++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (mask & PCIE_PORT_SERVICE_PME) {
|
||||
+ ret = of_irq_get_byname(np, "pme");
|
||||
+ if (ret > 0) {
|
||||
+ irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
|
||||
+ count++;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* TODO: add more service interrupts if there it is in the device tree*/
|
||||
+
|
||||
+ return count;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
* raw_pci_read/write - Platform-specific PCI config space access.
|
||||
*/
|
||||
int raw_pci_read(unsigned int domain, unsigned int bus,
|
||||
--- a/drivers/misc/pci_endpoint_test.c
|
||||
+++ b/drivers/misc/pci_endpoint_test.c
|
||||
@@ -97,6 +97,8 @@ struct pci_endpoint_test {
|
||||
struct miscdevice miscdev;
|
||||
enum pci_barno test_reg_bar;
|
||||
size_t alignment;
|
||||
+ char name[20];
|
||||
+ int irq_num;
|
||||
};
|
||||
|
||||
struct pci_endpoint_test_data {
|
||||
@@ -454,9 +456,7 @@ static int pci_endpoint_test_probe(struc
|
||||
{
|
||||
int i;
|
||||
int err;
|
||||
- int irq = 0;
|
||||
int id;
|
||||
- char name[20];
|
||||
enum pci_barno bar;
|
||||
void __iomem *base;
|
||||
struct device *dev = &pdev->dev;
|
||||
@@ -501,19 +501,19 @@ static int pci_endpoint_test_probe(struc
|
||||
pci_set_master(pdev);
|
||||
|
||||
if (!no_msi) {
|
||||
- irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
|
||||
- if (irq < 0)
|
||||
+ test->irq_num = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
|
||||
+ if (test->irq_num < 0)
|
||||
dev_err(dev, "failed to get MSI interrupts\n");
|
||||
}
|
||||
|
||||
- err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
|
||||
+ err = request_irq(pdev->irq, pci_endpoint_test_irqhandler,
|
||||
IRQF_SHARED, DRV_MODULE_NAME, test);
|
||||
if (err) {
|
||||
dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
|
||||
goto err_disable_msi;
|
||||
}
|
||||
|
||||
- for (i = 1; i < irq; i++) {
|
||||
+ for (i = 1; i < test->irq_num; i++) {
|
||||
err = devm_request_irq(dev, pdev->irq + i,
|
||||
pci_endpoint_test_irqhandler,
|
||||
IRQF_SHARED, DRV_MODULE_NAME, test);
|
||||
@@ -548,10 +548,10 @@ static int pci_endpoint_test_probe(struc
|
||||
goto err_iounmap;
|
||||
}
|
||||
|
||||
- snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
|
||||
+ snprintf(test->name, sizeof(test->name), DRV_MODULE_NAME ".%d", id);
|
||||
misc_device = &test->miscdev;
|
||||
misc_device->minor = MISC_DYNAMIC_MINOR;
|
||||
- misc_device->name = name;
|
||||
+ misc_device->name = test->name;
|
||||
misc_device->fops = &pci_endpoint_test_fops,
|
||||
|
||||
err = misc_register(misc_device);
|
||||
@@ -584,6 +584,7 @@ err_disable_pdev:
|
||||
static void pci_endpoint_test_remove(struct pci_dev *pdev)
|
||||
{
|
||||
int id;
|
||||
+ int i;
|
||||
enum pci_barno bar;
|
||||
struct pci_endpoint_test *test = pci_get_drvdata(pdev);
|
||||
struct miscdevice *misc_device = &test->miscdev;
|
||||
@@ -599,6 +600,8 @@ static void pci_endpoint_test_remove(str
|
||||
if (test->bar[bar])
|
||||
pci_iounmap(pdev, test->bar[bar]);
|
||||
}
|
||||
+ for (i = 0; i < test->irq_num; i++)
|
||||
+ free_irq(pdev->irq + i, test);
|
||||
pci_disable_msi(pdev);
|
||||
pci_release_regions(pdev);
|
||||
pci_disable_device(pdev);
|
||||
@@ -607,6 +610,7 @@ static void pci_endpoint_test_remove(str
|
||||
static const struct pci_device_id pci_endpoint_test_tbl[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
|
||||
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID) },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
|
||||
--- a/drivers/pci/dwc/Kconfig
|
||||
+++ b/drivers/pci/dwc/Kconfig
|
||||
@@ -111,6 +111,14 @@ config PCI_LAYERSCAPE
|
||||
help
|
||||
Say Y here if you want PCIe controller support on Layerscape SoCs.
|
||||
|
||||
+config PCI_LAYERSCAPE_EP
|
||||
+ bool "PCI layerscape Endpoint Mode"
|
||||
+ depends on PCI_ENDPOINT
|
||||
+ select PCIE_DW_EP
|
||||
+ help
|
||||
+ Enables support for the PCIe controller in the layerscape SoC to work in
|
||||
+ endpoint mode.
|
||||
+
|
||||
config PCI_HISI
|
||||
depends on OF && ARM64
|
||||
bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
|
||||
--- a/drivers/pci/dwc/pci-layerscape.c
|
||||
+++ b/drivers/pci/dwc/pci-layerscape.c
|
||||
@@ -33,8 +33,15 @@
|
||||
|
||||
/* PEX Internal Configuration Registers */
|
||||
#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
|
||||
+#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
|
||||
+#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
|
||||
|
||||
+#define PCIE_DBI2_BASE 0x1000 /* DBI2 base address*/
|
||||
+#define PCIE_MSI_MSG_DATA_OFF 0x5c /* MSI Data register address*/
|
||||
+#define PCIE_MSI_OB_SIZE 4096
|
||||
+#define PCIE_MSI_ADDR_OFFSET (1024 * 1024)
|
||||
#define PCIE_IATU_NUM 6
|
||||
+#define PCIE_EP_ADDR_SPACE_SIZE 0x100000000
|
||||
|
||||
struct ls_pcie_drvdata {
|
||||
u32 lut_offset;
|
||||
@@ -44,12 +51,20 @@ struct ls_pcie_drvdata {
|
||||
const struct dw_pcie_ops *dw_pcie_ops;
|
||||
};
|
||||
|
||||
+struct ls_pcie_ep {
|
||||
+ dma_addr_t msi_phys_addr;
|
||||
+ void __iomem *msi_virt_addr;
|
||||
+ u64 msi_msg_addr;
|
||||
+ u16 msi_msg_data;
|
||||
+};
|
||||
+
|
||||
struct ls_pcie {
|
||||
struct dw_pcie *pci;
|
||||
void __iomem *lut;
|
||||
struct regmap *scfg;
|
||||
const struct ls_pcie_drvdata *drvdata;
|
||||
int index;
|
||||
+ struct ls_pcie_ep *pcie_ep;
|
||||
};
|
||||
|
||||
#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
|
||||
@@ -124,6 +139,14 @@ static int ls_pcie_link_up(struct dw_pci
|
||||
return 1;
|
||||
}
|
||||
|
||||
+/* Forward error response of outbound non-posted requests */
|
||||
+static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
|
||||
+{
|
||||
+ struct dw_pcie *pci = pcie->pci;
|
||||
+
|
||||
+ iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
|
||||
+}
|
||||
+
|
||||
static int ls_pcie_host_init(struct pcie_port *pp)
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
@@ -135,6 +158,7 @@ static int ls_pcie_host_init(struct pcie
|
||||
* dw_pcie_setup_rc() will reconfigure the outbound windows.
|
||||
*/
|
||||
ls_pcie_disable_outbound_atus(pcie);
|
||||
+ ls_pcie_fix_error_response(pcie);
|
||||
|
||||
dw_pcie_dbi_ro_wr_en(pci);
|
||||
ls_pcie_clear_multifunction(pcie);
|
||||
@@ -253,6 +277,7 @@ static struct ls_pcie_drvdata ls2088_drv
|
||||
};
|
||||
|
||||
static const struct of_device_id ls_pcie_of_match[] = {
|
||||
+ { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
|
||||
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
|
||||
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
|
||||
{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
|
||||
@@ -263,6 +288,99 @@ static const struct of_device_id ls_pcie
|
||||
{ },
|
||||
};
|
||||
|
||||
+static void ls_pcie_raise_msi_irq(struct ls_pcie_ep *pcie_ep)
|
||||
+{
|
||||
+ iowrite32(pcie_ep->msi_msg_data, pcie_ep->msi_virt_addr);
|
||||
+}
|
||||
+
|
||||
+static int ls_pcie_raise_irq(struct dw_pcie_ep *ep,
|
||||
+ enum pci_epc_irq_type type, u8 interrupt_num)
|
||||
+{
|
||||
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||||
+ struct ls_pcie *pcie = to_ls_pcie(pci);
|
||||
+ struct ls_pcie_ep *pcie_ep = pcie->pcie_ep;
|
||||
+ u32 free_win;
|
||||
+
|
||||
+ /* get the msi message address and msi message data */
|
||||
+ pcie_ep->msi_msg_addr = ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_L32) |
|
||||
+ (((u64)ioread32(pci->dbi_base + MSI_MESSAGE_ADDR_U32)) << 32);
|
||||
+ pcie_ep->msi_msg_data = ioread16(pci->dbi_base + PCIE_MSI_MSG_DATA_OFF);
|
||||
+
|
||||
+ /* request and config the outband window for msi */
|
||||
+ free_win = find_first_zero_bit(&ep->ob_window_map,
|
||||
+ sizeof(ep->ob_window_map));
|
||||
+ if (free_win >= ep->num_ob_windows) {
|
||||
+ dev_err(pci->dev, "no free outbound window\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
|
||||
+ pcie_ep->msi_phys_addr,
|
||||
+ pcie_ep->msi_msg_addr,
|
||||
+ PCIE_MSI_OB_SIZE);
|
||||
+
|
||||
+ set_bit(free_win, &ep->ob_window_map);
|
||||
+
|
||||
+ /* generate the msi interrupt */
|
||||
+ ls_pcie_raise_msi_irq(pcie_ep);
|
||||
+
|
||||
+ /* release the outband window of msi */
|
||||
+ dw_pcie_disable_atu(pci, free_win, DW_PCIE_REGION_OUTBOUND);
|
||||
+ clear_bit(free_win, &ep->ob_window_map);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static struct dw_pcie_ep_ops pcie_ep_ops = {
|
||||
+ .raise_irq = ls_pcie_raise_irq,
|
||||
+};
|
||||
+
|
||||
+static int __init ls_add_pcie_ep(struct ls_pcie *pcie,
|
||||
+ struct platform_device *pdev)
|
||||
+{
|
||||
+ struct dw_pcie *pci = pcie->pci;
|
||||
+ struct device *dev = pci->dev;
|
||||
+ struct dw_pcie_ep *ep;
|
||||
+ struct ls_pcie_ep *pcie_ep;
|
||||
+ struct resource *cfg_res;
|
||||
+ int ret;
|
||||
+
|
||||
+ ep = &pci->ep;
|
||||
+ ep->ops = &pcie_ep_ops;
|
||||
+
|
||||
+ pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
|
||||
+ if (!pcie_ep)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ pcie->pcie_ep = pcie_ep;
|
||||
+
|
||||
+ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
|
||||
+ if (cfg_res) {
|
||||
+ ep->phys_base = cfg_res->start;
|
||||
+ ep->addr_size = PCIE_EP_ADDR_SPACE_SIZE;
|
||||
+ } else {
|
||||
+ dev_err(dev, "missing *config* space\n");
|
||||
+ return -ENODEV;
|
||||
+ }
|
||||
+
|
||||
+ pcie_ep->msi_phys_addr = ep->phys_base + PCIE_MSI_ADDR_OFFSET;
|
||||
+
|
||||
+ pcie_ep->msi_virt_addr = ioremap(pcie_ep->msi_phys_addr,
|
||||
+ PCIE_MSI_OB_SIZE);
|
||||
+ if (!pcie_ep->msi_virt_addr) {
|
||||
+ dev_err(dev, "failed to map MSI outbound region\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ ret = dw_pcie_ep_init(ep);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to initialize endpoint\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int __init ls_add_pcie_port(struct ls_pcie *pcie)
|
||||
{
|
||||
struct dw_pcie *pci = pcie->pci;
|
||||
@@ -309,18 +427,18 @@ static int __init ls_pcie_probe(struct p
|
||||
if (IS_ERR(pci->dbi_base))
|
||||
return PTR_ERR(pci->dbi_base);
|
||||
|
||||
- pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
|
||||
+ pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_BASE;
|
||||
|
||||
- if (!ls_pcie_is_bridge(pcie))
|
||||
- return -ENODEV;
|
||||
+ pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
|
||||
|
||||
platform_set_drvdata(pdev, pcie);
|
||||
|
||||
- ret = ls_add_pcie_port(pcie);
|
||||
- if (ret < 0)
|
||||
- return ret;
|
||||
+ if (!ls_pcie_is_bridge(pcie))
|
||||
+ ret = ls_add_pcie_ep(pcie, pdev);
|
||||
+ else
|
||||
+ ret = ls_add_pcie_port(pcie);
|
||||
|
||||
- return 0;
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver ls_pcie_driver = {
|
||||
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
|
||||
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
|
||||
@@ -471,7 +471,7 @@ static int pci_epf_test_probe(struct pci
|
||||
const struct pci_epf_device_id *match;
|
||||
struct pci_epf_test_data *data;
|
||||
enum pci_barno test_reg_bar = BAR_0;
|
||||
- bool linkup_notifier = true;
|
||||
+ bool linkup_notifier = false;
|
||||
|
||||
match = pci_epf_match_device(pci_epf_test_ids, epf);
|
||||
data = (struct pci_epf_test_data *)match->driver_data;
|
||||
--- a/drivers/pci/endpoint/pci-epf-core.c
|
||||
+++ b/drivers/pci/endpoint/pci-epf-core.c
|
||||
@@ -104,8 +104,8 @@ void pci_epf_free_space(struct pci_epf *
|
||||
if (!addr)
|
||||
return;
|
||||
|
||||
- dma_free_coherent(dev, epf->bar[bar].size, addr,
|
||||
- epf->bar[bar].phys_addr);
|
||||
+ free_pages((unsigned long)addr,
|
||||
+ get_order(epf->bar[bar].size));
|
||||
|
||||
epf->bar[bar].phys_addr = 0;
|
||||
epf->bar[bar].size = 0;
|
||||
@@ -129,7 +129,9 @@ void *pci_epf_alloc_space(struct pci_epf
|
||||
size = 128;
|
||||
size = roundup_pow_of_two(size);
|
||||
|
||||
- space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
|
||||
+ space = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
|
||||
+ get_order(size));
|
||||
+ phys_addr = virt_to_phys(space);
|
||||
if (!space) {
|
||||
dev_err(dev, "failed to allocate mem space\n");
|
||||
return NULL;
|
||||
--- a/drivers/pci/pcie/portdrv_core.c
|
||||
+++ b/drivers/pci/pcie/portdrv_core.c
|
||||
@@ -45,6 +45,20 @@ static void release_pcie_device(struct d
|
||||
}
|
||||
|
||||
/**
|
||||
+ * pcibios_check_service_irqs - check irqs in the device tree
|
||||
+ * @dev: PCI Express port to handle
|
||||
+ * @irqs: Array of irqs to populate
|
||||
+ * @mask: Bitmask of port capabilities returned by get_port_device_capability()
|
||||
+ *
|
||||
+ * Return value: 0 means no service irqs in the device tree
|
||||
+ *
|
||||
+ */
|
||||
+int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+/**
|
||||
* pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
|
||||
* for given port
|
||||
* @dev: PCI Express port to handle
|
||||
@@ -185,10 +199,25 @@ out_free_irqs:
|
||||
static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
|
||||
{
|
||||
int ret, i;
|
||||
+ int irq = -1;
|
||||
|
||||
for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
|
||||
irqs[i] = -1;
|
||||
|
||||
+ /* Check if some platforms owns independent irq pins for AER/PME etc.
|
||||
+ * Some platforms may own independent AER/PME interrupts and set
|
||||
+ * them in the device tree file.
|
||||
+ */
|
||||
+ ret = pcibios_check_service_irqs(dev, irqs, mask);
|
||||
+ if (ret) {
|
||||
+ if (dev->irq)
|
||||
+ irq = dev->irq;
|
||||
+ for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
|
||||
+ if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
|
||||
+ irqs[i] = irq;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
/*
|
||||
* If we support PME or hotplug, but we can't use MSI/MSI-X for
|
||||
* them, we have to fall back to INTx or other interrupts, e.g., a
|
||||
--- a/drivers/pci/quirks.c
|
||||
+++ b/drivers/pci/quirks.c
|
||||
@@ -3376,6 +3376,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
|
||||
|
||||
+/*
|
||||
+ * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
|
||||
+ * bus reset. Link state of device does not comes UP and so config space
|
||||
+ * never accessible again.
|
||||
+ */
|
||||
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
|
||||
+
|
||||
static void quirk_no_pm_reset(struct pci_dev *dev)
|
||||
{
|
||||
/*
|
||||
@@ -4857,3 +4864,11 @@ static void quirk_no_ats(struct pci_dev
|
||||
/* AMD Stoney platform GPU */
|
||||
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
|
||||
#endif /* CONFIG_PCI_ATS */
|
||||
+
|
||||
+/* Freescale PCIe doesn't support MSI in RC mode */
|
||||
+static void quirk_fsl_no_msi(struct pci_dev *pdev)
|
||||
+{
|
||||
+ if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
|
||||
+ pdev->no_msi = 1;
|
||||
+}
|
||||
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
|
||||
--- a/include/linux/pci.h
|
||||
+++ b/include/linux/pci.h
|
||||
@@ -1944,6 +1944,7 @@ void pcibios_release_device(struct pci_d
|
||||
void pcibios_penalize_isa_irq(int irq, int active);
|
||||
int pcibios_alloc_irq(struct pci_dev *dev);
|
||||
void pcibios_free_irq(struct pci_dev *dev);
|
||||
+int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
|
||||
|
||||
#ifdef CONFIG_HIBERNATE_CALLBACKS
|
||||
extern struct dev_pm_ops pcibios_pm_ops;
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,774 @@
|
||||
From 60eee49f37b77bc2d5f46c5db5a5c24d0c31bd02 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 20 Nov 2018 15:36:57 +0800
|
||||
Subject: [PATCH] qspi: support layerscape
|
||||
|
||||
This is an integrated patch of qspi for layerscape
|
||||
|
||||
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
||||
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
|
||||
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
||||
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
||||
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
|
||||
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
.../devicetree/bindings/mtd/fsl-quadspi.txt | 31 ++
|
||||
drivers/mtd/spi-nor/fsl-quadspi.c | 444 +++++++++++-------
|
||||
drivers/mtd/spi-nor/spi-nor.c | 5 +
|
||||
3 files changed, 320 insertions(+), 160 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
|
||||
+++ b/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
|
||||
@@ -7,6 +7,7 @@ Required properties:
|
||||
or
|
||||
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",
|
||||
"fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"
|
||||
+ "fsl,ls2080a-qspi" followed by "fsl,ls1088a-qspi",
|
||||
- reg : the first contains the register location and length,
|
||||
the second contains the memory mapping address and length
|
||||
- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
|
||||
@@ -39,3 +40,33 @@ qspi0: quadspi@40044000 {
|
||||
....
|
||||
};
|
||||
};
|
||||
+
|
||||
+qspi1: quadspi@20c0000 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x0 0x20c0000 0x0 0x10000>,
|
||||
+ <0x0 0x20000000 0x0 0x10000000>;
|
||||
+ reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
+ interrupts = <0 25 0x4>; /* Level high type */
|
||||
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
||||
+ clock-names = "qspi_en", "qspi";
|
||||
+ status = "okay";
|
||||
+
|
||||
+ qflash0: s25fs512s@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ reg = <0>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <4>;
|
||||
+ };
|
||||
+
|
||||
+ qflash1: s25fs512s@1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ spi-max-frequency = <20000000>;
|
||||
+ reg = <1>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ spi-tx-bus-width = <4>;
|
||||
+ };
|
||||
+};
|
||||
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
|
||||
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
|
||||
@@ -41,6 +41,7 @@
|
||||
#define QUADSPI_QUIRK_TKT253890 (1 << 2)
|
||||
/* Controller cannot wake up from wait mode, TKT245618 */
|
||||
#define QUADSPI_QUIRK_TKT245618 (1 << 3)
|
||||
+#define QUADSPI_ADDR_REMAP (1 << 4)
|
||||
|
||||
/* The registers */
|
||||
#define QUADSPI_MCR 0x00
|
||||
@@ -183,7 +184,7 @@
|
||||
|
||||
/* Macros for constructing the LUT register. */
|
||||
#define LUT0(ins, pad, opr) \
|
||||
- (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
|
||||
+ (((opr) << OPRND0_SHIFT) | ((pad) << PAD0_SHIFT) | \
|
||||
((LUT_##ins) << INSTR0_SHIFT))
|
||||
|
||||
#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
|
||||
@@ -193,27 +194,29 @@
|
||||
#define QUADSPI_LUT_NUM 64
|
||||
|
||||
/* SEQID -- we can have 16 seqids at most. */
|
||||
-#define SEQID_READ 0
|
||||
-#define SEQID_WREN 1
|
||||
-#define SEQID_WRDI 2
|
||||
-#define SEQID_RDSR 3
|
||||
-#define SEQID_SE 4
|
||||
-#define SEQID_CHIP_ERASE 5
|
||||
-#define SEQID_PP 6
|
||||
-#define SEQID_RDID 7
|
||||
-#define SEQID_WRSR 8
|
||||
-#define SEQID_RDCR 9
|
||||
-#define SEQID_EN4B 10
|
||||
-#define SEQID_BRWR 11
|
||||
+/* LUT0 programmed by bootloader, for run-time create entry for LUT seqid 1 */
|
||||
+#define SEQID_LUT0_BOOTLOADER 0
|
||||
+#define SEQID_LUT1_RUNTIME 1
|
||||
+#define SEQID_LUT2_AHBREAD 2
|
||||
|
||||
#define QUADSPI_MIN_IOMAP SZ_4M
|
||||
|
||||
+enum fsl_qspi_ops {
|
||||
+ FSL_QSPI_OPS_READ = 0,
|
||||
+ FSL_QSPI_OPS_WRITE,
|
||||
+ FSL_QSPI_OPS_ERASE,
|
||||
+ FSL_QSPI_OPS_READ_REG,
|
||||
+ FSL_QSPI_OPS_WRITE_REG,
|
||||
+ FSL_QSPI_OPS_WRITE_BUF_REG,
|
||||
+};
|
||||
+
|
||||
enum fsl_qspi_devtype {
|
||||
FSL_QUADSPI_VYBRID,
|
||||
FSL_QUADSPI_IMX6SX,
|
||||
FSL_QUADSPI_IMX7D,
|
||||
FSL_QUADSPI_IMX6UL,
|
||||
FSL_QUADSPI_LS1021A,
|
||||
+ FSL_QUADSPI_LS2080A,
|
||||
};
|
||||
|
||||
struct fsl_qspi_devtype_data {
|
||||
@@ -267,6 +270,15 @@ static struct fsl_qspi_devtype_data ls10
|
||||
.driver_data = 0,
|
||||
};
|
||||
|
||||
+static const struct fsl_qspi_devtype_data ls2080a_data = {
|
||||
+ .devtype = FSL_QUADSPI_LS2080A,
|
||||
+ .rxfifo = 128,
|
||||
+ .txfifo = 64,
|
||||
+ .ahb_buf_size = 1024,
|
||||
+ .driver_data = QUADSPI_QUIRK_TKT253890 | QUADSPI_ADDR_REMAP,
|
||||
+};
|
||||
+
|
||||
+
|
||||
#define FSL_QSPI_MAX_CHIP 4
|
||||
struct fsl_qspi {
|
||||
struct spi_nor nor[FSL_QSPI_MAX_CHIP];
|
||||
@@ -310,6 +322,22 @@ static inline int needs_wakeup_wait_mode
|
||||
}
|
||||
|
||||
/*
|
||||
+ * QSPI memory regions split into two parts: a 256MB region that is located
|
||||
+ * in the least significant 4GB of the SoC address space and a 3.75GB region
|
||||
+ * that is located above the least significant 4GB of the SoC address space.
|
||||
+ *
|
||||
+ * The 4GB QSPI address space map is shown below.
|
||||
+ *
|
||||
+ * SoC Address QSPI Address
|
||||
+ * 0x00_2000_0000-0x00_2FFF_FFFF 0x00_0000_0000-0x00_0FFF_FFFF First 256MB
|
||||
+ * 0x04_1000_0000-0x04_FFFF_FFFF 0x00_1000_0000-0x00_FFFF_FFFF Last 3.75GB
|
||||
+ */
|
||||
+static inline int need_address_remap(struct fsl_qspi *q)
|
||||
+{
|
||||
+ return q->devtype_data->driver_data & QUADSPI_ADDR_REMAP;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
* R/W functions for big- or little-endian registers:
|
||||
* The qSPI controller's endian is independent of the CPU core's endian.
|
||||
* So far, although the CPU core is little-endian but the qSPI have two
|
||||
@@ -368,137 +396,160 @@ static irqreturn_t fsl_qspi_irq_handler(
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
-static void fsl_qspi_init_lut(struct fsl_qspi *q)
|
||||
+static inline s8 pad_count(s8 pad_val)
|
||||
{
|
||||
+ s8 count = -1;
|
||||
+
|
||||
+ if (!pad_val)
|
||||
+ return 0;
|
||||
+
|
||||
+ while (pad_val) {
|
||||
+ pad_val >>= 1;
|
||||
+ count++;
|
||||
+ }
|
||||
+ return count;
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Prepare LUT entry for the input cmd.
|
||||
+ * Protocol info is present in instance of struct spi_nor, using which fields
|
||||
+ * like cmd, data, addrlen along with pad info etc can be parsed.
|
||||
+ */
|
||||
+static void fsl_qspi_prepare_lut(struct spi_nor *nor,
|
||||
+ enum fsl_qspi_ops ops, u8 cmd)
|
||||
+{
|
||||
+ struct fsl_qspi *q = nor->priv;
|
||||
void __iomem *base = q->iobase;
|
||||
int rxfifo = q->devtype_data->rxfifo;
|
||||
+ int txfifo = q->devtype_data->txfifo;
|
||||
u32 lut_base;
|
||||
- int i;
|
||||
+ u8 cmd_pad, addr_pad, data_pad, dummy_pad;
|
||||
+ enum spi_nor_protocol protocol = 0;
|
||||
+ u8 addrlen = 0;
|
||||
+ u8 read_dm, opcode;
|
||||
+ int stop_lut;
|
||||
+
|
||||
+ read_dm = opcode = cmd_pad = addr_pad = data_pad = dummy_pad = 0;
|
||||
+
|
||||
+ switch (ops) {
|
||||
+ case FSL_QSPI_OPS_READ_REG:
|
||||
+ case FSL_QSPI_OPS_WRITE_REG:
|
||||
+ case FSL_QSPI_OPS_WRITE_BUF_REG:
|
||||
+ opcode = cmd;
|
||||
+ protocol = nor->reg_proto;
|
||||
+ break;
|
||||
+ case FSL_QSPI_OPS_READ:
|
||||
+ opcode = cmd;
|
||||
+ read_dm = nor->read_dummy;
|
||||
+ protocol = nor->read_proto;
|
||||
+ break;
|
||||
+ case FSL_QSPI_OPS_WRITE:
|
||||
+ opcode = cmd;
|
||||
+ protocol = nor->write_proto;
|
||||
+ break;
|
||||
+ case FSL_QSPI_OPS_ERASE:
|
||||
+ opcode = cmd;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(q->dev, "Unsupported operation 0x%.2x\n", ops);
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (protocol) {
|
||||
+ cmd_pad = spi_nor_get_protocol_inst_nbits(protocol);
|
||||
+ addr_pad = spi_nor_get_protocol_addr_nbits(protocol);
|
||||
+ data_pad = spi_nor_get_protocol_data_nbits(protocol);
|
||||
+ }
|
||||
+
|
||||
+ dummy_pad = data_pad;
|
||||
|
||||
- struct spi_nor *nor = &q->nor[0];
|
||||
- u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
|
||||
- u8 read_op = nor->read_opcode;
|
||||
- u8 read_dm = nor->read_dummy;
|
||||
+ dev_dbg(q->dev, "ops:%x opcode:%x pad[cmd:%d, addr:%d, data:%d]\n",
|
||||
+ ops, opcode, cmd_pad, addr_pad, data_pad);
|
||||
|
||||
fsl_qspi_unlock_lut(q);
|
||||
|
||||
- /* Clear all the LUT table */
|
||||
- for (i = 0; i < QUADSPI_LUT_NUM; i++)
|
||||
- qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
|
||||
-
|
||||
- /* Read */
|
||||
- lut_base = SEQID_READ * 4;
|
||||
-
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
- qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
|
||||
- LUT1(FSL_READ, PAD4, rxfifo),
|
||||
- base + QUADSPI_LUT(lut_base + 1));
|
||||
-
|
||||
- /* Write enable */
|
||||
- lut_base = SEQID_WREN * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Page Program */
|
||||
- lut_base = SEQID_PP * 4;
|
||||
-
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
|
||||
- LUT1(ADDR, PAD1, addrlen),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
- qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
|
||||
- base + QUADSPI_LUT(lut_base + 1));
|
||||
-
|
||||
- /* Read Status */
|
||||
- lut_base = SEQID_RDSR * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDSR) |
|
||||
- LUT1(FSL_READ, PAD1, 0x1),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Erase a sector */
|
||||
- lut_base = SEQID_SE * 4;
|
||||
-
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
|
||||
- LUT1(ADDR, PAD1, addrlen),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Erase the whole chip */
|
||||
- lut_base = SEQID_CHIP_ERASE * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* READ ID */
|
||||
- lut_base = SEQID_RDID * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDID) |
|
||||
- LUT1(FSL_READ, PAD1, 0x8),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Write Register */
|
||||
- lut_base = SEQID_WRSR * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRSR) |
|
||||
- LUT1(FSL_WRITE, PAD1, 0x2),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Read Configuration Register */
|
||||
- lut_base = SEQID_RDCR * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RDCR) |
|
||||
- LUT1(FSL_READ, PAD1, 0x1),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Write disable */
|
||||
- lut_base = SEQID_WRDI * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WRDI),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Enter 4 Byte Mode (Micron) */
|
||||
- lut_base = SEQID_EN4B * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_EN4B),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
-
|
||||
- /* Enter 4 Byte Mode (Spansion) */
|
||||
- lut_base = SEQID_BRWR * 4;
|
||||
- qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
|
||||
- base + QUADSPI_LUT(lut_base));
|
||||
+ /* Dynamic LUT */
|
||||
+ lut_base = SEQID_LUT1_RUNTIME * 4;
|
||||
+ if (ops == FSL_QSPI_OPS_READ)
|
||||
+ lut_base = SEQID_LUT2_AHBREAD * 4;
|
||||
+
|
||||
+ /* default, STOP instruction to be programmed in (lut_base + 1) reg */
|
||||
+ stop_lut = 1;
|
||||
+ switch (ops) {
|
||||
+ case FSL_QSPI_OPS_READ_REG:
|
||||
+ qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
|
||||
+ LUT1(FSL_READ, pad_count(data_pad), rxfifo),
|
||||
+ base + QUADSPI_LUT(lut_base));
|
||||
+ break;
|
||||
+ case FSL_QSPI_OPS_WRITE_REG:
|
||||
+ qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode),
|
||||
+ base + QUADSPI_LUT(lut_base));
|
||||
+ break;
|
||||
+ case FSL_QSPI_OPS_WRITE_BUF_REG:
|
||||
+ qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
|
||||
+ LUT1(FSL_WRITE, pad_count(data_pad), txfifo),
|
||||
+ base + QUADSPI_LUT(lut_base));
|
||||
+ break;
|
||||
+ case FSL_QSPI_OPS_READ:
|
||||
+ case FSL_QSPI_OPS_WRITE:
|
||||
+ case FSL_QSPI_OPS_ERASE:
|
||||
+ /* Common for Read, Write and Erase ops. */
|
||||
+
|
||||
+ addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
|
||||
+
|
||||
+ qspi_writel(q, LUT0(CMD, pad_count(cmd_pad), opcode) |
|
||||
+ LUT1(ADDR, pad_count(addr_pad), addrlen),
|
||||
+ base + QUADSPI_LUT(lut_base));
|
||||
+ /*
|
||||
+ * For Erase ops - Data and Dummy not required.
|
||||
+ * For Write ops - Dummy not required.
|
||||
+ */
|
||||
|
||||
- fsl_qspi_lock_lut(q);
|
||||
-}
|
||||
+ if (ops == FSL_QSPI_OPS_READ) {
|
||||
|
||||
-/* Get the SEQID for the command */
|
||||
-static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
|
||||
-{
|
||||
- switch (cmd) {
|
||||
- case SPINOR_OP_READ_1_1_4:
|
||||
- case SPINOR_OP_READ_1_1_4_4B:
|
||||
- return SEQID_READ;
|
||||
- case SPINOR_OP_WREN:
|
||||
- return SEQID_WREN;
|
||||
- case SPINOR_OP_WRDI:
|
||||
- return SEQID_WRDI;
|
||||
- case SPINOR_OP_RDSR:
|
||||
- return SEQID_RDSR;
|
||||
- case SPINOR_OP_SE:
|
||||
- return SEQID_SE;
|
||||
- case SPINOR_OP_CHIP_ERASE:
|
||||
- return SEQID_CHIP_ERASE;
|
||||
- case SPINOR_OP_PP:
|
||||
- return SEQID_PP;
|
||||
- case SPINOR_OP_RDID:
|
||||
- return SEQID_RDID;
|
||||
- case SPINOR_OP_WRSR:
|
||||
- return SEQID_WRSR;
|
||||
- case SPINOR_OP_RDCR:
|
||||
- return SEQID_RDCR;
|
||||
- case SPINOR_OP_EN4B:
|
||||
- return SEQID_EN4B;
|
||||
- case SPINOR_OP_BRWR:
|
||||
- return SEQID_BRWR;
|
||||
+ /*
|
||||
+ * For cmds SPINOR_OP_READ and SPINOR_OP_READ_4B value
|
||||
+ * of dummy cycles are 0.
|
||||
+ */
|
||||
+ if (read_dm)
|
||||
+ qspi_writel(q,
|
||||
+ LUT0(DUMMY, pad_count(dummy_pad),
|
||||
+ read_dm) |
|
||||
+ LUT1(FSL_READ, pad_count(data_pad),
|
||||
+ rxfifo),
|
||||
+ base + QUADSPI_LUT(lut_base + 1));
|
||||
+ else
|
||||
+ qspi_writel(q,
|
||||
+ LUT0(FSL_READ, pad_count(data_pad),
|
||||
+ rxfifo),
|
||||
+ base + QUADSPI_LUT(lut_base + 1));
|
||||
+
|
||||
+ stop_lut = 2;
|
||||
+
|
||||
+ /* TODO Add condition to check if READ is IP/AHB. */
|
||||
+
|
||||
+ /* For AHB read, add seqid in BFGENCR register. */
|
||||
+ qspi_writel(q,
|
||||
+ SEQID_LUT2_AHBREAD <<
|
||||
+ QUADSPI_BFGENCR_SEQID_SHIFT,
|
||||
+ q->iobase + QUADSPI_BFGENCR);
|
||||
+ }
|
||||
+
|
||||
+ if (ops == FSL_QSPI_OPS_WRITE) {
|
||||
+ qspi_writel(q, LUT0(FSL_WRITE, pad_count(data_pad), 0),
|
||||
+ base + QUADSPI_LUT(lut_base + 1));
|
||||
+ stop_lut = 2;
|
||||
+ }
|
||||
+ break;
|
||||
default:
|
||||
- if (cmd == q->nor[0].erase_opcode)
|
||||
- return SEQID_SE;
|
||||
- dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
|
||||
+ dev_err(q->dev, "Unsupported operation 0x%.2x\n", ops);
|
||||
break;
|
||||
}
|
||||
- return -EINVAL;
|
||||
+
|
||||
+ /* prepare LUT for STOP instruction. */
|
||||
+ qspi_writel(q, 0, base + QUADSPI_LUT(lut_base + stop_lut));
|
||||
+
|
||||
+ fsl_qspi_lock_lut(q);
|
||||
}
|
||||
|
||||
static int
|
||||
@@ -508,6 +559,10 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
|
||||
int seqid;
|
||||
u32 reg, reg2;
|
||||
int err;
|
||||
+ u32 memmap_phyadd = q->memmap_phy;
|
||||
+
|
||||
+ if (need_address_remap(q))
|
||||
+ memmap_phyadd = 0;
|
||||
|
||||
init_completion(&q->c);
|
||||
dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
|
||||
@@ -516,7 +571,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
|
||||
/* save the reg */
|
||||
reg = qspi_readl(q, base + QUADSPI_MCR);
|
||||
|
||||
- qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
|
||||
+ qspi_writel(q, memmap_phyadd + q->chip_base_addr + addr,
|
||||
base + QUADSPI_SFAR);
|
||||
qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
|
||||
base + QUADSPI_RBCT);
|
||||
@@ -533,7 +588,7 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 c
|
||||
} while (1);
|
||||
|
||||
/* trigger the LUT now */
|
||||
- seqid = fsl_qspi_get_seqid(q, cmd);
|
||||
+ seqid = SEQID_LUT1_RUNTIME;
|
||||
qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
|
||||
base + QUADSPI_IPCR);
|
||||
|
||||
@@ -609,6 +664,7 @@ static ssize_t fsl_qspi_nor_write(struct
|
||||
{
|
||||
int ret, i, j;
|
||||
u32 tmp;
|
||||
+ u8 byts;
|
||||
|
||||
dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
|
||||
q->chip_base_addr, to, count);
|
||||
@@ -618,10 +674,18 @@ static ssize_t fsl_qspi_nor_write(struct
|
||||
qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
|
||||
|
||||
/* fill the TX data to the FIFO */
|
||||
+ byts = count;
|
||||
for (j = 0, i = ((count + 3) / 4); j < i; j++) {
|
||||
- tmp = fsl_qspi_endian_xchg(q, *txbuf);
|
||||
+ if(byts >= 4)
|
||||
+ tmp = fsl_qspi_endian_xchg(q, *txbuf);
|
||||
+ else {
|
||||
+ memcpy(&tmp, txbuf, byts);
|
||||
+ tmp = fsl_qspi_endian_xchg(q, tmp);
|
||||
+ }
|
||||
+
|
||||
qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
|
||||
txbuf++;
|
||||
+ byts -= 4;
|
||||
}
|
||||
|
||||
/* fill the TXFIFO upto 16 bytes for i.MX7d */
|
||||
@@ -642,11 +706,15 @@ static void fsl_qspi_set_map_addr(struct
|
||||
{
|
||||
int nor_size = q->nor_size;
|
||||
void __iomem *base = q->iobase;
|
||||
+ u32 memmap_phyadd = q->memmap_phy;
|
||||
+
|
||||
+ if (need_address_remap(q))
|
||||
+ memmap_phyadd = 0;
|
||||
|
||||
- qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
|
||||
- qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
|
||||
- qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
|
||||
- qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
|
||||
+ qspi_writel(q, nor_size + memmap_phyadd, base + QUADSPI_SFA1AD);
|
||||
+ qspi_writel(q, nor_size * 2 + memmap_phyadd, base + QUADSPI_SFA2AD);
|
||||
+ qspi_writel(q, nor_size * 3 + memmap_phyadd, base + QUADSPI_SFB1AD);
|
||||
+ qspi_writel(q, nor_size * 4 + memmap_phyadd, base + QUADSPI_SFB2AD);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -662,7 +730,7 @@ static void fsl_qspi_set_map_addr(struct
|
||||
* causes the controller to clear the buffer, and use the sequence pointed
|
||||
* by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
|
||||
*/
|
||||
-static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
|
||||
+static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
|
||||
{
|
||||
void __iomem *base = q->iobase;
|
||||
int seqid;
|
||||
@@ -685,8 +753,8 @@ static void fsl_qspi_init_abh_read(struc
|
||||
qspi_writel(q, 0, base + QUADSPI_BUF1IND);
|
||||
qspi_writel(q, 0, base + QUADSPI_BUF2IND);
|
||||
|
||||
- /* Set the default lut sequence for AHB Read. */
|
||||
- seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
|
||||
+ /* Set dynamic LUT entry as lut sequence for AHB Read . */
|
||||
+ seqid = SEQID_LUT2_AHBREAD;
|
||||
qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
|
||||
q->iobase + QUADSPI_BFGENCR);
|
||||
}
|
||||
@@ -729,7 +797,6 @@ static int fsl_qspi_nor_setup(struct fsl
|
||||
void __iomem *base = q->iobase;
|
||||
u32 reg;
|
||||
int ret;
|
||||
-
|
||||
/* disable and unprepare clock to avoid glitch pass to controller */
|
||||
fsl_qspi_clk_disable_unprep(q);
|
||||
|
||||
@@ -747,9 +814,6 @@ static int fsl_qspi_nor_setup(struct fsl
|
||||
base + QUADSPI_MCR);
|
||||
udelay(1);
|
||||
|
||||
- /* Init the LUT table. */
|
||||
- fsl_qspi_init_lut(q);
|
||||
-
|
||||
/* Disable the module */
|
||||
qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
|
||||
base + QUADSPI_MCR);
|
||||
@@ -770,6 +834,9 @@ static int fsl_qspi_nor_setup(struct fsl
|
||||
/* enable the interrupt */
|
||||
qspi_writel(q, QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
|
||||
|
||||
+ /* Init for AHB read */
|
||||
+ fsl_qspi_init_ahb_read(q);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -792,12 +859,6 @@ static int fsl_qspi_nor_setup_last(struc
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
- /* Init the LUT table again. */
|
||||
- fsl_qspi_init_lut(q);
|
||||
-
|
||||
- /* Init for AHB read */
|
||||
- fsl_qspi_init_abh_read(q);
|
||||
-
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -807,6 +868,7 @@ static const struct of_device_id fsl_qsp
|
||||
{ .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
|
||||
{ .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
|
||||
{ .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
|
||||
+ { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
|
||||
@@ -821,6 +883,7 @@ static int fsl_qspi_read_reg(struct spi_
|
||||
int ret;
|
||||
struct fsl_qspi *q = nor->priv;
|
||||
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ_REG, opcode);
|
||||
ret = fsl_qspi_runcmd(q, opcode, 0, len);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -835,6 +898,8 @@ static int fsl_qspi_write_reg(struct spi
|
||||
int ret;
|
||||
|
||||
if (!buf) {
|
||||
+ /* Prepare LUT for WRITE_REG cmd with input BUF as NULL. */
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE_REG, opcode);
|
||||
ret = fsl_qspi_runcmd(q, opcode, 0, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -843,6 +908,8 @@ static int fsl_qspi_write_reg(struct spi
|
||||
fsl_qspi_invalid(q);
|
||||
|
||||
} else if (len > 0) {
|
||||
+ /* Prepare LUT for WRITE_REG cmd with input BUF non-NULL. */
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE_BUF_REG, opcode);
|
||||
ret = fsl_qspi_nor_write(q, nor, opcode, 0,
|
||||
(u32 *)buf, len);
|
||||
if (ret > 0)
|
||||
@@ -859,8 +926,11 @@ static ssize_t fsl_qspi_write(struct spi
|
||||
size_t len, const u_char *buf)
|
||||
{
|
||||
struct fsl_qspi *q = nor->priv;
|
||||
- ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
|
||||
- (u32 *)buf, len);
|
||||
+ ssize_t ret;
|
||||
+
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_WRITE, nor->program_opcode);
|
||||
+ ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
|
||||
+ (u32 *)buf, len);
|
||||
|
||||
/* invalid the data in the AHB buffer. */
|
||||
fsl_qspi_invalid(q);
|
||||
@@ -873,6 +943,8 @@ static ssize_t fsl_qspi_read(struct spi_
|
||||
struct fsl_qspi *q = nor->priv;
|
||||
u8 cmd = nor->read_opcode;
|
||||
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ, nor->read_opcode);
|
||||
+
|
||||
/* if necessary,ioremap buffer before AHB read, */
|
||||
if (!q->ahb_addr) {
|
||||
q->memmap_offs = q->chip_base_addr + from;
|
||||
@@ -907,8 +979,9 @@ static ssize_t fsl_qspi_read(struct spi_
|
||||
len);
|
||||
|
||||
/* Read out the data directly from the AHB buffer.*/
|
||||
- memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
|
||||
- len);
|
||||
+ memcpy_fromio(buf,
|
||||
+ q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
|
||||
+ len);
|
||||
|
||||
return len;
|
||||
}
|
||||
@@ -921,6 +994,7 @@ static int fsl_qspi_erase(struct spi_nor
|
||||
dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
|
||||
nor->mtd.erasesize / 1024, q->chip_base_addr, (u32)offs);
|
||||
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_ERASE, nor->erase_opcode);
|
||||
ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -958,17 +1032,14 @@ static void fsl_qspi_unprep(struct spi_n
|
||||
|
||||
static int fsl_qspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
- const struct spi_nor_hwcaps hwcaps = {
|
||||
- .mask = SNOR_HWCAPS_READ_1_1_4 |
|
||||
- SNOR_HWCAPS_PP,
|
||||
- };
|
||||
+ struct spi_nor_hwcaps hwcaps;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct fsl_qspi *q;
|
||||
struct resource *res;
|
||||
struct spi_nor *nor;
|
||||
struct mtd_info *mtd;
|
||||
- int ret, i = 0;
|
||||
+ int ret, i = 0, value;
|
||||
|
||||
q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
|
||||
if (!q)
|
||||
@@ -1041,6 +1112,10 @@ static int fsl_qspi_probe(struct platfor
|
||||
|
||||
/* iterate the subnodes. */
|
||||
for_each_available_child_of_node(dev->of_node, np) {
|
||||
+ /* Reset hwcaps mask to minimal caps for the slave node. */
|
||||
+ hwcaps.mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP;
|
||||
+ value = 0;
|
||||
+
|
||||
/* skip the holes */
|
||||
if (!q->has_second_chip)
|
||||
i *= 2;
|
||||
@@ -1070,6 +1145,51 @@ static int fsl_qspi_probe(struct platfor
|
||||
/* set the chip address for READID */
|
||||
fsl_qspi_set_base_addr(q, nor);
|
||||
|
||||
+ /*
|
||||
+ * If spi-rx-bus-width and spi-tx-bus-width not defined assign
|
||||
+ * default hardware capabilities SNOR_HWCAPS_READ_1_1_4 and
|
||||
+ * SNOR_HWCAPS_PP supported by the Quad-SPI controller.
|
||||
+ */
|
||||
+ if (!of_property_read_u32(np, "spi-rx-bus-width", &value)) {
|
||||
+ switch (value) {
|
||||
+ case 1:
|
||||
+ hwcaps.mask |= SNOR_HWCAPS_READ |
|
||||
+ SNOR_HWCAPS_READ_FAST;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2 |
|
||||
+ SNOR_HWCAPS_READ_1_2_2;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4 |
|
||||
+ SNOR_HWCAPS_READ_1_4_4;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(dev,
|
||||
+ "spi-rx-bus-width %d not supported\n",
|
||||
+ value);
|
||||
+ break;
|
||||
+ }
|
||||
+ } else
|
||||
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
|
||||
+
|
||||
+ if (!of_property_read_u32(np, "spi-tx-bus-width", &value)) {
|
||||
+ switch (value) {
|
||||
+ case 1:
|
||||
+ hwcaps.mask |= SNOR_HWCAPS_PP;
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4 |
|
||||
+ SNOR_HWCAPS_PP_1_4_4;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(dev,
|
||||
+ "spi-tx-bus-width %d not supported\n",
|
||||
+ value);
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
ret = spi_nor_scan(nor, NULL, &hwcaps);
|
||||
if (ret)
|
||||
goto mutex_failed;
|
||||
@@ -1098,6 +1218,8 @@ static int fsl_qspi_probe(struct platfor
|
||||
if (nor->page_size > q->devtype_data->txfifo)
|
||||
nor->page_size = q->devtype_data->txfifo;
|
||||
|
||||
+ /*required for memory mapped AHB read*/
|
||||
+ fsl_qspi_prepare_lut(nor, FSL_QSPI_OPS_READ, nor->read_opcode);
|
||||
i++;
|
||||
}
|
||||
|
||||
@@ -1106,6 +1228,8 @@ static int fsl_qspi_probe(struct platfor
|
||||
if (ret)
|
||||
goto last_init_failed;
|
||||
|
||||
+
|
||||
+
|
||||
fsl_qspi_clk_disable_unprep(q);
|
||||
return 0;
|
||||
|
||||
--- a/drivers/mtd/spi-nor/spi-nor.c
|
||||
+++ b/drivers/mtd/spi-nor/spi-nor.c
|
||||
@@ -1146,6 +1146,11 @@ static const struct flash_info spi_nor_i
|
||||
{ "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
|
||||
{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
|
||||
{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
|
||||
+ {
|
||||
+ "w25q16dw", INFO(0xef6015, 0, 64 * 1024, 32,
|
||||
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
|
||||
+ },
|
||||
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
|
||||
{ "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
|
||||
{ "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
|
||||
@ -0,0 +1,147 @@
|
||||
From f901f791d07deaeba6310ac070769575a0bb790a Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:27:54 +0800
|
||||
Subject: [PATCH 36/40] sdhc: support layerscape
|
||||
This is an integrated patch of sdhc for layerscape
|
||||
|
||||
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/mmc/host/sdhci-of-esdhc.c | 85 +++++++++++++++++++++----------
|
||||
1 file changed, 57 insertions(+), 28 deletions(-)
|
||||
|
||||
--- a/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
@@ -30,11 +30,56 @@
|
||||
#define VENDOR_V_22 0x12
|
||||
#define VENDOR_V_23 0x13
|
||||
|
||||
+#define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1)
|
||||
+
|
||||
+struct esdhc_clk_fixup {
|
||||
+ const unsigned int sd_dflt_max_clk;
|
||||
+ const unsigned int max_clk[MMC_TIMING_NUM];
|
||||
+};
|
||||
+
|
||||
+static const struct esdhc_clk_fixup ls1021a_esdhc_clk = {
|
||||
+ .sd_dflt_max_clk = 25000000,
|
||||
+ .max_clk[MMC_TIMING_MMC_HS] = 46500000,
|
||||
+ .max_clk[MMC_TIMING_SD_HS] = 46500000,
|
||||
+};
|
||||
+
|
||||
+static const struct esdhc_clk_fixup ls1046a_esdhc_clk = {
|
||||
+ .sd_dflt_max_clk = 25000000,
|
||||
+ .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
|
||||
+ .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
|
||||
+};
|
||||
+
|
||||
+static const struct esdhc_clk_fixup ls1012a_esdhc_clk = {
|
||||
+ .sd_dflt_max_clk = 25000000,
|
||||
+ .max_clk[MMC_TIMING_UHS_SDR104] = 125000000,
|
||||
+ .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
|
||||
+};
|
||||
+
|
||||
+static const struct esdhc_clk_fixup p1010_esdhc_clk = {
|
||||
+ .sd_dflt_max_clk = 20000000,
|
||||
+ .max_clk[MMC_TIMING_LEGACY] = 20000000,
|
||||
+ .max_clk[MMC_TIMING_MMC_HS] = 42000000,
|
||||
+ .max_clk[MMC_TIMING_SD_HS] = 40000000,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id sdhci_esdhc_of_match[] = {
|
||||
+ { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
|
||||
+ { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
|
||||
+ { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
|
||||
+ { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
|
||||
+ { .compatible = "fsl,mpc8379-esdhc" },
|
||||
+ { .compatible = "fsl,mpc8536-esdhc" },
|
||||
+ { .compatible = "fsl,esdhc" },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
|
||||
+
|
||||
struct sdhci_esdhc {
|
||||
u8 vendor_ver;
|
||||
u8 spec_ver;
|
||||
bool quirk_incorrect_hostver;
|
||||
unsigned int peripheral_clock;
|
||||
+ const struct esdhc_clk_fixup *clk_fixup;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -498,6 +543,7 @@ static void esdhc_of_set_clock(struct sd
|
||||
int pre_div = 1;
|
||||
int div = 1;
|
||||
ktime_t timeout;
|
||||
+ long fixup = 0;
|
||||
u32 temp;
|
||||
|
||||
host->mmc->actual_clock = 0;
|
||||
@@ -511,27 +557,14 @@ static void esdhc_of_set_clock(struct sd
|
||||
if (esdhc->vendor_ver < VENDOR_V_23)
|
||||
pre_div = 2;
|
||||
|
||||
- /*
|
||||
- * Limit SD clock to 167MHz for ls1046a according to its datasheet
|
||||
- */
|
||||
- if (clock > 167000000 &&
|
||||
- of_find_compatible_node(NULL, NULL, "fsl,ls1046a-esdhc"))
|
||||
- clock = 167000000;
|
||||
+ if (host->mmc->card && mmc_card_sd(host->mmc->card) &&
|
||||
+ esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY)
|
||||
+ fixup = esdhc->clk_fixup->sd_dflt_max_clk;
|
||||
+ else if (esdhc->clk_fixup)
|
||||
+ fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing];
|
||||
|
||||
- /*
|
||||
- * Limit SD clock to 125MHz for ls1012a according to its datasheet
|
||||
- */
|
||||
- if (clock > 125000000 &&
|
||||
- of_find_compatible_node(NULL, NULL, "fsl,ls1012a-esdhc"))
|
||||
- clock = 125000000;
|
||||
-
|
||||
- /* Workaround to reduce the clock frequency for p1010 esdhc */
|
||||
- if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
|
||||
- if (clock > 20000000)
|
||||
- clock -= 5000000;
|
||||
- if (clock > 40000000)
|
||||
- clock -= 5000000;
|
||||
- }
|
||||
+ if (fixup && clock > fixup)
|
||||
+ clock = fixup;
|
||||
|
||||
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
|
||||
temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN |
|
||||
@@ -789,6 +822,7 @@ static struct soc_device_attribute soc_i
|
||||
|
||||
static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
|
||||
{
|
||||
+ const struct of_device_id *match;
|
||||
struct sdhci_pltfm_host *pltfm_host;
|
||||
struct sdhci_esdhc *esdhc;
|
||||
struct device_node *np;
|
||||
@@ -808,6 +842,9 @@ static void esdhc_init(struct platform_d
|
||||
else
|
||||
esdhc->quirk_incorrect_hostver = false;
|
||||
|
||||
+ match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node);
|
||||
+ if (match)
|
||||
+ esdhc->clk_fixup = match->data;
|
||||
np = pdev->dev.of_node;
|
||||
clk = of_clk_get(np, 0);
|
||||
if (!IS_ERR(clk)) {
|
||||
@@ -907,14 +944,6 @@ static int sdhci_esdhc_probe(struct plat
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static const struct of_device_id sdhci_esdhc_of_match[] = {
|
||||
- { .compatible = "fsl,mpc8379-esdhc" },
|
||||
- { .compatible = "fsl,mpc8536-esdhc" },
|
||||
- { .compatible = "fsl,esdhc" },
|
||||
- { }
|
||||
-};
|
||||
-MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
|
||||
-
|
||||
static struct platform_driver sdhci_esdhc_driver = {
|
||||
.driver = {
|
||||
.name = "sdhci-esdhc",
|
||||
13093
target/linux/layerscape/patches-4.14/820-sec-support-layerscape.patch
Normal file
13093
target/linux/layerscape/patches-4.14/820-sec-support-layerscape.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,506 @@
|
||||
From 05375244c8e74f90239db92646a771905fdfc0db Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:28:22 +0800
|
||||
Subject: [PATCH 38/40] smmu: support layerscape
|
||||
This is an integrated patch of smmu for layerscape
|
||||
|
||||
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
|
||||
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
|
||||
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
.../devicetree/bindings/misc/fsl,qoriq-mc.txt | 39 ++++++
|
||||
drivers/iommu/arm-smmu.c | 7 +
|
||||
drivers/iommu/iommu.c | 21 +++
|
||||
drivers/iommu/of_iommu.c | 126 +++++++++++++++++-
|
||||
drivers/of/irq.c | 6 +-
|
||||
drivers/of/of_pci.c | 101 --------------
|
||||
include/linux/iommu.h | 2 +
|
||||
include/linux/of_iommu.h | 10 ++
|
||||
include/linux/of_pci.h | 10 --
|
||||
9 files changed, 205 insertions(+), 117 deletions(-)
|
||||
|
||||
--- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
|
||||
+++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
|
||||
@@ -9,6 +9,25 @@ blocks that can be used to create functi
|
||||
such as network interfaces, crypto accelerator instances, L2 switches,
|
||||
etc.
|
||||
|
||||
+For an overview of the DPAA2 architecture and fsl-mc bus see:
|
||||
+drivers/staging/fsl-mc/README.txt
|
||||
+
|
||||
+As described in the above overview, all DPAA2 objects in a DPRC share the
|
||||
+same hardware "isolation context" and a 10-bit value called an ICID
|
||||
+(isolation context id) is expressed by the hardware to identify
|
||||
+the requester.
|
||||
+
|
||||
+The generic 'iommus' property is insufficient to describe the relationship
|
||||
+between ICIDs and IOMMUs, so an iommu-map property is used to define
|
||||
+the set of possible ICIDs under a root DPRC and how they map to
|
||||
+an IOMMU.
|
||||
+
|
||||
+For generic IOMMU bindings, see
|
||||
+Documentation/devicetree/bindings/iommu/iommu.txt.
|
||||
+
|
||||
+For arm-smmu binding, see:
|
||||
+Documentation/devicetree/bindings/iommu/arm,smmu.txt.
|
||||
+
|
||||
Required properties:
|
||||
|
||||
- compatible
|
||||
@@ -88,14 +107,34 @@ Sub-nodes:
|
||||
Value type: <phandle>
|
||||
Definition: Specifies the phandle to the PHY device node associated
|
||||
with the this dpmac.
|
||||
+Optional properties:
|
||||
+
|
||||
+- iommu-map: Maps an ICID to an IOMMU and associated iommu-specifier
|
||||
+ data.
|
||||
+
|
||||
+ The property is an arbitrary number of tuples of
|
||||
+ (icid-base,iommu,iommu-base,length).
|
||||
+
|
||||
+ Any ICID i in the interval [icid-base, icid-base + length) is
|
||||
+ associated with the listed IOMMU, with the iommu-specifier
|
||||
+ (i - icid-base + iommu-base).
|
||||
|
||||
Example:
|
||||
|
||||
+ smmu: iommu@5000000 {
|
||||
+ compatible = "arm,mmu-500";
|
||||
+ #iommu-cells = <2>;
|
||||
+ stream-match-mask = <0x7C00>;
|
||||
+ ...
|
||||
+ };
|
||||
+
|
||||
fsl_mc: fsl-mc@80c000000 {
|
||||
compatible = "fsl,qoriq-mc";
|
||||
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
||||
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
||||
msi-parent = <&its>;
|
||||
+ /* define map for ICIDs 23-64 */
|
||||
+ iommu-map = <23 &smmu 23 41>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <1>;
|
||||
|
||||
--- a/drivers/iommu/arm-smmu.c
|
||||
+++ b/drivers/iommu/arm-smmu.c
|
||||
@@ -52,6 +52,7 @@
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include <linux/amba/bus.h>
|
||||
+#include <linux/fsl/mc.h>
|
||||
|
||||
#include "io-pgtable.h"
|
||||
#include "arm-smmu-regs.h"
|
||||
@@ -1464,6 +1465,8 @@ static struct iommu_group *arm_smmu_devi
|
||||
|
||||
if (dev_is_pci(dev))
|
||||
group = pci_device_group(dev);
|
||||
+ else if (dev_is_fsl_mc(dev))
|
||||
+ group = fsl_mc_device_group(dev);
|
||||
else
|
||||
group = generic_device_group(dev);
|
||||
|
||||
@@ -2040,6 +2043,10 @@ static void arm_smmu_bus_init(void)
|
||||
bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
|
||||
}
|
||||
#endif
|
||||
+#ifdef CONFIG_FSL_MC_BUS
|
||||
+ if (!iommu_present(&fsl_mc_bus_type))
|
||||
+ bus_set_iommu(&fsl_mc_bus_type, &arm_smmu_ops);
|
||||
+#endif
|
||||
}
|
||||
|
||||
static int arm_smmu_device_probe(struct platform_device *pdev)
|
||||
--- a/drivers/iommu/iommu.c
|
||||
+++ b/drivers/iommu/iommu.c
|
||||
@@ -33,6 +33,7 @@
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/property.h>
|
||||
#include <trace/events/iommu.h>
|
||||
+#include <linux/fsl/mc.h>
|
||||
|
||||
static struct kset *iommu_group_kset;
|
||||
static DEFINE_IDA(iommu_group_ida);
|
||||
@@ -987,6 +988,26 @@ struct iommu_group *pci_device_group(str
|
||||
return iommu_group_alloc();
|
||||
}
|
||||
|
||||
+/* Get the IOMMU group for device on fsl-mc bus */
|
||||
+struct iommu_group *fsl_mc_device_group(struct device *dev)
|
||||
+{
|
||||
+ struct device *cont_dev = fsl_mc_cont_dev(dev);
|
||||
+ struct iommu_group *group;
|
||||
+
|
||||
+ /* Container device is responsible for creating the iommu group */
|
||||
+ if (fsl_mc_is_cont_dev(dev)) {
|
||||
+ group = iommu_group_alloc();
|
||||
+ if (IS_ERR(group))
|
||||
+ return NULL;
|
||||
+ } else {
|
||||
+ get_device(cont_dev);
|
||||
+ group = iommu_group_get(cont_dev);
|
||||
+ put_device(cont_dev);
|
||||
+ }
|
||||
+
|
||||
+ return group;
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* iommu_group_get_for_dev - Find or create the IOMMU group for a device
|
||||
* @dev: target device
|
||||
--- a/drivers/iommu/of_iommu.c
|
||||
+++ b/drivers/iommu/of_iommu.c
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/of_iommu.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/slab.h>
|
||||
+#include <linux/fsl/mc.h>
|
||||
|
||||
#define NO_IOMMU 1
|
||||
|
||||
@@ -143,15 +144,115 @@ struct of_pci_iommu_alias_info {
|
||||
struct device_node *np;
|
||||
};
|
||||
|
||||
+/**
|
||||
+ * of_map_rid - Translate a requester ID through a downstream mapping.
|
||||
+ * @np: root complex device node.
|
||||
+ * @rid: Requester ID to map.
|
||||
+ * @map_name: property name of the map to use.
|
||||
+ * @map_mask_name: optional property name of the mask to use.
|
||||
+ * @target: optional pointer to a target device node.
|
||||
+ * @id_out: optional pointer to receive the translated ID.
|
||||
+ *
|
||||
+ * Given PCI/MC requester ID, look up the appropriate implementation-defined
|
||||
+ * platform ID and/or the target device which receives transactions on that
|
||||
+ * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
|
||||
+ * @id_out may be NULL if only the other is required. If @target points to
|
||||
+ * a non-NULL device node pointer, only entries targeting that node will be
|
||||
+ * matched; if it points to a NULL value, it will receive the device node of
|
||||
+ * the first matching target phandle, with a reference held.
|
||||
+ *
|
||||
+ * Return: 0 on success or a standard error code on failure.
|
||||
+ */
|
||||
+int of_map_rid(struct device_node *np, u32 rid,
|
||||
+ const char *map_name, const char *map_mask_name,
|
||||
+ struct device_node **target, u32 *id_out)
|
||||
+{
|
||||
+ u32 map_mask, masked_rid;
|
||||
+ int map_len;
|
||||
+ const __be32 *map = NULL;
|
||||
+
|
||||
+ if (!np || !map_name || (!target && !id_out))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ map = of_get_property(np, map_name, &map_len);
|
||||
+ if (!map) {
|
||||
+ if (target)
|
||||
+ return -ENODEV;
|
||||
+ /* Otherwise, no map implies no translation */
|
||||
+ *id_out = rid;
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ if (!map_len || map_len % (4 * sizeof(*map))) {
|
||||
+ pr_err("%pOF: Error: Bad %s length: %d\n", np,
|
||||
+ map_name, map_len);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /* The default is to select all bits. */
|
||||
+ map_mask = 0xffffffff;
|
||||
+
|
||||
+ /*
|
||||
+ * Can be overridden by "{iommu,msi}-map-mask" property.
|
||||
+ * If of_property_read_u32() fails, the default is used.
|
||||
+ */
|
||||
+ if (map_mask_name)
|
||||
+ of_property_read_u32(np, map_mask_name, &map_mask);
|
||||
+
|
||||
+ masked_rid = map_mask & rid;
|
||||
+ for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
|
||||
+ struct device_node *phandle_node;
|
||||
+ u32 rid_base = be32_to_cpup(map + 0);
|
||||
+ u32 phandle = be32_to_cpup(map + 1);
|
||||
+ u32 out_base = be32_to_cpup(map + 2);
|
||||
+ u32 rid_len = be32_to_cpup(map + 3);
|
||||
+
|
||||
+ if (rid_base & ~map_mask) {
|
||||
+ pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
|
||||
+ np, map_name, map_name,
|
||||
+ map_mask, rid_base);
|
||||
+ return -EFAULT;
|
||||
+ }
|
||||
+
|
||||
+ if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
|
||||
+ continue;
|
||||
+
|
||||
+ phandle_node = of_find_node_by_phandle(phandle);
|
||||
+ if (!phandle_node)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ if (target) {
|
||||
+ if (*target)
|
||||
+ of_node_put(phandle_node);
|
||||
+ else
|
||||
+ *target = phandle_node;
|
||||
+
|
||||
+ if (*target != phandle_node)
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ if (id_out)
|
||||
+ *id_out = masked_rid - rid_base + out_base;
|
||||
+
|
||||
+ pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
|
||||
+ np, map_name, map_mask, rid_base, out_base,
|
||||
+ rid_len, rid, *id_out);
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
+ pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
|
||||
+ np, map_name, rid, target && *target ? *target : NULL);
|
||||
+ return -EFAULT;
|
||||
+}
|
||||
static int of_pci_iommu_init(struct pci_dev *pdev, u16 alias, void *data)
|
||||
{
|
||||
struct of_pci_iommu_alias_info *info = data;
|
||||
struct of_phandle_args iommu_spec = { .args_count = 1 };
|
||||
int err;
|
||||
|
||||
- err = of_pci_map_rid(info->np, alias, "iommu-map",
|
||||
- "iommu-map-mask", &iommu_spec.np,
|
||||
- iommu_spec.args);
|
||||
+ err = of_map_rid(info->np, alias, "iommu-map",
|
||||
+ "iommu-map-mask", &iommu_spec.np,
|
||||
+ iommu_spec.args);
|
||||
if (err)
|
||||
return err == -ENODEV ? NO_IOMMU : err;
|
||||
|
||||
@@ -160,6 +261,23 @@ static int of_pci_iommu_init(struct pci_
|
||||
return err;
|
||||
}
|
||||
|
||||
+static int of_fsl_mc_iommu_init(struct fsl_mc_device *mc_dev,
|
||||
+ struct device_node *master_np)
|
||||
+{
|
||||
+ struct of_phandle_args iommu_spec = { .args_count = 1 };
|
||||
+ int err;
|
||||
+
|
||||
+ err = of_map_rid(master_np, mc_dev->icid, "iommu-map",
|
||||
+ "iommu-map-mask", &iommu_spec.np,
|
||||
+ iommu_spec.args);
|
||||
+ if (err)
|
||||
+ return err == -ENODEV ? NO_IOMMU : err;
|
||||
+
|
||||
+ err = of_iommu_xlate(&mc_dev->dev, &iommu_spec);
|
||||
+ of_node_put(iommu_spec.np);
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
const struct iommu_ops *of_iommu_configure(struct device *dev,
|
||||
struct device_node *master_np)
|
||||
{
|
||||
@@ -191,6 +309,8 @@ const struct iommu_ops *of_iommu_configu
|
||||
|
||||
err = pci_for_each_dma_alias(to_pci_dev(dev),
|
||||
of_pci_iommu_init, &info);
|
||||
+ } else if (dev_is_fsl_mc(dev)) {
|
||||
+ err = of_fsl_mc_iommu_init(to_fsl_mc_device(dev), master_np);
|
||||
} else {
|
||||
struct of_phandle_args iommu_spec;
|
||||
int idx = 0;
|
||||
--- a/drivers/of/irq.c
|
||||
+++ b/drivers/of/irq.c
|
||||
@@ -26,7 +26,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
-#include <linux/of_pci.h>
|
||||
+#include <linux/of_iommu.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
@@ -593,8 +593,8 @@ static u32 __of_msi_map_rid(struct devic
|
||||
* "msi-map" property.
|
||||
*/
|
||||
for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent)
|
||||
- if (!of_pci_map_rid(parent_dev->of_node, rid_in, "msi-map",
|
||||
- "msi-map-mask", np, &rid_out))
|
||||
+ if (!of_map_rid(parent_dev->of_node, rid_in, "msi-map",
|
||||
+ "msi-map-mask", np, &rid_out))
|
||||
break;
|
||||
return rid_out;
|
||||
}
|
||||
--- a/drivers/of/of_pci.c
|
||||
+++ b/drivers/of/of_pci.c
|
||||
@@ -281,104 +281,3 @@ parse_failed:
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
|
||||
#endif /* CONFIG_OF_ADDRESS */
|
||||
-
|
||||
-/**
|
||||
- * of_pci_map_rid - Translate a requester ID through a downstream mapping.
|
||||
- * @np: root complex device node.
|
||||
- * @rid: PCI requester ID to map.
|
||||
- * @map_name: property name of the map to use.
|
||||
- * @map_mask_name: optional property name of the mask to use.
|
||||
- * @target: optional pointer to a target device node.
|
||||
- * @id_out: optional pointer to receive the translated ID.
|
||||
- *
|
||||
- * Given a PCI requester ID, look up the appropriate implementation-defined
|
||||
- * platform ID and/or the target device which receives transactions on that
|
||||
- * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
|
||||
- * @id_out may be NULL if only the other is required. If @target points to
|
||||
- * a non-NULL device node pointer, only entries targeting that node will be
|
||||
- * matched; if it points to a NULL value, it will receive the device node of
|
||||
- * the first matching target phandle, with a reference held.
|
||||
- *
|
||||
- * Return: 0 on success or a standard error code on failure.
|
||||
- */
|
||||
-int of_pci_map_rid(struct device_node *np, u32 rid,
|
||||
- const char *map_name, const char *map_mask_name,
|
||||
- struct device_node **target, u32 *id_out)
|
||||
-{
|
||||
- u32 map_mask, masked_rid;
|
||||
- int map_len;
|
||||
- const __be32 *map = NULL;
|
||||
-
|
||||
- if (!np || !map_name || (!target && !id_out))
|
||||
- return -EINVAL;
|
||||
-
|
||||
- map = of_get_property(np, map_name, &map_len);
|
||||
- if (!map) {
|
||||
- if (target)
|
||||
- return -ENODEV;
|
||||
- /* Otherwise, no map implies no translation */
|
||||
- *id_out = rid;
|
||||
- return 0;
|
||||
- }
|
||||
-
|
||||
- if (!map_len || map_len % (4 * sizeof(*map))) {
|
||||
- pr_err("%pOF: Error: Bad %s length: %d\n", np,
|
||||
- map_name, map_len);
|
||||
- return -EINVAL;
|
||||
- }
|
||||
-
|
||||
- /* The default is to select all bits. */
|
||||
- map_mask = 0xffffffff;
|
||||
-
|
||||
- /*
|
||||
- * Can be overridden by "{iommu,msi}-map-mask" property.
|
||||
- * If of_property_read_u32() fails, the default is used.
|
||||
- */
|
||||
- if (map_mask_name)
|
||||
- of_property_read_u32(np, map_mask_name, &map_mask);
|
||||
-
|
||||
- masked_rid = map_mask & rid;
|
||||
- for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
|
||||
- struct device_node *phandle_node;
|
||||
- u32 rid_base = be32_to_cpup(map + 0);
|
||||
- u32 phandle = be32_to_cpup(map + 1);
|
||||
- u32 out_base = be32_to_cpup(map + 2);
|
||||
- u32 rid_len = be32_to_cpup(map + 3);
|
||||
-
|
||||
- if (rid_base & ~map_mask) {
|
||||
- pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
|
||||
- np, map_name, map_name,
|
||||
- map_mask, rid_base);
|
||||
- return -EFAULT;
|
||||
- }
|
||||
-
|
||||
- if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
|
||||
- continue;
|
||||
-
|
||||
- phandle_node = of_find_node_by_phandle(phandle);
|
||||
- if (!phandle_node)
|
||||
- return -ENODEV;
|
||||
-
|
||||
- if (target) {
|
||||
- if (*target)
|
||||
- of_node_put(phandle_node);
|
||||
- else
|
||||
- *target = phandle_node;
|
||||
-
|
||||
- if (*target != phandle_node)
|
||||
- continue;
|
||||
- }
|
||||
-
|
||||
- if (id_out)
|
||||
- *id_out = masked_rid - rid_base + out_base;
|
||||
-
|
||||
- pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
|
||||
- np, map_name, map_mask, rid_base, out_base,
|
||||
- rid_len, rid, *id_out);
|
||||
- return 0;
|
||||
- }
|
||||
-
|
||||
- pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
|
||||
- np, map_name, rid, target && *target ? *target : NULL);
|
||||
- return -EFAULT;
|
||||
-}
|
||||
--- a/include/linux/iommu.h
|
||||
+++ b/include/linux/iommu.h
|
||||
@@ -389,6 +389,8 @@ static inline size_t iommu_map_sg(struct
|
||||
extern struct iommu_group *pci_device_group(struct device *dev);
|
||||
/* Generic device grouping function */
|
||||
extern struct iommu_group *generic_device_group(struct device *dev);
|
||||
+/* FSL-MC device grouping function */
|
||||
+struct iommu_group *fsl_mc_device_group(struct device *dev);
|
||||
|
||||
/**
|
||||
* struct iommu_fwspec - per-device IOMMU instance data
|
||||
--- a/include/linux/of_iommu.h
|
||||
+++ b/include/linux/of_iommu.h
|
||||
@@ -15,6 +15,9 @@ extern int of_get_dma_window(struct devi
|
||||
extern const struct iommu_ops *of_iommu_configure(struct device *dev,
|
||||
struct device_node *master_np);
|
||||
|
||||
+int of_map_rid(struct device_node *np, u32 rid,
|
||||
+ const char *map_name, const char *map_mask_name,
|
||||
+ struct device_node **target, u32 *id_out);
|
||||
#else
|
||||
|
||||
static inline int of_get_dma_window(struct device_node *dn, const char *prefix,
|
||||
@@ -30,6 +33,13 @@ static inline const struct iommu_ops *of
|
||||
return NULL;
|
||||
}
|
||||
|
||||
+static inline int of_map_rid(struct device_node *np, u32 rid,
|
||||
+ const char *map_name, const char *map_mask_name,
|
||||
+ struct device_node **target, u32 *id_out)
|
||||
+{
|
||||
+ return -EINVAL;
|
||||
+}
|
||||
+
|
||||
#endif /* CONFIG_OF_IOMMU */
|
||||
|
||||
extern struct of_device_id __iommu_of_table;
|
||||
--- a/include/linux/of_pci.h
|
||||
+++ b/include/linux/of_pci.h
|
||||
@@ -19,9 +19,6 @@ int of_pci_parse_bus_range(struct device
|
||||
int of_get_pci_domain_nr(struct device_node *node);
|
||||
int of_pci_get_max_link_speed(struct device_node *node);
|
||||
void of_pci_check_probe_only(void);
|
||||
-int of_pci_map_rid(struct device_node *np, u32 rid,
|
||||
- const char *map_name, const char *map_mask_name,
|
||||
- struct device_node **target, u32 *id_out);
|
||||
#else
|
||||
static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
|
||||
{
|
||||
@@ -57,13 +54,6 @@ of_get_pci_domain_nr(struct device_node
|
||||
return -1;
|
||||
}
|
||||
|
||||
-static inline int of_pci_map_rid(struct device_node *np, u32 rid,
|
||||
- const char *map_name, const char *map_mask_name,
|
||||
- struct device_node **target, u32 *id_out)
|
||||
-{
|
||||
- return -EINVAL;
|
||||
-}
|
||||
-
|
||||
static inline int
|
||||
of_pci_get_max_link_speed(struct device_node *node)
|
||||
{
|
||||
@ -0,0 +1,52 @@
|
||||
From 558ca1294aa2bf7f29d55361d2f18c6dc534e1d6 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:28:33 +0800
|
||||
Subject: [PATCH 39/40] uart: support layerscape
|
||||
This is an integrated patch of uart for layerscape
|
||||
|
||||
Signed-off-by: Sriram Dash <Sriram.dash@nxp.com>
|
||||
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
drivers/tty/serial/fsl_lpuart.c | 15 +++++++++------
|
||||
1 file changed, 9 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/tty/serial/fsl_lpuart.c
|
||||
+++ b/drivers/tty/serial/fsl_lpuart.c
|
||||
@@ -236,6 +236,8 @@
|
||||
/* IMX lpuart has four extra unused regs located at the beginning */
|
||||
#define IMX_REG_OFF 0x10
|
||||
|
||||
+static DECLARE_BITMAP(linemap, UART_NR);
|
||||
+
|
||||
struct lpuart_port {
|
||||
struct uart_port port;
|
||||
struct clk *clk;
|
||||
@@ -2149,13 +2151,13 @@ static int lpuart_probe(struct platform_
|
||||
|
||||
ret = of_alias_get_id(np, "serial");
|
||||
if (ret < 0) {
|
||||
- dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
|
||||
- return ret;
|
||||
- }
|
||||
- if (ret >= ARRAY_SIZE(lpuart_ports)) {
|
||||
- dev_err(&pdev->dev, "serial%d out of range\n", ret);
|
||||
- return -EINVAL;
|
||||
+ ret = find_first_zero_bit(linemap, UART_NR);
|
||||
+ if (ret >= UART_NR) {
|
||||
+ dev_err(&pdev->dev, "port line is full, add device failed\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
+ set_bit(ret, linemap);
|
||||
sport->port.line = ret;
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
@@ -2246,6 +2248,7 @@ static int lpuart_remove(struct platform
|
||||
struct lpuart_port *sport = platform_get_drvdata(pdev);
|
||||
|
||||
uart_remove_one_port(&lpuart_reg, &sport->port);
|
||||
+ clear_bit(sport->port.line, linemap);
|
||||
|
||||
clk_disable_unprepare(sport->clk);
|
||||
|
||||
@ -0,0 +1,718 @@
|
||||
From aded309f403c4202b9c6f61ea6a635e0c736eb77 Mon Sep 17 00:00:00 2001
|
||||
From: Biwen Li <biwen.li@nxp.com>
|
||||
Date: Tue, 30 Oct 2018 18:27:07 +0800
|
||||
Subject: [PATCH 40/40] pm: support layerscape
|
||||
This is an integrated patch of pm for layerscape
|
||||
|
||||
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
|
||||
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
|
||||
Signed-off-by: Li Yang <leoyang.li@nxp.com>
|
||||
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
|
||||
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
||||
Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
|
||||
Signed-off-by: Biwen Li <biwen.li@nxp.com>
|
||||
---
|
||||
.../devicetree/bindings/powerpc/fsl/pmc.txt | 59 ++--
|
||||
drivers/firmware/psci.c | 16 +-
|
||||
drivers/soc/fsl/rcpm.c | 158 ++++++++++
|
||||
drivers/soc/fsl/sleep_fsm.c | 279 ++++++++++++++++++
|
||||
drivers/soc/fsl/sleep_fsm.h | 130 ++++++++
|
||||
5 files changed, 615 insertions(+), 27 deletions(-)
|
||||
create mode 100644 drivers/soc/fsl/rcpm.c
|
||||
create mode 100644 drivers/soc/fsl/sleep_fsm.c
|
||||
create mode 100644 drivers/soc/fsl/sleep_fsm.h
|
||||
|
||||
--- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
|
||||
+++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
|
||||
@@ -9,15 +9,20 @@ Properties:
|
||||
|
||||
"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
|
||||
compatible. "fsl,mpc8536-pmc" should also be listed for any chip
|
||||
- whose PMC is compatible, and implies deep-sleep capability.
|
||||
+ whose PMC is compatible, and implies deep-sleep capability and
|
||||
+ wake on user defined packet(wakeup on ARP).
|
||||
+
|
||||
+ "fsl,p1022-pmc" should be listed for any chip whose PMC is
|
||||
+ compatible, and implies lossless Ethernet capability during sleep.
|
||||
|
||||
"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
|
||||
compatible; all statements below that apply to "fsl,mpc8548-pmc" also
|
||||
apply to "fsl,mpc8641d-pmc".
|
||||
|
||||
Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
|
||||
- bit assignments are indicated via the sleep specifier in each device's
|
||||
- sleep property.
|
||||
+ bit assignments are indicated via the clock nodes. Device which has a
|
||||
+ controllable clock source should have a "fsl,pmc-handle" property pointing
|
||||
+ to the clock node.
|
||||
|
||||
- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
|
||||
is the PMC block, and the second resource is the Clock Configuration
|
||||
@@ -33,31 +38,35 @@ Properties:
|
||||
this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
|
||||
a wakeup source from deep sleep.
|
||||
|
||||
-Sleep specifiers:
|
||||
-
|
||||
- fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit
|
||||
- that is set in the cell, the corresponding bit in SCCR will be saved
|
||||
- and cleared on suspend, and restored on resume. This sleep controller
|
||||
- supports disabling and resuming devices at any time.
|
||||
-
|
||||
- fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
|
||||
- which will be ORed into PMCDR upon suspend, and cleared from PMCDR
|
||||
- upon resume. The first two cells are as described for fsl,mpc8578-pmc.
|
||||
- This sleep controller only supports disabling devices during system
|
||||
- sleep, or permanently.
|
||||
-
|
||||
- fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
|
||||
- first of which will be ORed into DEVDISR (and the second into
|
||||
- DEVDISR2, if present -- this cell should be zero or absent if the
|
||||
- hardware does not have DEVDISR2) upon a request for permanent device
|
||||
- disabling. This sleep controller does not support configuring devices
|
||||
- to disable during system sleep (unless supported by another compatible
|
||||
- match), or dynamically.
|
||||
+Clock nodes:
|
||||
+The clock nodes are to describe the masks in PM controller registers for each
|
||||
+soc clock.
|
||||
+- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
|
||||
+ ORed into PMCDR before suspend if the device using this clock is the wake-up
|
||||
+ source and need to be running during low power mode; clear the mask if
|
||||
+ otherwise.
|
||||
+
|
||||
+- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
|
||||
+ bit specified by the mask in SCCR will be saved and cleared on suspend, and
|
||||
+ restored on resume.
|
||||
+
|
||||
+- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
|
||||
+ DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR
|
||||
+ or DEVDISR2 when the clock should be permenently disabled.
|
||||
|
||||
Example:
|
||||
|
||||
- power@b00 {
|
||||
- compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
|
||||
- reg = <0xb00 0x100 0xa00 0x100>;
|
||||
- interrupts = <80 8>;
|
||||
+ power@e0070 {
|
||||
+ compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
|
||||
+ reg = <0xe0070 0x20>;
|
||||
+
|
||||
+ etsec1_clk: soc-clk@24 {
|
||||
+ fsl,pmcdr-mask = <0x00000080>;
|
||||
+ };
|
||||
+ etsec2_clk: soc-clk@25 {
|
||||
+ fsl,pmcdr-mask = <0x00000040>;
|
||||
+ };
|
||||
+ etsec3_clk: soc-clk@26 {
|
||||
+ fsl,pmcdr-mask = <0x00000020>;
|
||||
+ };
|
||||
};
|
||||
--- a/drivers/firmware/psci.c
|
||||
+++ b/drivers/firmware/psci.c
|
||||
@@ -437,8 +437,18 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
|
||||
|
||||
static int psci_system_suspend(unsigned long unused)
|
||||
{
|
||||
- return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
|
||||
- __pa_symbol(cpu_resume), 0, 0);
|
||||
+ u32 state;
|
||||
+ u32 ver = psci_get_version();
|
||||
+
|
||||
+ if (PSCI_VERSION_MAJOR(ver) >= 1) {
|
||||
+ return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
|
||||
+ virt_to_phys(cpu_resume), 0, 0);
|
||||
+ } else {
|
||||
+ state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
|
||||
+ (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
|
||||
+
|
||||
+ return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
|
||||
+ }
|
||||
}
|
||||
|
||||
static int psci_system_suspend_enter(suspend_state_t state)
|
||||
@@ -562,6 +572,8 @@ static void __init psci_0_2_set_function
|
||||
arm_pm_restart = psci_sys_reset;
|
||||
|
||||
pm_power_off = psci_sys_poweroff;
|
||||
+
|
||||
+ suspend_set_ops(&psci_suspend_ops);
|
||||
}
|
||||
|
||||
/*
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/rcpm.c
|
||||
@@ -0,0 +1,158 @@
|
||||
+/*
|
||||
+ * Run Control and Power Management (RCPM) driver
|
||||
+ *
|
||||
+ * Copyright 2016 NXP
|
||||
+ *
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
+ * the Free Software Foundation; either version 2 of the License, or
|
||||
+ * (at your option) any later version.
|
||||
+ *
|
||||
+ * This program is distributed in the hope that it will be useful,
|
||||
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
+ * GNU General Public License for more details.
|
||||
+ *
|
||||
+ */
|
||||
+#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/of_platform.h>
|
||||
+#include <linux/of_address.h>
|
||||
+#include <linux/suspend.h>
|
||||
+
|
||||
+/* RCPM register offset */
|
||||
+#define RCPM_IPPDEXPCR0 0x140
|
||||
+
|
||||
+#define RCPM_WAKEUP_CELL_SIZE 2
|
||||
+
|
||||
+struct rcpm_config {
|
||||
+ int ipp_num;
|
||||
+ int ippdexpcr_offset;
|
||||
+ u32 ippdexpcr[2];
|
||||
+ void *rcpm_reg_base;
|
||||
+};
|
||||
+
|
||||
+static struct rcpm_config *rcpm;
|
||||
+
|
||||
+static inline void rcpm_reg_write(u32 offset, u32 value)
|
||||
+{
|
||||
+ iowrite32be(value, rcpm->rcpm_reg_base + offset);
|
||||
+}
|
||||
+
|
||||
+static inline u32 rcpm_reg_read(u32 offset)
|
||||
+{
|
||||
+ return ioread32be(rcpm->rcpm_reg_base + offset);
|
||||
+}
|
||||
+
|
||||
+static void rcpm_wakeup_fixup(struct device *dev, void *data)
|
||||
+{
|
||||
+ struct device_node *node = dev ? dev->of_node : NULL;
|
||||
+ u32 value[RCPM_WAKEUP_CELL_SIZE];
|
||||
+ int ret, i;
|
||||
+
|
||||
+ if (!dev || !node || !device_may_wakeup(dev))
|
||||
+ return;
|
||||
+
|
||||
+ /*
|
||||
+ * Get the values in the "rcpm-wakeup" property.
|
||||
+ * Three values are:
|
||||
+ * The first is a pointer to the RCPM node.
|
||||
+ * The second is the value of the ippdexpcr0 register.
|
||||
+ * The third is the value of the ippdexpcr1 register.
|
||||
+ */
|
||||
+ ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
|
||||
+ value, RCPM_WAKEUP_CELL_SIZE);
|
||||
+ if (ret)
|
||||
+ return;
|
||||
+
|
||||
+ pr_debug("wakeup source: the device %s\n", node->full_name);
|
||||
+
|
||||
+ for (i = 0; i < rcpm->ipp_num; i++)
|
||||
+ rcpm->ippdexpcr[i] |= value[i + 1];
|
||||
+}
|
||||
+
|
||||
+static int rcpm_suspend_prepare(void)
|
||||
+{
|
||||
+ int i;
|
||||
+ u32 val;
|
||||
+
|
||||
+ BUG_ON(!rcpm);
|
||||
+
|
||||
+ for (i = 0; i < rcpm->ipp_num; i++)
|
||||
+ rcpm->ippdexpcr[i] = 0;
|
||||
+
|
||||
+ dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
|
||||
+
|
||||
+ for (i = 0; i < rcpm->ipp_num; i++) {
|
||||
+ if (rcpm->ippdexpcr[i]) {
|
||||
+ val = rcpm_reg_read(rcpm->ippdexpcr_offset + 4 * i);
|
||||
+ rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
|
||||
+ val | rcpm->ippdexpcr[i]);
|
||||
+ pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rcpm_suspend_notifier_call(struct notifier_block *bl,
|
||||
+ unsigned long state,
|
||||
+ void *unused)
|
||||
+{
|
||||
+ switch (state) {
|
||||
+ case PM_SUSPEND_PREPARE:
|
||||
+ rcpm_suspend_prepare();
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static struct rcpm_config rcpm_default_config = {
|
||||
+ .ipp_num = 1,
|
||||
+ .ippdexpcr_offset = RCPM_IPPDEXPCR0,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id rcpm_matches[] = {
|
||||
+ {
|
||||
+ .compatible = "fsl,qoriq-rcpm-2.1",
|
||||
+ .data = &rcpm_default_config,
|
||||
+ },
|
||||
+ {}
|
||||
+};
|
||||
+
|
||||
+static struct notifier_block rcpm_suspend_notifier = {
|
||||
+ .notifier_call = rcpm_suspend_notifier_call,
|
||||
+};
|
||||
+
|
||||
+static int __init layerscape_rcpm_init(void)
|
||||
+{
|
||||
+ const struct of_device_id *match;
|
||||
+ struct device_node *np;
|
||||
+
|
||||
+ np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
|
||||
+ if (!np) {
|
||||
+ pr_err("Can't find the RCPM node.\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (match->data)
|
||||
+ rcpm = (struct rcpm_config *)match->data;
|
||||
+ else
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ rcpm->rcpm_reg_base = of_iomap(np, 0);
|
||||
+ of_node_put(np);
|
||||
+ if (!rcpm->rcpm_reg_base)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ register_pm_notifier(&rcpm_suspend_notifier);
|
||||
+
|
||||
+ pr_info("The RCPM driver initialized.\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+subsys_initcall(layerscape_rcpm_init);
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/sleep_fsm.c
|
||||
@@ -0,0 +1,279 @@
|
||||
+/*
|
||||
+ * deep sleep FSM (finite-state machine) configuration
|
||||
+ *
|
||||
+ * Copyright 2018 NXP
|
||||
+ *
|
||||
+ * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
|
||||
+ * Chenhui Zhao <chenhui.zhao@freescale.com>
|
||||
+ *
|
||||
+ * Redistribution and use in source and binary forms, with or without
|
||||
+ * modification, are permitted provided that the following conditions are met:
|
||||
+ * * Redistributions of source code must retain the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer.
|
||||
+ * * Redistributions in binary form must reproduce the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer in the
|
||||
+ * documentation and/or other materials provided with the distribution.
|
||||
+ * * Neither the name of the above-listed copyright holders nor the
|
||||
+ * names of any contributors may be used to endorse or promote products
|
||||
+ * derived from this software without specific prior written permission.
|
||||
+ *
|
||||
+ * ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
+ * GNU General Public License ("GPL") as published by the Free Software
|
||||
+ * Foundation, either version 2 of that License or (at your option) any
|
||||
+ * later version.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
|
||||
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
+ * POSSIBILITY OF SUCH DAMAGE.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/types.h>
|
||||
+
|
||||
+#include "sleep_fsm.h"
|
||||
+/*
|
||||
+ * These values are from chip's reference manual. For example,
|
||||
+ * the values for T1040 can be found in "8.4.3.8 Programming
|
||||
+ * supporting deep sleep mode" of Chapter 8 "Run Control and
|
||||
+ * Power Management (RCPM)".
|
||||
+ * The default value can be applied to T104x, LS1021.
|
||||
+ */
|
||||
+struct fsm_reg_vals epu_default_val[] = {
|
||||
+ /* EPGCR (Event Processor Global Control Register) */
|
||||
+ {EPGCR, 0},
|
||||
+ /* EPECR (Event Processor Event Control Registers) */
|
||||
+ {EPECR0 + EPECR_STRIDE * 0, 0},
|
||||
+ {EPECR0 + EPECR_STRIDE * 1, 0},
|
||||
+ {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
|
||||
+ {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
|
||||
+ {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
|
||||
+ {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
|
||||
+ /*
|
||||
+ * EPEVTCR (Event Processor EVT Pin Control Registers)
|
||||
+ * SCU8 triger EVT2, and SCU11 triger EVT9
|
||||
+ */
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
|
||||
+ {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
|
||||
+ /* EPCMPR (Event Processor Counter Compare Registers) */
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
|
||||
+ {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
|
||||
+ /* EPCCR (Event Processor Counter Control Registers) */
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 0, 0},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 1, 0},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 3, 0},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 6, 0},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 7, 0},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 13, 0},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
|
||||
+ {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
|
||||
+ /* EPSMCR (Event Processor SCU Mux Control Registers) */
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
|
||||
+ {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
|
||||
+ /* EPACR (Event Processor Action Control Registers) */
|
||||
+ {EPACR0 + EPACR_STRIDE * 0, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 1, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 2, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
|
||||
+ {EPACR0 + EPACR_STRIDE * 4, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
|
||||
+ {EPACR0 + EPACR_STRIDE * 6, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 7, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 8, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
|
||||
+ {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
|
||||
+ {EPACR0 + EPACR_STRIDE * 11, 0},
|
||||
+ {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
|
||||
+ {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
|
||||
+ {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
|
||||
+ {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
|
||||
+ /* EPIMCR (Event Processor Input Mux Control Registers) */
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
|
||||
+ {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
|
||||
+ /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
|
||||
+ {EPXTRIGCR, 0x0000FFDF},
|
||||
+ /* end */
|
||||
+ {FSM_END_FLAG, 0},
|
||||
+};
|
||||
+
|
||||
+struct fsm_reg_vals npc_default_val[] = {
|
||||
+ /* NPC triggered Memory-Mapped Access Registers */
|
||||
+ {NCR, 0x80000000},
|
||||
+ {MCCR1, 0},
|
||||
+ {MCSR1, 0},
|
||||
+ {MMAR1LO, 0},
|
||||
+ {MMAR1HI, 0},
|
||||
+ {MMDR1, 0},
|
||||
+ {MCSR2, 0},
|
||||
+ {MMAR2LO, 0},
|
||||
+ {MMAR2HI, 0},
|
||||
+ {MMDR2, 0},
|
||||
+ {MCSR3, 0x80000000},
|
||||
+ {MMAR3LO, 0x000E2130},
|
||||
+ {MMAR3HI, 0x00030000},
|
||||
+ {MMDR3, 0x00020000},
|
||||
+ /* end */
|
||||
+ {FSM_END_FLAG, 0},
|
||||
+};
|
||||
+
|
||||
+/**
|
||||
+ * fsl_fsm_setup - Configure EPU's FSM registers
|
||||
+ * @base: the base address of registers
|
||||
+ * @val: Pointer to address-value pairs for FSM registers
|
||||
+ */
|
||||
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
|
||||
+{
|
||||
+ struct fsm_reg_vals *data = val;
|
||||
+
|
||||
+ WARN_ON(!base || !data);
|
||||
+ while (data->offset != FSM_END_FLAG) {
|
||||
+ iowrite32be(data->value, base + data->offset);
|
||||
+ data++;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+void fsl_epu_setup_default(void __iomem *epu_base)
|
||||
+{
|
||||
+ fsl_fsm_setup(epu_base, epu_default_val);
|
||||
+}
|
||||
+
|
||||
+void fsl_npc_setup_default(void __iomem *npc_base)
|
||||
+{
|
||||
+ fsl_fsm_setup(npc_base, npc_default_val);
|
||||
+}
|
||||
+
|
||||
+void fsl_epu_clean_default(void __iomem *epu_base)
|
||||
+{
|
||||
+ u32 offset;
|
||||
+
|
||||
+ /* follow the exact sequence to clear the registers */
|
||||
+ /* Clear EPACRn */
|
||||
+ for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPEVTCRn */
|
||||
+ for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPGCR */
|
||||
+ iowrite32be(0, epu_base + EPGCR);
|
||||
+
|
||||
+ /* Clear EPSMCRn */
|
||||
+ for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPCCRn */
|
||||
+ for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPCMPRn */
|
||||
+ for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPCTRn */
|
||||
+ for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPIMCRn */
|
||||
+ for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+
|
||||
+ /* Clear EPXTRIGCRn */
|
||||
+ iowrite32be(0, epu_base + EPXTRIGCR);
|
||||
+
|
||||
+ /* Clear EPECRn */
|
||||
+ for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
|
||||
+ iowrite32be(0, epu_base + offset);
|
||||
+}
|
||||
--- /dev/null
|
||||
+++ b/drivers/soc/fsl/sleep_fsm.h
|
||||
@@ -0,0 +1,130 @@
|
||||
+/*
|
||||
+ * deep sleep FSM (finite-state machine) configuration
|
||||
+ *
|
||||
+ * Copyright 2018 NXP
|
||||
+ *
|
||||
+ * Redistribution and use in source and binary forms, with or without
|
||||
+ * modification, are permitted provided that the following conditions are met:
|
||||
+ * * Redistributions of source code must retain the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer.
|
||||
+ * * Redistributions in binary form must reproduce the above copyright
|
||||
+ * notice, this list of conditions and the following disclaimer in the
|
||||
+ * documentation and/or other materials provided with the distribution.
|
||||
+ * * Neither the name of the above-listed copyright holders nor the
|
||||
+ * names of any contributors may be used to endorse or promote products
|
||||
+ * derived from this software without specific prior written permission.
|
||||
+ *
|
||||
+ *
|
||||
+ * ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
+ * GNU General Public License ("GPL") as published by the Free Software
|
||||
+ * Foundation, either version 2 of that License or (at your option) any
|
||||
+ * later version.
|
||||
+ *
|
||||
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
|
||||
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
+ * POSSIBILITY OF SUCH DAMAGE.
|
||||
+ */
|
||||
+
|
||||
+#ifndef _FSL_SLEEP_FSM_H
|
||||
+#define _FSL_SLEEP_FSM_H
|
||||
+
|
||||
+#define FSL_STRIDE_4B 4
|
||||
+#define FSL_STRIDE_8B 8
|
||||
+
|
||||
+/* End flag */
|
||||
+#define FSM_END_FLAG 0xFFFFFFFFUL
|
||||
+
|
||||
+/* Block offsets */
|
||||
+#define RCPM_BLOCK_OFFSET 0x00022000
|
||||
+#define EPU_BLOCK_OFFSET 0x00000000
|
||||
+#define NPC_BLOCK_OFFSET 0x00001000
|
||||
+
|
||||
+/* EPGCR (Event Processor Global Control Register) */
|
||||
+#define EPGCR 0x000
|
||||
+
|
||||
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
|
||||
+#define EPEVTCR0 0x050
|
||||
+#define EPEVTCR9 0x074
|
||||
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
|
||||
+#define EPXTRIGCR 0x090
|
||||
+
|
||||
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
|
||||
+#define EPIMCR0 0x100
|
||||
+#define EPIMCR31 0x17C
|
||||
+#define EPIMCR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
|
||||
+#define EPSMCR0 0x200
|
||||
+#define EPSMCR15 0x278
|
||||
+#define EPSMCR_STRIDE FSL_STRIDE_8B
|
||||
+
|
||||
+/* EPECR0-15 (Event Processor Event Control Registers) */
|
||||
+#define EPECR0 0x300
|
||||
+#define EPECR15 0x33C
|
||||
+#define EPECR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* EPACR0-15 (Event Processor Action Control Registers) */
|
||||
+#define EPACR0 0x400
|
||||
+#define EPACR15 0x43C
|
||||
+#define EPACR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* EPCCRi0-15 (Event Processor Counter Control Registers) */
|
||||
+#define EPCCR0 0x800
|
||||
+#define EPCCR15 0x83C
|
||||
+#define EPCCR31 0x87C
|
||||
+#define EPCCR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
|
||||
+#define EPCMPR0 0x900
|
||||
+#define EPCMPR15 0x93C
|
||||
+#define EPCMPR31 0x97C
|
||||
+#define EPCMPR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* EPCTR0-31 (Event Processor Counter Register) */
|
||||
+#define EPCTR0 0xA00
|
||||
+#define EPCTR31 0xA7C
|
||||
+#define EPCTR_STRIDE FSL_STRIDE_4B
|
||||
+
|
||||
+/* NPC triggered Memory-Mapped Access Registers */
|
||||
+#define NCR 0x000
|
||||
+#define MCCR1 0x0CC
|
||||
+#define MCSR1 0x0D0
|
||||
+#define MMAR1LO 0x0D4
|
||||
+#define MMAR1HI 0x0D8
|
||||
+#define MMDR1 0x0DC
|
||||
+#define MCSR2 0x0E0
|
||||
+#define MMAR2LO 0x0E4
|
||||
+#define MMAR2HI 0x0E8
|
||||
+#define MMDR2 0x0EC
|
||||
+#define MCSR3 0x0F0
|
||||
+#define MMAR3LO 0x0F4
|
||||
+#define MMAR3HI 0x0F8
|
||||
+#define MMDR3 0x0FC
|
||||
+
|
||||
+/* RCPM Core State Action Control Register 0 */
|
||||
+#define CSTTACR0 0xB00
|
||||
+
|
||||
+/* RCPM Core Group 1 Configuration Register 0 */
|
||||
+#define CG1CR0 0x31C
|
||||
+
|
||||
+struct fsm_reg_vals {
|
||||
+ u32 offset;
|
||||
+ u32 value;
|
||||
+};
|
||||
+
|
||||
+void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
|
||||
+void fsl_epu_setup_default(void __iomem *epu_base);
|
||||
+void fsl_npc_setup_default(void __iomem *npc_base);
|
||||
+void fsl_epu_clean_default(void __iomem *epu_base);
|
||||
+
|
||||
+#endif /* _FSL_SLEEP_FSM_H */
|
||||
@ -0,0 +1,23 @@
|
||||
From bb7412794db9b48dc4cc041c75d380e512dfff2a Mon Sep 17 00:00:00 2001
|
||||
From: Mathew McBride <matt@traverse.com.au>
|
||||
Date: Tue, 20 Nov 2018 14:36:54 +0800
|
||||
Subject: [PATCH] mmc: sdhci-of-esdhc: add voltage switch support for ls1043a
|
||||
|
||||
Added voltage switch support for ls1043a.
|
||||
|
||||
Signed-off-by: Mathew McBride <matt@traverse.com.au>
|
||||
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
||||
---
|
||||
drivers/mmc/host/sdhci-of-esdhc.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
|
||||
@@ -650,6 +650,7 @@ static void esdhc_reset(struct sdhci_hos
|
||||
static const struct of_device_id scfg_device_ids[] = {
|
||||
{ .compatible = "fsl,t1040-scfg", },
|
||||
{ .compatible = "fsl,ls1012a-scfg", },
|
||||
+ { .compatible = "fsl,ls1043a-scfg", },
|
||||
{ .compatible = "fsl,ls1046a-scfg", },
|
||||
{}
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user