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ramips/mt7621: drop the timer recalibration patch

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We've been carrying this patch for many years [1], in order to fix a timer
calibration issue on MT7621. Turns out, after retesting with a recent kernel
(Linux 5.10), the system works perfectly fine without it (no rcu_sched stalls
or inconsistent BogoMIPS values across CPUs).

Manually refreshed:
322-mt7621-fix-cpu-clk-add-clkdev.patch
323-mt7621-memory-detect.patch

[1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=6f4a903533361a2906a4d94ac6f597cd9c6c47bc

Suggested-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
Tested-by: Donald Hoskins <grommish@gmail.com>
Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
Signed-off-by: maurerr <mariusd84@gmail.com>
This commit is contained in:
Rui Salvaterra 2021-03-30 23:59:49 +01:00 committed by maurerr
parent bb733bb387
commit 04d9212065
3 changed files with 10 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

87
target/linux/ramips/patches-5.10/321-mt7621-timer.patch
View File

@ -1,87 +0,0 @@
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -9,6 +9,7 @@
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
+#include <linux/jiffies.h>
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
@@ -16,6 +17,7 @@
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
#include <asm/mips-boards/launch.h>
+#include <asm/delay.h>
#include <pinmux.h>
@@ -161,6 +163,58 @@ bool plat_cpu_core_present(int core)
return true;
}
+#define LPS_PREC 8
+/*
+* Re-calibration lpj(loop-per-jiffy).
+* (derived from kernel/calibrate.c)
+*/
+static int udelay_recal(void)
+{
+ unsigned int i, lpj = 0;
+ unsigned long ticks, loopbit;
+ int lps_precision = LPS_PREC;
+
+ lpj = (1<<12);
+
+ while ((lpj <<= 1) != 0) {
+ /* wait for "start of" clock tick */
+ ticks = jiffies;
+ while (ticks == jiffies)
+ /* nothing */;
+
+ /* Go .. */
+ ticks = jiffies;
+ __delay(lpj);
+ ticks = jiffies - ticks;
+ if (ticks)
+ break;
+ }
+
+ /*
+ * Do a binary approximation to get lpj set to
+ * equal one clock (up to lps_precision bits)
+ */
+ lpj >>= 1;
+ loopbit = lpj;
+ while (lps_precision-- && (loopbit >>= 1)) {
+ lpj |= loopbit;
+ ticks = jiffies;
+ while (ticks == jiffies)
+ /* nothing */;
+ ticks = jiffies;
+ __delay(lpj);
+ if (jiffies != ticks) /* longer than 1 tick */
+ lpj &= ~loopbit;
+ }
+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
+
+ for(i=0; i< NR_CPUS; i++)
+ cpu_data[i].udelay_val = lpj;
+
+ return 0;
+}
+device_initcall(udelay_recal);
+
void prom_soc_init(struct ralink_soc_info *soc_info)
{
void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -62,6 +62,7 @@ choice
select CLKSRC_MIPS_GIC
select HAVE_PCI if PCI_MT7621
select SOC_BUS
+ select GENERIC_CLOCKEVENTS_BROADCAST
endchoice
choice

10
target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch
View File

@ -36,10 +36,10 @@
#define MT7621_DDR2_SIZE_MAX 256
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -10,6 +10,10 @@
@@ -9,6 +9,10 @@
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <linux/jiffies.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
@ -47,15 +47,15 @@
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
@@ -18,6 +22,7 @@
@@ -16,6 +20,7 @@
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/mt7621.h>
#include <asm/mips-boards/launch.h>
#include <asm/delay.h>
+#include <asm/time.h>
#include <pinmux.h>
@@ -108,11 +113,89 @@ static struct rt2880_pmx_group mt7621_pi
@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi
{ 0 }
};

10
target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch
View File

@ -44,10 +44,10 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
#define MT7621_CHIP_NAME1 0x20203132
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -10,11 +10,13 @@
@@ -9,11 +9,13 @@
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
#include <linux/jiffies.h>
+#include <linux/memblock.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
#include <asm/mipsregs.h>
#include <asm/smp-ops.h>
#include <asm/mips-cps.h>
@@ -57,6 +59,8 @@
@@ -55,6 +57,8 @@
#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
#define MT7621_GPIO_MODE_SDHCI_GPIO 1
@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
static struct rt2880_pmx_func uart3_grp[] = {
@@ -141,6 +145,26 @@ static struct clk *__init mt7621_add_sys
@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys
return clk;
}
@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
void __init ralink_clk_init(void)
{
u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
@@ -346,10 +370,7 @@ void prom_soc_init(struct ralink_soc_inf
@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf
(rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
(rev & CHIP_REV_ECO_MASK));