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uboot-rockchip: add Orange Pi R1 Plus support
Add support for the Xunlong Orange Pi R1 Plus. Manually generated of-platdata files to avoid swig dependency. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
2d5f3b3c4c
commit
043f8a4f5e
@ -45,6 +45,13 @@ define U-Boot/nanopi-r2s-rk3328
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friendlyarm_nanopi-r2s
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endef
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define U-Boot/orangepi-r1-plus-rk3328
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$(U-Boot/rk3328/Default)
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NAME:=Orange Pi R1 Plus
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BUILD_DEVICES:= \
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xunlong_orangepi-r1-plus
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endef
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define U-Boot/roc-cc-rk3328
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$(U-Boot/rk3328/Default)
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NAME:=ROC-RK3328-CC
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@ -87,6 +94,7 @@ UBOOT_TARGETS := \
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rockpro64-rk3399 \
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nanopi-r2c-rk3328 \
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nanopi-r2s-rk3328 \
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orangepi-r1-plus-rk3328 \
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roc-cc-rk3328
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UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
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@ -0,0 +1,564 @@
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From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001
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From: Tianling Shen <cnsztl@gmail.com>
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Date: Sat, 20 May 2023 18:50:38 +0800
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Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
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Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
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This device is similar to the NanoPi R2S, and has a 16MB
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SPI NOR (mx25l12805d). The reset button is changed to
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directly reset the power supply, another detail is that
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both network ports have independent MAC addresses.
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The device tree and description are taken from kernel v6.3-rc1.
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
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---
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arch/arm/dts/Makefile | 1 +
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.../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 46 +++
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arch/arm/dts/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
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board/rockchip/evb_rk3328/MAINTAINERS | 6 +
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configs/orangepi-r1-plus-rk3328_defconfig | 114 ++++++
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5 files changed, 540 insertions(+)
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create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts
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create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
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rk3328-evb.dtb \
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rk3328-nanopi-r2c.dtb \
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rk3328-nanopi-r2s.dtb \
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+ rk3328-orangepi-r1-plus.dtb \
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rk3328-roc-cc.dtb \
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rk3328-rock64.dtb \
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rk3328-rock-pi-e.dtb
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
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@@ -0,0 +1,46 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+/*
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+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
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+ * (C) Copyright 2020 David Bauer
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+ */
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+
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+#include "rk3328-u-boot.dtsi"
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+#include "rk3328-sdram-ddr4-666.dtsi"
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+/ {
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+ chosen {
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+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
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+ };
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+};
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+
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+&gpio0 {
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+ u-boot,dm-spl;
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+};
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+
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+&pinctrl {
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+ u-boot,dm-spl;
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+};
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+
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+&sdmmc0m1_gpio {
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+ u-boot,dm-spl;
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+};
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+
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+&pcfg_pull_up_4ma {
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+ u-boot,dm-spl;
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+};
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+
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+/* Need this and all the pinctrl/gpio stuff above to set pinmux */
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+&vcc_sd {
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+ u-boot,dm-spl;
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+};
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+
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+&gmac2io {
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+ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 10000 50000>;
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+};
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+
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+&spi0 {
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+ spi_flash: spiflash@0 {
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+ u-boot,dm-pre-reloc;
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
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@@ -0,0 +1,359 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Based on rk3328-nanopi-r2s.dts, which is:
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+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+#include "rk3328.dtsi"
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+
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+/ {
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+ model = "Xunlong Orange Pi R1 Plus";
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+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
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+
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+ aliases {
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+ mmc0 = &sdmmc;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ gmac_clk: gmac-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
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+ pinctrl-names = "default";
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+
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+ led-0 {
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+ function = LED_FUNCTION_LAN;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-1 {
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_RED>;
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+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "heartbeat";
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+ };
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+
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+ led-2 {
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+ function = LED_FUNCTION_WAN;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ vcc_sd: sdmmc-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&sdmmc0m1_gpio>;
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+ pinctrl-names = "default";
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+ regulator-name = "vcc_sd";
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+ regulator-boot-on;
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+ vin-supply = <&vcc_io>;
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+ };
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+
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+ vcc_sys: vcc-sys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vdd_5v_lan: vdd-5v-lan-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
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+ pinctrl-0 = <&lan_vdd_pin>;
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+ pinctrl-names = "default";
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+ regulator-name = "vdd_5v_lan";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vcc_sys>;
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+ };
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&display_subsystem {
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+ status = "disabled";
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+};
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+
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+&gmac2io {
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+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
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+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
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+ clock_in_out = "input";
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+ phy-handle = <&rtl8211e>;
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+ phy-mode = "rgmii";
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+ phy-supply = <&vcc_io>;
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+ pinctrl-0 = <&rgmiim1_pins>;
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+ pinctrl-names = "default";
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+ snps,aal;
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+ rx_delay = <0x18>;
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+ tx_delay = <0x24>;
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+ status = "okay";
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+
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+ mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ rtl8211e: ethernet-phy@1 {
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+ reg = <1>;
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <10000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "okay";
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+
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+ rk805: pmic@18 {
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+ compatible = "rockchip,rk805";
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+ reg = <0x18>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk805-clkout2";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ pinctrl-0 = <&pmic_int_l>;
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+ pinctrl-names = "default";
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vcc_sys>;
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+ vcc2-supply = <&vcc_sys>;
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+ vcc3-supply = <&vcc_sys>;
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+ vcc4-supply = <&vcc_sys>;
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+ vcc5-supply = <&vcc_io>;
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+ vcc6-supply = <&vcc_sys>;
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+
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+ regulators {
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+ vdd_log: DCDC_REG1 {
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+ regulator-name = "vdd_log";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vdd_arm: DCDC_REG2 {
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+ regulator-name = "vdd_arm";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <950000>;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_io: DCDC_REG4 {
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+ regulator-name = "vcc_io";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <3300000>;
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+ };
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+ };
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+
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+ vcc_18: LDO_REG1 {
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+ regulator-name = "vcc_18";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc18_emmc: LDO_REG2 {
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+ regulator-name = "vcc18_emmc";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vdd_10: LDO_REG3 {
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+ regulator-name = "vdd_10";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&io_domains {
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+ pmuio-supply = <&vcc_io>;
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+ vccio1-supply = <&vcc_io>;
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+ vccio2-supply = <&vcc18_emmc>;
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+ vccio3-supply = <&vcc_io>;
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+ vccio4-supply = <&vcc_io>;
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+ vccio5-supply = <&vcc_io>;
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+ vccio6-supply = <&vcc_io>;
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ gmac2io {
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+ eth_phy_reset_pin: eth-phy-reset-pin {
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+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
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+ };
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+ };
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+
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+ leds {
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+ lan_led_pin: lan-led-pin {
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+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
|
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+
|
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+ sys_led_pin: sys-led-pin {
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+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
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+ };
|
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+
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+ wan_led_pin: wan-led-pin {
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+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
|
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+ };
|
||||
+
|
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+ lan {
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+ lan_vdd_pin: lan-vdd-pin {
|
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+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pmic {
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+ pmic_int_l: pmic-int-l {
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+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
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+ };
|
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+ };
|
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+};
|
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+
|
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+&pwm2 {
|
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+ status = "okay";
|
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+};
|
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+
|
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+&sdmmc {
|
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+ bus-width = <4>;
|
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+ cap-sd-highspeed;
|
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+ disable-wp;
|
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+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
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+ pinctrl-names = "default";
|
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+ vmmc-supply = <&vcc_sd>;
|
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+ status = "okay";
|
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+};
|
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+
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+&spi0 {
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+ status = "okay";
|
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+
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+ flash@0 {
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+ compatible = "jedec,spi-nor";
|
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+ reg = <0>;
|
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+ spi-max-frequency = <50000000>;
|
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+ };
|
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+};
|
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+
|
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+&tsadc {
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+ rockchip,hw-tshut-mode = <0>;
|
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+ rockchip,hw-tshut-polarity = <0>;
|
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+ status = "okay";
|
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+};
|
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+
|
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+&u2phy {
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+ status = "okay";
|
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+};
|
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+
|
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+&u2phy_host {
|
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+ status = "okay";
|
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+};
|
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+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- a/board/rockchip/evb_rk3328/MAINTAINERS
|
||||
+++ b/board/rockchip/evb_rk3328/MAINTAINERS
|
||||
@@ -18,6 +18,12 @@ F: configs/nanopi-r2s-rk3328_defcon
|
||||
F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
|
||||
F: arch/arm/dts/rk3328-nanopi-r2s.dts
|
||||
|
||||
+ORANGEPI-R1-PLUS-RK3328
|
||||
+M: Tianling Shen <cnsztl@gmail.com>
|
||||
+S: Maintained
|
||||
+F: configs/orangepi-r1-plus-rk3328_defconfig
|
||||
+F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
|
||||
+
|
||||
ROC-RK3328-CC
|
||||
M: Loic Devulder <ldevulder@suse.com>
|
||||
M: Chen-Yu Tsai <wens@csie.org>
|
||||
--- /dev/null
|
||||
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
|
||||
@@ -0,0 +1,98 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_SYS_TEXT_BASE=0x00200000
|
||||
+CONFIG_SPL_GPIO_SUPPORT=y
|
||||
+CONFIG_ENV_OFFSET=0x3F8000
|
||||
+CONFIG_ROCKCHIP_RK3328=y
|
||||
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
|
||||
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
|
||||
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
|
||||
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
+CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
+CONFIG_NR_DRAM_BANKS=1
|
||||
+CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_SYSINFO=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
+# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
|
||||
+CONFIG_MISC_INIT_R=y
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
|
||||
+CONFIG_SPL_STACK_R=y
|
||||
+CONFIG_SPL_I2C_SUPPORT=y
|
||||
+CONFIG_SPL_POWER_SUPPORT=y
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
|
||||
+CONFIG_CMD_BOOTZ=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+# CONFIG_CMD_SETEXPR is not set
|
||||
+CONFIG_CMD_TIME=y
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_TPL_OF_CONTROL=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_TPL_OF_PLATDATA=y
|
||||
+CONFIG_ENV_IS_IN_MMC=y
|
||||
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
+CONFIG_NET_RANDOM_ETHADDR=y
|
||||
+CONFIG_TPL_DM=y
|
||||
+CONFIG_REGMAP=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_TPL_REGMAP=y
|
||||
+CONFIG_SYSCON=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_TPL_SYSCON=y
|
||||
+CONFIG_CLK=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+CONFIG_FASTBOOT_BUF_ADDR=0x800800
|
||||
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_SF_DEFAULT_SPEED=20000000
|
||||
+CONFIG_DM_ETH=y
|
||||
+CONFIG_ETH_DESIGNWARE=y
|
||||
+CONFIG_GMAC_ROCKCHIP=y
|
||||
+CONFIG_PINCTRL=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_SPL_DM_REGULATOR=y
|
||||
+CONFIG_REGULATOR_PWM=y
|
||||
+CONFIG_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_SPL_DM_REGULATOR_FIXED=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_RAM=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_TPL_RAM=y
|
||||
+CONFIG_DM_RESET=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYSRESET=y
|
||||
+# CONFIG_TPL_SYSRESET is not set
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_XHCI_DWC3=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC2=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+# CONFIG_USB_DWC3_GADGET is not set
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
+CONFIG_SPL_TINY_MEMSET=y
|
||||
+CONFIG_TPL_TINY_MEMSET=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
@ -0,0 +1,24 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares externs for all device/uclass instances.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
|
||||
/* driver declarations - these allow DM_DRIVER_GET() to be used */
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
|
||||
extern U_BOOT_DRIVER(ns16550_serial);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
|
||||
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
|
||||
|
||||
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
|
||||
extern UCLASS_DRIVER(clk);
|
||||
extern UCLASS_DRIVER(mmc);
|
||||
extern UCLASS_DRIVER(ram);
|
||||
extern UCLASS_DRIVER(serial);
|
||||
extern UCLASS_DRIVER(syscon);
|
||||
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Declares the U_BOOT_DRIVER() records and platform data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
/* Allow use of U_BOOT_DRVINFO() in this file */
|
||||
#define DT_PLAT_C
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <dt-structs.h>
|
||||
|
||||
/*
|
||||
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
|
||||
*
|
||||
* idx driver_info driver
|
||||
* --- -------------------- --------------------
|
||||
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
|
||||
* 1: dmc rockchip_rk3328_dmc
|
||||
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
|
||||
* 3: serial_at_ff130000 ns16550_serial
|
||||
* 4: spi_at_ff190000 rockchip_rk3328_spi
|
||||
* 5: syscon_at_ff100000 rockchip_rk3328_grf
|
||||
* --- -------------------- --------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* Node /clock-controller@ff440000 index 0
|
||||
* driver rockchip_rk3328_cru parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
|
||||
.reg = {0xff440000, 0x1000},
|
||||
.rockchip_grf = 0x38,
|
||||
};
|
||||
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
|
||||
.name = "rockchip_rk3328_cru",
|
||||
.plat = &dtv_clock_controller_at_ff440000,
|
||||
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /dmc index 1
|
||||
* driver rockchip_rk3328_dmc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
|
||||
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
|
||||
0xff720000, 0x1000, 0xff798000, 0x1000},
|
||||
.rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
|
||||
0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
|
||||
0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
|
||||
0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
|
||||
0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
|
||||
0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
|
||||
0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
|
||||
0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
|
||||
0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
|
||||
0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
|
||||
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
|
||||
0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
|
||||
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
|
||||
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
|
||||
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
|
||||
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
|
||||
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
|
||||
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
|
||||
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
|
||||
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
|
||||
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
|
||||
0x77, 0x77, 0x79, 0x9},
|
||||
};
|
||||
U_BOOT_DRVINFO(dmc) = {
|
||||
.name = "rockchip_rk3328_dmc",
|
||||
.plat = &dtv_dmc,
|
||||
.plat_size = sizeof(dtv_dmc),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /mmc@ff500000 index 2
|
||||
* driver rockchip_rk3288_dw_mshc parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
|
||||
.bus_width = 0x4,
|
||||
.cap_sd_highspeed = true,
|
||||
.clocks = {
|
||||
{0, {317}},
|
||||
{0, {33}},
|
||||
{0, {74}},
|
||||
{0, {78}},},
|
||||
.disable_wp = true,
|
||||
.fifo_depth = 0x100,
|
||||
.interrupts = {0x0, 0xc, 0x4},
|
||||
.max_frequency = 0x8f0d180,
|
||||
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff500000, 0x4000},
|
||||
.u_boot_spl_fifo_mode = true,
|
||||
.vmmc_supply = 0x49,
|
||||
};
|
||||
U_BOOT_DRVINFO(mmc_at_ff500000) = {
|
||||
.name = "rockchip_rk3288_dw_mshc",
|
||||
.plat = &dtv_mmc_at_ff500000,
|
||||
.plat_size = sizeof(dtv_mmc_at_ff500000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /serial@ff130000 index 3
|
||||
* driver ns16550_serial parent None
|
||||
*/
|
||||
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
|
||||
.clock_frequency = 0x16e3600,
|
||||
.clocks = {
|
||||
{0, {40}},
|
||||
{0, {212}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x6, 0x10, 0x7},
|
||||
.interrupts = {0x0, 0x39, 0x4},
|
||||
.pinctrl_0 = 0x24,
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff130000, 0x100},
|
||||
.reg_io_width = 0x4,
|
||||
.reg_shift = 0x2,
|
||||
};
|
||||
U_BOOT_DRVINFO(serial_at_ff130000) = {
|
||||
.name = "ns16550_serial",
|
||||
.plat = &dtv_serial_at_ff130000,
|
||||
.plat_size = sizeof(dtv_serial_at_ff130000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/* Node /spi@ff190000 index 4 */
|
||||
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
|
||||
.clocks = {
|
||||
{0, {32}},
|
||||
{0, {209}},},
|
||||
.dma_names = {"tx", "rx"},
|
||||
.dmas = {0x10, 0x8, 0x10, 0x9},
|
||||
.interrupts = {0x0, 0x31, 0x4},
|
||||
.pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
|
||||
.pinctrl_names = "default",
|
||||
.reg = {0xff190000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(spi_at_ff190000) = {
|
||||
.name = "rockchip_rk3328_spi",
|
||||
.plat = &dtv_spi_at_ff190000,
|
||||
.plat_size = sizeof(dtv_spi_at_ff190000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Node /syscon@ff100000 index 5
|
||||
* driver rockchip_rk3328_grf parent None
|
||||
*/
|
||||
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
|
||||
.reg = {0xff100000, 0x1000},
|
||||
};
|
||||
U_BOOT_DRVINFO(syscon_at_ff100000) = {
|
||||
.name = "rockchip_rk3328_grf",
|
||||
.plat = &dtv_syscon_at_ff100000,
|
||||
.plat_size = sizeof(dtv_syscon_at_ff100000),
|
||||
.parent_idx = -1,
|
||||
};
|
||||
|
||||
@ -0,0 +1,55 @@
|
||||
/*
|
||||
* DO NOT MODIFY
|
||||
*
|
||||
* Defines the structs used to hold devicetree data.
|
||||
* This was generated by dtoc from a .dtb (device tree binary) file.
|
||||
*/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <linux/libfdt.h>
|
||||
struct dtd_ns16550_serial {
|
||||
fdt32_t clock_frequency;
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0;
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
fdt32_t reg_io_width;
|
||||
fdt32_t reg_shift;
|
||||
};
|
||||
struct dtd_rockchip_rk3288_dw_mshc {
|
||||
fdt32_t bus_width;
|
||||
bool cap_sd_highspeed;
|
||||
struct phandle_1_arg clocks[4];
|
||||
bool disable_wp;
|
||||
fdt32_t fifo_depth;
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t max_frequency;
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
bool u_boot_spl_fifo_mode;
|
||||
fdt32_t vmmc_supply;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_cru {
|
||||
fdt64_t reg[2];
|
||||
fdt32_t rockchip_grf;
|
||||
};
|
||||
struct dtd_rockchip_rk3328_dmc {
|
||||
fdt64_t reg[12];
|
||||
fdt32_t rockchip_sdram_params[196];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_grf {
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
struct dtd_rockchip_rk3328_spi {
|
||||
struct phandle_1_arg clocks[2];
|
||||
const char * dma_names[2];
|
||||
fdt32_t dmas[4];
|
||||
fdt32_t interrupts[3];
|
||||
fdt32_t pinctrl_0[4];
|
||||
const char * pinctrl_names;
|
||||
fdt64_t reg[2];
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user