openwrt/target/linux/mediatek/dts/mt7986a-acer-w6-common.dtsi

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mediatek: split Acer/W6 dts into W6 common dtsi and device specific dts In order to prepare OpenWrt support for other Acer W6 devices, this commit moves all device tree components that are used by all Acer W6/W6e/W6d/W6m routers from mt7986a-acer-predator-w6.dts to mt7986a-acer-w6-common.dtsi (new file) and includes this dtsi file in mt7986a-acer-predator-w6.dts. Minor changes had to be made to the device tree in order to improve clarity and – notably – to reduce the number of dtc warnings: - replace (obviously wrong) led@<N> gpio led entities by led-<N> - remove unnecessary (default-state = "off") gpio led statements - rename entity “memory” to “memory@0” - add missing #address-cells and #address-size in /soc/mmc@11230000 - add missing #address-cells and #address-size in /soc/pcie@11280000 - introduce symbols “nvmem” and “swport0” in dtsi (referenced in dts) The changes were checked with `diff -BEZbdtwy --suppress-common-lines ...` (comparing two dts files created using old and new fdt-1 blobs again), see https://github.com/openwrt/openwrt/pull/16861/#issuecomment-2455680020 . This is the first of four commits into which the original commit was split to make reviews easier and more targeted. Signed-off-by: George Oldfort <openwrt@10099.de> Link: https://github.com/openwrt/openwrt/pull/16861 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> (cherry picked from commit ce3b36b3d5374709b9b091390cb9053657be17fa) Link: https://github.com/openwrt/openwrt/pull/17097 Signed-off-by: Petr Štetiar <ynezz@true.cz>
2024-11-11 08:25:56 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "mt7986a.dtsi"
/ {
chosen {
stdout-path = "serial0:115200n8";
bootargs = "dm-mod.create=\"dm-verity,,,ro,0 31544 verity 1 PARTLABEL=rootfs PARTLABEL=rootfs 4096 4096 3943 3944 sha256 2f969fa9e9e4e20b37746f22633e85b178f5db7c143e11f92733a704299cc933 2dd56e34b15c6c84573cf26c4392028421061d2c808975217b45e9a5b49d2087\" rootfstype=squashfs,ext4 rootwait root=/dev/mmcblk0p6 fstools_ignore_partname=1";
};
memory@0 {
reg = <0 0x40000000 0 0x20000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "fixed-5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
};
gpio-keys {
compatible = "gpio-keys";
factory {
label = "factory";
linux,code = <KEY_RESTART>;
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&pio 10 GPIO_ACTIVE_LOW>;
};
};
};
&watchdog {
status = "okay";
};
&pio {
mmc0_pins_default: mmc0-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
mmc0_pins_uhs: mmc0-uhs-pins {
mux {
function = "emmc";
groups = "emmc_51";
};
conf-cmd-dat {
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
input-enable;
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
conf-clk {
pins = "EMMC_CK";
drive-strength = <6>;
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-ds {
pins = "EMMC_DSL";
mediatek,pull-down-adv = <2>; /* pull-down 50K */
};
conf-rst {
pins = "EMMC_RSTB";
drive-strength = <4>;
mediatek,pull-up-adv = <1>; /* pull-up 10K */
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_pereset";
};
};
wf_2g_5g_pins: wf_2g_5g-pins {
mux {
function = "wifi";
groups = "wf_2g", "wf_5g";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
wf_dbdc_pins: wf-dbdc-pins {
mux {
function = "wifi";
groups = "wf_dbdc";
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <4>;
};
};
};
&trng {
status = "okay";
};
&crypto {
status = "okay";
};
&uart0 {
status = "okay";
};
&mmc0 {
status = "okay";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-1 = <&mmc0_pins_uhs>;
bus-width = <0x08>;
max-frequency = <200000000>;
cap-mmc-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
hs400-ds-delay = <0x14014>;
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
non-removable;
no-sd;
no-sdio;
#address-cells = <1>;
#size-cells = <0>;
card@0 {
compatible = "mmc-card";
reg = <0>;
block {
compatible = "block-device";
partitions {
block-partition-factory {
partname = "factory";
nvmem: nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x1000>;
};
};
};
};
};
};
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
status = "okay";
slot0: pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <0x03>;
#size-cells = <0x02>;
};
};
&pcie_phy {
status = "okay";
};
&eth {
status = "okay";
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
reg = <0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
switch: switch@1f {
compatible = "mediatek,mt7531";
reg = <31>;
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
swport0: port@0 {
reg = <0>;
phy-handle = <&swphy0>;
};
port@1 {
reg = <1>;
label = "lan1";
phy-handle = <&swphy1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&swphy2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-handle = <&swphy3>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
swphy0: phy@0 {
reg = <0>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
swphy1: phy@1 {
reg = <1>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
swphy2: phy@2 {
reg = <2>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
swphy3: phy@3 {
reg = <3>;
mediatek,led-config = <
0x21 0x8009 /* BASIC_CTRL */
0x22 0x0c00 /* ON_DURATION */
0x23 0x1400 /* BLINK_DURATION */
0x24 0xc001 /* LED0_ON_CTRL */
0x25 0x0000 /* LED0_BLINK_CTRL */
0x26 0xc007 /* LED1_ON_CTRL */
0x27 0x003f /* LED1_BLINK_CTRL */
>;
};
};
};
};
};
&wifi {
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
status = "okay";
};