2022-02-04 13:57:50 +00:00
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From 3f55310c00b8c478da1458704027036c1a414973 Mon Sep 17 00:00:00 2001
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From: Claudiu Beznea <claudiu.beznea@microchip.com>
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Date: Thu, 15 Apr 2021 13:50:03 +0300
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Subject: [PATCH 212/247] ARM: at91: pm: add sama7g5 ddr controller
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Add SAMA7G5 DDR controller to the list of DDR controller compatibles.
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At the moment there is no standby support. Adapt the code for this.
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Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
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Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com
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---
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arch/arm/mach-at91/pm.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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--- a/arch/arm/mach-at91/pm.c
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+++ b/arch/arm/mach-at91/pm.c
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2022-03-02 13:11:44 +00:00
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@@ -548,6 +548,7 @@ static const struct of_device_id ramc_id
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2022-02-04 13:57:50 +00:00
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{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
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{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
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{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
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+ { .compatible = "microchip,sama7g5-uddrc", },
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{ /*sentinel*/ }
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};
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@@ -569,9 +570,11 @@ static __init int at91_dt_ramc(void)
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}
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ramc = of_id->data;
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- if (!standby)
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- standby = ramc->idle;
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- soc_pm.data.memctrl = ramc->memctrl;
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+ if (ramc) {
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+ if (!standby)
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+ standby = ramc->idle;
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+ soc_pm.data.memctrl = ramc->memctrl;
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+ }
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idx++;
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}
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