2022-01-10 01:12:45 +00:00
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From a29a7d01cd778854e08108461cba321a63d98871 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 2 Jul 2021 16:39:47 +0200
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Subject: [PATCH] PCI: aardvark: Fix reading MSI interrupt number
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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In advk_pcie_handle_msi() the authors expect that when bit i in the W1C
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register PCIE_MSI_STATUS_REG is cleared, the PCIE_MSI_PAYLOAD_REG is
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updated to contain the MSI number corresponding to index i.
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Experiments show that this is not so, and instead PCIE_MSI_PAYLOAD_REG
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always contains the number of the last received MSI, overall.
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Do not read PCIE_MSI_PAYLOAD_REG register for determining MSI interrupt
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number. Since Aardvark already forbids more than 32 interrupts and uses
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own allocated hwirq numbers, the msi_idx already corresponds to the
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received MSI number.
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Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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---
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drivers/pci/controller/pci-aardvark.c | 13 ++++++-------
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1 file changed, 6 insertions(+), 7 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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2022-01-16 12:53:21 +00:00
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@@ -1391,7 +1391,7 @@ static void advk_pcie_remove_irq_domain(
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2022-01-10 01:12:45 +00:00
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static void advk_pcie_handle_msi(struct advk_pcie *pcie)
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{
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u32 msi_val, msi_mask, msi_status, msi_idx;
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- u16 msi_data;
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+ int virq;
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msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
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msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
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2022-01-16 12:53:21 +00:00
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@@ -1401,13 +1401,12 @@ static void advk_pcie_handle_msi(struct
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2022-01-10 01:12:45 +00:00
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if (!(BIT(msi_idx) & msi_status))
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continue;
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- /*
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- * msi_idx contains bits [4:0] of the msi_data and msi_data
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- * contains 16bit MSI interrupt number
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- */
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advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
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- msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
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- generic_handle_irq(msi_data);
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+ virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx);
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+ if (virq)
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+ generic_handle_irq(virq);
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+ else
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+ dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
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}
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advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
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