2022-10-21 21:55:37 +00:00
|
|
|
From 73a78b6130d9e13daca22b86ad52f063b9403e03 Mon Sep 17 00:00:00 2001
|
2021-11-04 20:52:43 +00:00
|
|
|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
2022-10-21 21:55:37 +00:00
|
|
|
Date: Wed, 8 Dec 2021 03:40:35 +0100
|
|
|
|
|
Subject: [PATCH 1/1] arm64: dts: marvell: armada-37xx: Add xtal clock to
|
|
|
|
|
comphy node
|
2021-11-04 20:52:43 +00:00
|
|
|
MIME-Version: 1.0
|
|
|
|
|
Content-Type: text/plain; charset=UTF-8
|
|
|
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
|
|
|
|
|
|
Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the
|
|
|
|
|
reference xtal clock. So add missing xtal clock source into comphy device
|
|
|
|
|
tree node. If the property is not present, the driver defaults to 25 MHz
|
|
|
|
|
xtal rate (which, as far as we know, is used by all the existing boards).
|
|
|
|
|
|
|
|
|
|
Signed-off-by: Pali Rohár <pali@kernel.org>
|
|
|
|
|
Signed-off-by: Marek Behún <kabel@kernel.org>
|
2022-10-21 21:55:37 +00:00
|
|
|
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
2021-11-04 20:52:43 +00:00
|
|
|
---
|
|
|
|
|
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++
|
|
|
|
|
1 file changed, 2 insertions(+)
|
|
|
|
|
|
|
|
|
|
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
|
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
|
|
|
@@ -265,6 +265,8 @@
|
|
|
|
|
"lane2_sata_usb3";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
+ clocks = <&xtalclk>;
|
|
|
|
|
+ clock-names = "xtal";
|
|
|
|
|
|
|
|
|
|
comphy0: phy@0 {
|
|
|
|
|
reg = <0>;
|
