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90 lines
3.1 KiB
Diff
90 lines
3.1 KiB
Diff
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From caf32f96f13df7d3ae6cb8bf8001c88ae22025ca Mon Sep 17 00:00:00 2001
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From: Russell King <rmk+kernel@armlinux.org.uk>
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Date: Fri, 8 Nov 2019 15:28:22 +0000
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Subject: [PATCH 650/660] net: phylink: support Clause 45 PHYs on SFP+ modules
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Some SFP+ modules have Clause 45 PHYs embedded on them, which need a
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little more handling in order to ensure that they are correctly setup,
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as they switch the PHY link mode according to the negotiated speed.
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With Clause 22 PHYs, we assumed that they would operate in SGMII mode,
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but this assumption is now false. Adapt phylink to support Clause 45
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PHYs on SFP+ modules.
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Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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---
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drivers/net/phy/phylink.c | 21 ++++++++++++++++-----
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1 file changed, 16 insertions(+), 5 deletions(-)
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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@@ -671,7 +671,8 @@ static void phylink_phy_change(struct ph
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phy_duplex_to_str(phydev->duplex));
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}
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-static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy)
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+static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy,
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+ phy_interface_t interface)
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{
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struct phylink_link_state config;
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__ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
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@@ -691,7 +692,7 @@ static int phylink_bringup_phy(struct ph
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ethtool_convert_legacy_u32_to_link_mode(supported, phy->supported);
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ethtool_convert_legacy_u32_to_link_mode(config.advertising,
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phy->advertising);
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- config.interface = pl->link_config.interface;
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+ config.interface = interface;
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ret = phylink_validate(pl, supported, &config);
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if (ret)
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@@ -707,6 +708,7 @@ static int phylink_bringup_phy(struct ph
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mutex_lock(&phy->lock);
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mutex_lock(&pl->state_mutex);
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pl->phydev = phy;
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+ pl->phy_state.interface = interface;
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linkmode_copy(pl->supported, supported);
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linkmode_copy(pl->link_config.advertising, config.advertising);
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@@ -771,7 +773,7 @@ int phylink_connect_phy(struct phylink *
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if (ret < 0)
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return ret;
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- ret = phylink_bringup_phy(pl, phy);
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+ ret = phylink_bringup_phy(pl, phy, pl->link_config.interface);
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if (ret)
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phy_detach(phy);
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@@ -824,7 +826,7 @@ int phylink_of_phy_connect(struct phylin
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if (!phy_dev)
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return -ENODEV;
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- ret = phylink_bringup_phy(pl, phy_dev);
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+ ret = phylink_bringup_phy(pl, phy_dev, pl->link_config.interface);
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if (ret)
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phy_detach(phy_dev);
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@@ -1759,13 +1761,22 @@ static void phylink_sfp_link_up(void *up
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static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
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{
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struct phylink *pl = upstream;
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+ phy_interface_t interface = pl->link_config.interface;
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int ret;
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ret = phylink_attach_phy(pl, phy, pl->link_config.interface);
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if (ret < 0)
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return ret;
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- ret = phylink_bringup_phy(pl, phy);
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+ /* Clause 45 PHYs switch their Serdes lane between several different
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+ * modes, normally 10GBASE-R, SGMII. Some use 2500BASE-X for 2.5G
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+ * speeds. We really need to know which interface modes the PHY and
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+ * MAC supports to properly work out which linkmodes can be supported.
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+ */
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+ if (phy->is_c45)
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+ interface = PHY_INTERFACE_MODE_NA;
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+
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+ ret = phylink_bringup_phy(pl, phy, interface);
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if (ret)
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phy_detach(phy);
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