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48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
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From e27072851bf7d706c592fc528549b52023b17a09 Mon Sep 17 00:00:00 2001
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From: Andy Yan <andy.yan@rock-chips.com>
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Date: Mon, 28 Aug 2017 09:58:29 +0800
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Subject: [PATCH 1/2] mtd: spi-nor: add a quad_enable callback in struct
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flash_info
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Some manufacturers may use different bit to set QE on different
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memories.
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The GD25Q256 from GigaDevice is an example, which uses S6(bit 6
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of the Status Register-1) to set QE, which is different with
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other supported memories from GigaDevice that use S9(bit 1 of
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the Status Register-2). This makes it is impossible to select
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the quad enable method by distinguishing the MFR. This patch
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introduce a quad_enable function which can be set per memory
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in the flash_info list table.
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Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
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Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -89,6 +89,8 @@ struct flash_info {
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#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
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#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
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#define USE_CLSR BIT(14) /* use CLSR command */
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+
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+ int (*quad_enable)(struct spi_nor *nor);
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};
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#define JEDEC_MFR(info) ((info)->id[0])
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@@ -2433,6 +2435,15 @@ static int spi_nor_init_params(struct sp
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params->quad_enable = spansion_quad_enable;
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break;
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}
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+
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+ /*
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+ * Some manufacturer like GigaDevice may use different
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+ * bit to set QE on different memories, so the MFR can't
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+ * indicate the quad_enable method for this case, we need
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+ * set it in flash info list.
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+ */
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+ if (info->quad_enable)
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+ params->quad_enable = info->quad_enable;
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}
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/* Override the parameters with data read from SFDP tables. */
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