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openwrt/target/linux/realtek/dts-5.10/rtl8393_d-link_dgs-1210-52.dts

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realtek: add support for DGS-1210-52 Hardware specification ---------------------- * RTL8393M SoC, 1 MIPS 34Kc core @ 700MHz * 128MB DRAM * 32MB NOR Flash * 48 x 10/100/1000BASE-T ports - 6 x External PHY with 8 ports (RTL8218D) * 4 x Gigabit RJ45/SFP Combo ports - External PHY with 4 SFP ports (RTL8214FC) * Power LED * Reset button on front panel * UART (115200 8N1) via unpopulated standard 0.1" pin header marked J14 The gpio-restart node is not required but it does reset the switch. TODO: The 4 combo ports attached to the RTL8214FC are not detect properly. Linux kernel reports 49 and 50 as "External RTL8393 SERDES" and 51 and 52 as "RTL8218B (external)". Those ports only work if u-boot initialize it (for example, loading initramfs image using one of those ports). A patch to PHY detection is needed for full support. The firmware recovery using U-Boot is broken for all DGS-1210 tested devices as pressing RESET does not trigger it (only if pressed from a running stock image) UART pinout ----------- [o]ooo|J14 | ||`------ GND | |`------- RX | `-------- TX `---------- Vcc (3V3) Installation using OEM upgrade ------------------------------ 1. Make sure you are running OEM firmware in image2 slot (logged as admin): - > config firmware image_id 2 boot_up - > reboot 2. Install squashfs-factory_image1.bin to image1 using (logged as admin): - > download firmware_fromTFTP <tftpserver> factory_image1.bin - > config firmware image_id 1 boot_up - > reboot Installation using serial interface ----------------------------------- 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. Press CTRL+C keys to get into real U-Boot prompt 3. Init network with `rtk network on` command 4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl839x-d-link_dgs-1210-52-initramfs-kernel.bin` command 5. Boot the image with `bootm` command Once booted the initramfs, install the squashfs-sysupgrade.bin as a normal OpenWrt system. Dual-boot with stock firmware using writable u-boot-env ------------------------------------------------------- From stock to OpenWrt / boot image 1 (CLI as admin): - > config firmware image_id 1 boot_up - > reboot From OpenWrt to stock / boot image 2: (shell as root) - # fw_setenv bootcmd 'run addargs ; bootm 0xb4e80000' - # fw_setenv image '/dev/mtdblock7' - # reboot Debrick using serial interface ------------------------------ 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should detect the switch 3. Flash the firmware. Back to stock firmware using dual-boot -------------------------------------- If you have serial interface, you can change u-boot env vars interrupting the boot process. If not but you are running OpenWrt, you can dual-boot (as mentioned eariler) and skip to step 4: 1. Press Escape key during `Hit Esc key to stop autoboot` prompt 2. Press CTRL+C keys to get into real U-Boot prompt 3. Boot the image 2: - set image /dev/mtdblock7; run addargs; bootm 0xb4e80000 4. Once booted, log as admin and change the boot image to 2 - > config firmware image_id 2 boot_up - > reboot 5. After the boot, flash image1 with the vendor image Back to stock firmware using DNA -------------------------------- 1. From an OpenWrt: - # fw_setenv bootstop on - # reboot 2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should detect the switch 3. Flash the firmware. It has been developed and tested on device with F3 revision. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-09-17 17:12:19 +00:00
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rtl839x.dtsi"
#include "rtl83xx_d-link_dgs-1210_common.dtsi"
#include "rtl83xx_d-link_dgs-1210_gpio.dtsi"
#include "rtl839x_d-link_dgs-1210_gpio.dtsi"
/ {
compatible = "d-link,dgs-1210-52", "realtek,rtl8393-soc";
model = "D-Link DGS-1210-52";
};
&ethernet0 {
mdio: mdio-bus {
compatible = "realtek,rtl838x-mdio";
regmap = <&ethernet0>;
#address-cells = <1>;
#size-cells = <0>;
/* External phy RTL8218B #1 */
EXTERNAL_PHY(0)
EXTERNAL_PHY(1)
EXTERNAL_PHY(2)
EXTERNAL_PHY(3)
EXTERNAL_PHY(4)
EXTERNAL_PHY(5)
EXTERNAL_PHY(6)
EXTERNAL_PHY(7)
/* External phy RTL8218B #2 */
EXTERNAL_PHY(8)
EXTERNAL_PHY(9)
EXTERNAL_PHY(10)
EXTERNAL_PHY(11)
EXTERNAL_PHY(12)
EXTERNAL_PHY(13)
EXTERNAL_PHY(14)
EXTERNAL_PHY(15)
/* External phy RTL8218B #3 */
EXTERNAL_PHY(16)
EXTERNAL_PHY(17)
EXTERNAL_PHY(18)
EXTERNAL_PHY(19)
EXTERNAL_PHY(20)
EXTERNAL_PHY(21)
EXTERNAL_PHY(22)
EXTERNAL_PHY(23)
/* External phy RTL8218B #4 */
EXTERNAL_PHY(24)
EXTERNAL_PHY(25)
EXTERNAL_PHY(26)
EXTERNAL_PHY(27)
EXTERNAL_PHY(28)
EXTERNAL_PHY(29)
EXTERNAL_PHY(30)
EXTERNAL_PHY(31)
/* External phy RTL8218B #5 */
EXTERNAL_PHY(32)
EXTERNAL_PHY(33)
EXTERNAL_PHY(34)
EXTERNAL_PHY(35)
EXTERNAL_PHY(36)
EXTERNAL_PHY(37)
EXTERNAL_PHY(38)
EXTERNAL_PHY(39)
/* External phy RTL8218B #6 */
EXTERNAL_PHY(40)
EXTERNAL_PHY(41)
EXTERNAL_PHY(42)
EXTERNAL_PHY(43)
EXTERNAL_PHY(44)
EXTERNAL_PHY(45)
EXTERNAL_PHY(46)
EXTERNAL_PHY(47)
/* External phy RTL8214FC */
EXTERNAL_SFP_PHY_FULL(48, 0)
EXTERNAL_SFP_PHY_FULL(49, 1)
EXTERNAL_SFP_PHY_FULL(50, 2)
EXTERNAL_SFP_PHY_FULL(51, 3)
};
};
&switch0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii)
SWITCH_PORT(1, 2, qsgmii)
SWITCH_PORT(2, 3, qsgmii)
SWITCH_PORT(3, 4, qsgmii)
SWITCH_PORT(4, 5, qsgmii)
SWITCH_PORT(5, 6, qsgmii)
SWITCH_PORT(6, 7, qsgmii)
SWITCH_PORT(7, 8, qsgmii)
SWITCH_PORT(8, 9, qsgmii)
SWITCH_PORT(9, 10, qsgmii)
SWITCH_PORT(10, 11, qsgmii)
SWITCH_PORT(11, 12, qsgmii)
SWITCH_PORT(12, 13, qsgmii)
SWITCH_PORT(13, 14, qsgmii)
SWITCH_PORT(14, 15, qsgmii)
SWITCH_PORT(15, 16, qsgmii)
SWITCH_PORT(16, 17, qsgmii)
SWITCH_PORT(17, 18, qsgmii)
SWITCH_PORT(18, 19, qsgmii)
SWITCH_PORT(19, 20, qsgmii)
SWITCH_PORT(20, 21, qsgmii)
SWITCH_PORT(21, 22, qsgmii)
SWITCH_PORT(22, 23, qsgmii)
SWITCH_PORT(23, 24, qsgmii)
SWITCH_PORT(24, 25, qsgmii)
SWITCH_PORT(25, 26, qsgmii)
SWITCH_PORT(26, 27, qsgmii)
SWITCH_PORT(27, 28, qsgmii)
SWITCH_PORT(28, 29, qsgmii)
SWITCH_PORT(29, 30, qsgmii)
SWITCH_PORT(30, 31, qsgmii)
SWITCH_PORT(31, 32, qsgmii)
SWITCH_PORT(32, 33, qsgmii)
SWITCH_PORT(33, 34, qsgmii)
SWITCH_PORT(34, 35, qsgmii)
SWITCH_PORT(35, 36, qsgmii)
SWITCH_PORT(36, 37, qsgmii)
SWITCH_PORT(37, 38, qsgmii)
SWITCH_PORT(38, 39, qsgmii)
SWITCH_PORT(39, 40, qsgmii)
SWITCH_PORT(40, 41, qsgmii)
SWITCH_PORT(41, 42, qsgmii)
SWITCH_PORT(42, 43, qsgmii)
SWITCH_PORT(43, 44, qsgmii)
SWITCH_PORT(44, 45, qsgmii)
SWITCH_PORT(45, 46, qsgmii)
SWITCH_PORT(46, 47, qsgmii)
SWITCH_PORT(47, 48, qsgmii)
SWITCH_PORT(48, 49, qsgmii)
SWITCH_PORT(49, 50, qsgmii)
SWITCH_PORT(50, 51, qsgmii)
SWITCH_PORT(51, 52, qsgmii)
/* CPU-Port */
port@52 {
ethernet = <&ethernet0>;
reg = <52>;
phy-mode = "qsgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
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