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105 lines
4.4 KiB
Diff
105 lines
4.4 KiB
Diff
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From da58a931f248f423f917c3a0b3c94303aa30a738 Mon Sep 17 00:00:00 2001
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From: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Date: Tue, 25 Sep 2018 15:59:39 +0200
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Subject: [PATCH] net: mvneta: Add support for 2500Mbps SGMII
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The mvneta controller can handle speeds up to 2500Mbps on the SGMII
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interface. This relies on serdes configuration, the lane must be
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configured at 3.125Gbps and we can't use in-band autoneg at that speed.
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The main issue when supporting that speed on this particular controller
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is that the link partner can send ethernet frames with a shortened
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preamble, which if not explicitly enabled in the controller will cause
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unexpected behaviours.
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This was tested on Armada 385, with the comphy configuration done in
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bootloader.
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Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/marvell/mvneta.c | 27 +++++++++++++++++++++++----
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1 file changed, 23 insertions(+), 4 deletions(-)
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--- a/drivers/net/ethernet/marvell/mvneta.c
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+++ b/drivers/net/ethernet/marvell/mvneta.c
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@@ -221,6 +221,8 @@
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#define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
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#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
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+#define MVNETA_GMAC_CTRL_4 0x2c90
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+#define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
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#define MVNETA_MIB_COUNTERS_BASE 0x3000
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#define MVNETA_MIB_LATE_COLLISION 0x7c
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#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
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@@ -3344,6 +3346,7 @@ static void mvneta_validate(struct net_d
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if (state->interface != PHY_INTERFACE_MODE_NA &&
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state->interface != PHY_INTERFACE_MODE_QSGMII &&
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state->interface != PHY_INTERFACE_MODE_SGMII &&
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+ state->interface != PHY_INTERFACE_MODE_2500BASEX &&
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!phy_interface_mode_is_8023z(state->interface) &&
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!phy_interface_mode_is_rgmii(state->interface)) {
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bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
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@@ -3356,9 +3359,15 @@ static void mvneta_validate(struct net_d
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/* Asymmetric pause is unsupported */
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phylink_set(mask, Pause);
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- /* Half-duplex at speeds higher than 100Mbit is unsupported */
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- phylink_set(mask, 1000baseT_Full);
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- phylink_set(mask, 1000baseX_Full);
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+
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+ /* We cannot use 1Gbps when using the 2.5G interface. */
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+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
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+ phylink_set(mask, 2500baseT_Full);
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+ phylink_set(mask, 2500baseX_Full);
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+ } else {
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+ phylink_set(mask, 1000baseT_Full);
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+ phylink_set(mask, 1000baseX_Full);
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+ }
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if (!phy_interface_mode_is_8023z(state->interface)) {
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/* 10M and 100M are only supported in non-802.3z mode */
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@@ -3419,12 +3428,14 @@ static void mvneta_mac_config(struct net
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struct mvneta_port *pp = netdev_priv(ndev);
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u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
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u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
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+ u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
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u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
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u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
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new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
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new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
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MVNETA_GMAC2_PORT_RESET);
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+ new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
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new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
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new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
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MVNETA_GMAC_INBAND_RESTART_AN |
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@@ -3457,7 +3468,7 @@ static void mvneta_mac_config(struct net
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if (state->duplex)
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new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
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- if (state->speed == SPEED_1000)
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+ if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
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new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
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else if (state->speed == SPEED_100)
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new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
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@@ -3496,10 +3507,18 @@ static void mvneta_mac_config(struct net
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MVNETA_GMAC_FORCE_LINK_DOWN);
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}
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+ /* When at 2.5G, the link partner can send frames with shortened
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+ * preambles.
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+ */
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+ if (state->speed == SPEED_2500)
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+ new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
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+
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if (new_ctrl0 != gmac_ctrl0)
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mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
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if (new_ctrl2 != gmac_ctrl2)
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mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
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+ if (new_ctrl4 != gmac_ctrl4)
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+ mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
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if (new_clk != gmac_clk)
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mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
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if (new_an != gmac_an)
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