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47 lines
1.8 KiB
Diff
47 lines
1.8 KiB
Diff
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From ae5d39403c61f4ed691a0a8d94673210475242be Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Tue, 15 Aug 2017 16:47:18 -0700
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Subject: [PATCH 204/454] drm/vc4: Move the DSI clock divider workaround closer
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to the clock call.
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We want the adjusted_mode->clock to be the actual clock we're
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expecting to program, so that consumers see the right values for clock
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and vrefresh.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Link: https://patchwork.freedesktop.org/patch/msgid/20170815234722.20700-1-eric@anholt.net
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Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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(cherry picked from commit d409eeafa9ba1c0f2eb75a2619fc787808a545e4)
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -864,11 +864,7 @@ static bool vc4_dsi_encoder_mode_fixup(s
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pll_clock = parent_rate / divider;
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pixel_clock_hz = pll_clock / dsi->divider;
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- /* Round up the clk_set_rate() request slightly, since
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- * PLLD_DSI1 is an integer divider and its rate selection will
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- * never round up.
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- */
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- adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
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+ adjusted_mode->clock = pixel_clock_hz / 1000;
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/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
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adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
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@@ -906,7 +902,11 @@ static void vc4_dsi_encoder_enable(struc
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vc4_dsi_dump_regs(dsi);
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}
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- phy_clock = pixel_clock_hz * dsi->divider;
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+ /* Round up the clk_set_rate() request slightly, since
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+ * PLLD_DSI1 is an integer divider and its rate selection will
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+ * never round up.
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+ */
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+ phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
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ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
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if (ret) {
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dev_err(&dsi->pdev->dev,
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