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27 lines
969 B
Diff
27 lines
969 B
Diff
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From 916c79dc5a1df708d6984f5e964eaa3de7e130f2 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 22 Oct 2021 16:48:50 +0100
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Subject: [PATCH] drm/vc4: dsi: Correct max divider to 255 (not 7)
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The integer divider from parent PLL to DSI clock is capable
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of going up to /255, not just /7 that the driver was trying.
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This allows for slower link frequencies on the DSI bus where
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the resolution permits.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_dsi.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_dsi.c
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+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
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@@ -850,7 +850,7 @@ static bool vc4_dsi_encoder_mode_fixup(s
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/* Find what divider gets us a faster clock than the requested
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* pixel clock.
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*/
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- for (divider = 1; divider < 7; divider++) {
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+ for (divider = 1; divider < 255; divider++) {
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if (parent_rate / (divider + 1) < pll_clock)
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break;
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}
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